School of Computing and Information Technology

UNIT-2
Instruction Set Of 8086
Microprocessor

Presenter: Prof. Ravatappa A B

Email :[email protected]
Outline:

Review of Pre-requisites
Topic for the day
Objective and Outcome of Lecture
Instruction Set of 8086 Microprocessor
Lecture
Discussion Assembly language programming

Stack structure of 8086, Interrupt cycle of 8086 and Macros

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Topic for the Lecture:

Instruction Set of 8086 Microprocessor

Assembly language programming

Stack structure of 8086, Interrupt cycle of 8086 and Macros

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Objective and Outcome of
Lecture:

• Illustrate 8086 assembly language

Lecture Objective Interrupt based real time
applications.

• Make use of addressing modes

Lecture Outcome and instructions formats of 8086
architecture .
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Chapter 03

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 Instruction Set of 8086
An instruction is a binary pattern
designed inside a microprocessor to
perform a specific function.
The entire group of instructions that
a microprocessor supports is called
Instruction Set.
8086 has more than 20,000
instructions.
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 Classification of Instruction Set
1. Arithmetic Instructions and Logical
Instruction
2. Data Transfer Instructions
3. Branch and Loop Instruction
4. M/C control Instruction
5. Flag Manipulation Instructions
6. Shift and Rotate Instruction
7. String Instructions

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1. Arithmetic And Logical
Instructions
 Arithmetic Instructions
ADD Des, Src:
It adds a byte to byte or a word to word.
It effects AF, CF, OF, PF, SF, ZF flags.
E.g.:
ADD AL, 74H
ADD DX, AX
ADD AX, [BX]

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 Arithmetic Instructions
ADC Des, Src:
It adds the two operands with CF.
It effects AF, CF, OF, PF, SF, ZF flags.
E.g.:
ADC AL, 74H
ADC DX, AX
ADC AX, [BX]

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 Arithmetic Instructions
SUB Des, Src:
It subtracts a byte from byte or a word
from word.
It effects AF, CF, OF, PF, SF, ZF flags.
For subtraction, CF acts as borrow flag.
E.g.:
SUB AL, 74H
SUB DX, AX
SUB AX, [BX]
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 Arithmetic Instructions
SBB Des, Src:
It subtracts the two operands and also
the borrow from the result.
It effects AF, CF, OF, PF, SF, ZF flags.
E.g.:
SBB AL, 74H
SBB DX, AX
SBB AX, [BX]

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 Arithmetic Instructions
MUL Src:
It is an unsigned multiplication instruction.
It multiplies two bytes to produce a word or two
words to produce a double word.
AX = AL * Src
DX : AX = AX * Src
This instruction assumes one of the operand in AL or
AX.
Src can be a register or memory location. And Flags-
OF, CF
Unused bits of destination register is always filled
with sign bit
IMUL Src:
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 Arithmetic Instructions
DIV Src:
It is an unsigned division instruction.
It divides word by byte or double word
by word.
The operand is stored in AX, divisor is
Src and the result is stored as:
AH = remainder, AL = quotient (for
word/byte)
DX=remainder, AX=quotient (for
D-word/word)
IDIV Src:
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 Arithmetic Instructions
CBW (Convert Byte to Word):
This instruction converts byte in AL to word in
AX.
The conversion is done by extending the sign
bit of AL throughout AH.
CWD (Convert Word to Double Word):
This instruction converts word in AX to double
word in DX : AX.
The conversion is done by extending the sign
bit of AX throughout DX.
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 Arithmetic Instructions
INC Src:
It increments the byte or word by one.
The operand can be a register or
memory location.
E.g.: INC AX
INC [SI]

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 Arithmetic Instructions
DEC Src:
It decrements the byte or word by one.
The operand can be a register or
memory location.
E.g.: DEC AX

DEC [SI]

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 Arithmetic Instructions
CMP Des, Src:
It compares two specified bytes or words.
The Src and Des can be a constant, register or
memory location.
Both operands cannot be a memory location at
the same time.
The comparison is done simply by internally
subtracting the source from destination.
The value of source and destination does not
change, but the flags CF, ZF, SF are modified to
indicate the result.

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 Arithmetic Instructions
NEG Src:
It creates 2’s complement of a
given number.
That means, it changes the sign of
a number.

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 Arithmetic Instructions
DAA (Decimal Adjust after Addition)
It is used to make sure that the result of
adding two BCD numbers is adjusted to be a
correct BCD number.
It only works on AL register.

For Subtraction : DAS (Decimal Adjust

after Subtraction)

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 Arithmetic Instructions
AAA (ASCII Adjust after Addition):
This Instruction Can be used to convert the
contents of the AL register to unpacked BCD result
i.e. If lower nibble of AL>9 then
1. AL=AL+6 2. AH=AH+1
3. AL=AL AND 0FH
This instruction does not have any operand.
Other ASCII Instructions:
AAS (ASCII Adjust after Subtraction)
AAM (ASCII Adjust after Multiplication)
AAD (ASCII Adjust Before Division)
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 Logical Instructions
NOT Src:
It complements each bit of Src to produce 1’s
complement of the specified operand.
The operand can be a register or memory
location.
e,.g NOT AX

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 Logical Instructions
AND Des, Src:
It performs AND operation of Des and Src.
Src can be immediate number, register or
memory location.
Des can be register or memory location.
Both operands cannot be memory locations at
the same time.
CF and OF become zero after the operation.
PF, SF and ZF are updated.

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 Bit Manipulation Instructions
OR Des, Src:
It performs OR operation of Des and Src.
Src can be immediate number, register or
memory location.
Des can be register or memory location.
Both operands cannot be memory locations at
the same time.
CF and OF become zero after the operation.
PF, SF and ZF are updated.

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 Bit Manipulation Instructions
XOR Des, Src:
It performs XOR operation of Des and Src.
Src can be immediate number, register or
memory location.
Des can be register or memory location.
Both operands cannot be memory locations at
the same time.
CF and OF become zero after the operation.
PF, SF and ZF are updated.

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 Bit Manipulation Instructions
TEST Des, Src:
It performs AND operation of Des and Src.
Src can be immediate number, and src/Des can
be register or memory location.
It is Non-Destructive And means Dest is not
modified only flags are affected.
Both operands cannot be memory locations at
the same time.
CF and OF become zero after the operation.
PF, SF and ZF are updated.
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2. Data Transfer Instructions

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 Data Transfer Instructions
MOV Des, Src:
It is used to copy the content of Src to Des
Src operand can be register, memory location or
immediate operand.
Des can be register or memory operand.
Both Src and Des cannot be memory location at
the same time.
E.g.:
MOV CX, 037A H
MOV AL, BL
MOV BX, [0301 H]
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 Data Transfer Instructions
PUSH Operand:
It pushes the operand into top of stack.
E.g.: PUSH BX

POP Des:
It pops the operand from top of stack to Des.
Des can be a general purpose register, segment
register (except CS) or memory location.
E.g.: POP AX
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 Data Transfer Instructions
XCHG Des, Src:
This instruction exchanges Src with Des.
It cannot exchange two memory locations
directly.
E.g.: XCHG DX, AX

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 Data Transfer Instructions
IN Accumulator, Port Address:
It transfers the operand from specified port to
accumulator register.
E.g.: IN AX, 0028 H

OUT Port Address, Accumulator:

It transfers the operand from accumulator to
specified port.
E.g.: OUT 0028 H, AX

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 Data Transfer Instructions
LEA Register, Src:
It loads a 16-bit register with the
offset address of the data specified
by the Src.
E.g.: LEA BX, [DI]
This instruction loads the contents of
DI (offset) into the BX register.

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 Data Transfer Instructions
LDS Des, Src:
It loads 32-bit pointer from memory source to
destination register and DS.
The word is placed in the destination register
and the segment is placed in DS.
This instruction Copies the word at the lower
memory address to the Des reg and the word at
the higher address to the segment reg i.e. DS.
E.g.: LDS BX, [0301 H]

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 Data Transfer Instructions
LES Des, Src:
It loads 32-bit pointer from memory source to
destination register and ES.
The Word is placed in the destination register
and the segment is placed in ES.
This instruction is very similar to LDS except
that it initializes ES instead of DS.
E.g.: LES BX, [0301 H]

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 Data Transfer Instructions
LAHF:
It copies the lower byte of flag register to AH.

SAHF:
It copies the contents of AH to lower byte of flag register.

PUSHF:
Pushes flag register to top of stack.

POPF:
Pops the stack top to flag register.

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 3. Branch/Program Execution Transfer
Instructions
These instructions cause change in the
sequence of the execution of instruction.
This change can be a conditional or
sometimes unconditional.
The conditions are represented by flags.

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 Branch Instructions
CALL Des:
This instruction is used to call a subroutine or
function or procedure.
The address of next instruction after CALL is
saved onto stack.
RET:
It returns the control from procedure to calling
program.
Every CALL instruction should have a RET.
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 Branch Instructions
JMP Des:
This instruction is used for unconditional jump
from one place to another.

Jxx Des (Conditional Jump):

All the conditional jumps follow some
conditional statements or any instruction that
affects the flag.

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 Conditional Jump Table
Mnemon Meaning Jump
ic Condition

JA Jump if Above CF = 0 and ZF

=0

JAE Jump if Above or Equal CF = 0

JB Jump if Below CF = 1

JBE Jump if Below or Equal CF = 1 or ZF =

1

JC Jump if Carry CF = 1

JE Jump if Equal ZF = 1

JNC Jump if Not Carry CF = 0

JNE Jump if Not Equal ZF = 0

JNZ Jump if Not Zero ZF = 0

JPE Jump if Parity Even PF = 1

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 Loop Instructions
Loop Des:
This is a looping instruction.
The number of times looping is required is
placed in the CX register.
With each iteration, the contents of CX are
decremented.
ZF is checked whether to loop again or not.

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 Program Execution Transfer Instructions
INTO (Interrupt on overflow):
This instruction generates type 4 interrupt
(i.e. interrupt for overflow) and causes the
8086 to do an indirect far call a procedure
which is written by the user to handle the
overflow condition.
IRET
To return the execution to the interrupted
program

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4. Machine Control
Instructions
 Machine Control Instructions
HLT (Halt) :- It causes the processor to enter in
to the halt state. It can be stop by INTR,NMI or
RESET pin
NOP (No Opration) :- It causes the processor to
enter in to the wait state for 3 Clock cycles.
WAIT :- It causes the processor to enter in to the
ideal state. Can be stop by TEST, INTR OR NMI pin
LOCK :- This instruction prevents other
processors to take the control of shared
resources. For e.g LOCK IN AL,80H

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5. Flag Manipulation
Instructions
Flag Manipulation Instructions
STC:
It sets the carry flag to 1.

CLC:
It clears the carry flag to 0.

CMC:
It complements the carry flag.

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Flag Manipulation Instructions
STD:
It sets the direction flag to 1.
If it is set, string bytes are accessed from
higher memory address to lower memory
address.

CLD:
It clears the direction flag to 0.
If it is reset, the string bytes are accessed from
lower memory address to higher memory
address. 46
 Flag Manipulation Instructions
STI:
It sets the Interrupt flag to 1.

CLI:
It clears the Interrupt flag to 0.

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6. Shift And Rotate Instructions
 Shift And Rotate Instructions
SHL/SAL Des, Count:
It shift bits of byte or word left, by count.
It puts zero(s) in LSBs.
MSB is shifted into carry flag.
If the number of bits desired to be shifted is 1,
then the immediate number 1 can be written in
Count.
However, if the number of bits to be shifted is
more than 1, then the count is put in CL
register. And recent bit to the CF (Carry flag)
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 Shift And Rotate Instructions
SHR/SAR Des, Count:
It shift bits of byte or word right, by count.
It puts zero(s)(for SHL) and Sign bit (for SAL)
in MSBs.
LSB is shifted into carry flag.
If the number of bits desired to be shifted is 1,
then the immediate number 1 can be written in
Count.
However, if the number of bits to be shifted is
more than 1, then the count is put in CL
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 Shift And Rotate Instructions
ROL Des, Count:
It rotates bits of byte or word left, by count.
LSB is transferred to MSB and also to CF.
If the number of bits desired to be shifted is 1,
then the immediate number 1 can be written in
Count.
However, if the number of bits to be shifted is
more than 1, then the count is put in CL
register. And recent bit to the CF (Carry flag)

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 Shift And Rotate Instructions
ROR Des, Count:
It rotates bits of byte or word right, by count.
MSB is transferred to LSB and also to CF.
If the number of bits desired to be shifted is 1,
then the immediate number 1 can be written in
Count.
However, if the number of bits to be shifted is
more than 1, then the count is put in CL
register. And recent bit to the CF (Carry flag)

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 Shift And Rotate Instructions
RCL Des, Count:
It rotates bits of byte or word right, by count.
LSB to MSB then MSB is transferred to CF and
CF to LSB.
If the number of bits desired to be shifted is 1,
then the immediate number 1 can be written in
Count.
However, if the number of bits to be shifted is
more than 1, then the count is put in CL
register. And recent bit to the CF (Carry flag)
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 Shift And Rotate Instructions
RCR Des, Count:
It rotates bits of byte or word left, by count.
MSB to LSB then LSB is transferred to CF and
CF to MSB.
If the number of bits desired to be shifted is 1,
then the immediate number 1 can be written in
Count.
However, if the number of bits to be shifted is
more than 1, then the count is put in CL
register. And recent bit to the CF (Carry flag)
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7. String Manipulation
Instructions
 String Manipulation
Instructions
String in assembly language is just a
sequentially stored bytes or words.
There are very strong set of string
instructions in 8086.
By using these string instructions, the size of
the program is considerably reduced.

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 8086
Microprocessor

String Manipulation Instructions

 String : Sequence of bytes or words

 8086 instruction set includes instruction for string movement, comparison, scan, load and
store.

 REP instruction prefix : used to repeat execution of string instructions

 String instructions end with S or SB or SW. S represents string, SB string byte

and SW string word.

 Offset or effective address of the source operand is stored in SI register and that of the
destination operand is stored in DI register.

 Depending on the status of DF, SI and DI registers are automatically updated.

 DF = 0  SI and DI are incremented by 1 for byte and 2 for word.

 DF = 1  SI and DI are decremented by 1 for byte and 2 for word.

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 String Manipulation
Instructions
MOVS / MOVSB / MOVSW:
It causes moving of byte or word from one
string to another.
In this instruction, the source string is in Data
Segment referred by DS:SI and destination
string is in Extra Segment referred by ES:DI.
For e.g. movs str1,str2
Movsb
Movsw
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 String Manipulation
Instructions
LODS / LODSB / LODSW:
It causes TRANSFER of byte or word from one
string to another.
In this instruction, the source string is in Data
Segment referred by DS:SI transferred to
Accumulator.
For e.g. lods string
lodsb
lodsw
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 String Manipulation
Instructions
STOS / STOSB / STOSW:
It causes TRANSFER of byte or word from one
string to another.
In this instruction, the string is in Extra Segment
referred by ES:DI transferred to Accumulator.
For e.g. stos string
stosb
stosw

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 String Manipulation
Instructions
CMPS Des, Src:
It compares the string bytes or words.

SCAS String:
It scans a string.
It compares the String with byte in AL or with
word in AX.

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 String Manipulation
Instructions
REP (Repeat):
This is an instruction prefix.
It causes the repetition of the instruction until
CX becomes zero.
E.g.: REP MOVSB
It copies byte by byte contents.

REP repeats the operation MOVSB until CX

becomes zero.

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 8086
Microprocessor

String Manipulation
Instructions
REP

REPZ/ REPE While CX  0 and ZF = 1, repeat

execution of string instruction and
(Repeat CMPS or (CX)  (CX) – 1
SCAS until ZF = 0)

REPNZ/ REPNE While CX  0 and ZF = 0, repeat

execution of string instruction and
(Repeat CMPS or (CX)  (CX) - 1
SCAS until ZF = 1)

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 Assembly Level Programming 8086

• The assembly programming language is a low-level language

which is developed by using mnemonics.
• The microcontroller or microprocessor can understand only the
binary language like 0’s or 1’s therefore the assembler convert the
assembly language to binary language and store it the memory to
perform the tasks.
• Before writing the program the embedded designers must have
sufficient knowledge on particular hardware of the controller or
processor, so first we required to know hardware of 8086
processor.

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The assembly language programming 8086 has some rules such
as
•The assembly level programming 8086 code must be written in
upper case letters
•The labels must be followed by a colon, for example: label:
•All labels and symbols must begin with a letter
•All comments are typed in lower case
•The last line of the program must be ended with the END
directive.
8086 processors have two other instructions to access the data,
such as WORD PTR – for word (two bytes), BYTE PTR – for byte.
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Op-code: A single instruction is called as an op-code that can be
executed by the CPU. Here the ‘MOV’ instruction is called as an
op-code.

Operands: A single piece data are called operands that can be operated
by the op-code. Example, subtraction operation is performed by the
operands that are subtracted by the operand.

Syntax: SUB b, c
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8086 microprocessor assembly language programs

Write a Program For Read a Character From The Keyboard

MOV ah, 1h //keyboard input subprogram
INT 21h // character input
// character is stored in al
MOV c, al //copy character from alto c

Write a Program For Reading and Displaying a Character

MOV ah, 1h // keyboard input subprogram
INT 21h //read character into al
MOV dl, al //copy character to dl
MOV ah, 2h //character output subprogram
INT 21h // display character in dl

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Addition
ORG0000h
MOV DX, #07H // move the value 7 to the register AX//
MOV AX, #09H // move the value 9 to accumulator AX//
Add AX, 00H // add CX value with R0 value and stores the result
in AX//
END
Multiplication
ORG0000h
MOV DX, #04H // move the value 4 to the register DX//
MOV AX, #08H // move the value 8 to accumulator AX//
MUL AX, 06H // Multiplied result is stored in the Accumulator AX //
END
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Subtraction
ORG 0000h
MOV DX, #02H // move the value 2 to register DX//
MOV AX, #08H // move the value 8 to accumulator AX//
SUBB AX, 09H // Result value is stored in the Accumulator A X//
END
Division
ORG 0000h
MOV DX, #08H // move the value 3 to register DX//
MOV AX, #19H // move the value 5 to accumulator AX//
DIV AX, 08H // final value is stored in the Accumulator AX //
END
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 8086 stack
•The stack is a block of memory that may be used for temporarily
storing the contents of registers inside CPU.
•Stack is accessed by using SP and SS.
•Stack is a Top Down Data Structure whose elements are accessed by
using a pointer (SP,SS).
•The stack is required when CALL instruction is used.
• Push
• Pop
• Top of stack
• Stack pointer
• LIFO 70
• The Stack is a portion of memory which, like a
stack of plates in a canteen, is organized on a Last-
In-First-Out basis.
• Thus the item which was put last on the stack is
the first to be withdrawn

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 The Stack Pointer

The Stack pointer keeps track of the

position of the last item placed on the
stack (i.e. the Top of Stack)
•The Stack is organized in words, (i.e.
two bytes at a time). Thus the stack
pointer is incremented or decremented
by 2.
•The Stack Pointer points to the last
occupied locations on the stack

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 Stack instructions

Flags: Only affected by the popf instruction

Addressing mode: src and dst should be words and cannot be immediate.
dst cannot be the IP or CS register

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 PUSH & POP

The two set of instructions which

explicitly modify the stack are the PUSH
(which places items on the stack) and
the POP (which retrieves items from the
stack).
•In both cases, the stack pointer is
adjusted accordingly to point always to
the top of stack.
•Thus PUSH AX means SP=SP-2 and AX ->
[SP]
•POP AX means [SP] -> AX and SP=SP+2.
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 Example

•Using the stack, swap the values of the ax and bx registers, so

that ax now contains what bx contained and bx contains what ax
contained. (This is not the most efficient way to exchange the
contents of two variables). To carry out this operation, we need at
least one temporary variable:
push ax ; Store ax on stack
push bx ; Store bx on stack
pop ax ; Copy last value on stack to ax
pop bx ; Copy first value to bx
Push ax
Mov ax, bx
Pop bx
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76
 Interrupts

•An interrupt is either a hardware generated call

(externally derived from a hardware signal) or software
generated CALL (internally derived from the execution of
an instruction or by some other internal event)
•When an interrupt occurs, the CPU is interrupted
•the CPU attends to the interrupt and then carries on
where it left off

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 Types of Interrupts

Hardware
•an external signal is applied to the NMI input pin or the
INTR input pin
•NMI -non-maskable interrupt
•INTR –interrupt used to deal with I/O devices that need
attention
Software
•Occurs when INT instruction is executed
•When some error condition is produced by the execution of an
instruction such as divide by zero
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Interrupt handling in 8086

When an interrupt is requested…

•the CPU finishes executing current instruction
•pushes flag register onto stack
•disables the INTR input by clearing the IF
(interrupt flag) in the flag register
•clears the TF (trap flag) in the flag register
•pushes the current CS contents onto the stack
•pushes the current IP contents onto the stack
•does an indirect far jump to the start of the ISR
(Interrupt Service Routine)

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 Interrupt Handling (cont.)

•Processor executes Interrupt Service Routine (ISR) like

a normal procedure
•Only difference is normal procedures use RET at the
end of a procedure, ISRs use an IRET instruction instead
of RET
•This pops IP, CS, and the Flag registers
•ISRs can be interrupted!

80
 Interrupt vector table

•In 8086, 1st1k bytes of memory 00000-003ffh is set aside as a table for
storing the starting addresses of interrupt service procedures(routines)
•Since 4 bytes are required to store the CS & IP values for each interrupt
service procedure, the table can hold the starting addresses of up to 256
interrupts
•The starting address of an interrupt service procedure is called interrupt
vector or interrupt pointer and the table is referred to as interrupt vector
table or the interrupt pointer table
•Each double word interrupt vector is identified by a number from 0 to
255.
•Intel calls this number, the type of interrupt
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Interrupt vector table contd..

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 Interrupt vector table contd..

•The lowest 5 interrupts are dedicated to specific interrupts such as

divide by 0, single step, NMI, interrupt caused by an instruction and
overflow interrupt.
•Interrupts from 5-31 are reserved by Intel for more complex
processors
•The upper 224 interrupts from type 32 to type 255 are available for
users to use for hardware or software interrupts
•The vector for each interrupt requires 4 memory locations.
•Therefore, when the 8086 responds to a particular type of interrupt,
it automatically multiplies the type by 4 to produce the desired
address in the table to get the starting address of The Interrupt
Service Procedure (ISP) 83
 Interrupt sources

•An 8086 interrupt can come from any one of the 3 sources
1.External signal to NMI or INTR input pin. An interrupt caused by a signal
applied to one of these inputs is referred to as hardware interrupt
2.Execution of interrupt instruction INT. This is referred to as software
interrupt
3.An interrupt caused by some error condition in 8086 by the execution
of an instruction
Ex: Divide by 0. If an attempt is made to divide an operand by 0, 8086
automatically interrupts the current executing program

84
 Actions taken by 8086 when an interrupt occurs

•At the end of each instruction cycle, 8086 checks to see if any interrupts have
been requested. If an interrupt has been requested, 8086 responds to the interrupt
by stepping through the following series of major actions.
•It decrements IP by 2 and pushes the flag register on the stack
•Disables INTR interrupt by clearing interrupt flag in the flag register
•It resets Trap flag in the flag register
•IT decrements SP by 2 and pushes the current CS register on the stack
•IT decrements SP again by 2 and pushes the current IP contents on the stack
•IT does an indirect far jump to the start of the procedure that is written to
respond to the interrupt

85
 Type 2 interrupt-NMI

•8086 will automatically do a type 2 interrupt response when it receives

low-to-high transition on its NMI input pin
•When 8086 does type2 interrupt, it pushes flag register on the stack,
resets IF and TF, pushes CS & IP on the stack
•It then gets CS & IP values from the address 0000Ah and IP value from
00008h in the interrupt vector table
•The name Non Maskable implies that type 2 interrupt response cannot
be disabled (masked) by any program instructions
•Because this interrupt cannot be disabled intentionally or accidentally,
it is used to signal 8086 that some condition in an external system must
be taken care of. 86
 Interrupt cycle of 8086

•Broadly, there are two types of interrupts

•The first out of them is external interrupt and the second is internal
interrupt.
•In external interrupt, an external device or a signal interrupts the
processor from outside. I.e. the interrupt is generated outside the
processor
•For ex: a keyboard interrupt
•The internal interrupt on the other hand is generated internally by
the processor circuit or by the execution of interrupt instruction.

•The examples of this type are divide by 0, overflow interrupt and

interrupts due to INT instructions
87
 Interrupt cycle of 8086 contd..

•The responses to the NMI, TRAP or Divide by zero interrupt requests are independent
of the IF flag.
•After an interrupt is acknowledged, the CPU computes the vector address from the
type of the interrupt and the processor executes the ISR of the corresponding interrupt.
•If further interrupts are to be responded to during the time of the first interrupt is
being serviced, the IF should be set by the ISR of the first interrupt
•If the interrupt flag IF is not set, the subsequent interrupt signals will not be
acknowledged by the processor, till the current one is completed
•The programmable interrupt controller is used for managing such multiple interrupts
based on their priorities.
•At the end of ISR, the last instruction should be IRET
•When the CPU executed IRET, the contents of flags, IP and CS which were saved before
the execution of ISR are now retrieved to the respective registers.
•The execution continues onwards from this address received by IP and CS 88
Interrupt Response Sequence and structure of
interrupt vector table

89
Interrupt Response Sequence contd..

90
 NMI interrupt

NMI interrupt has the highest priority among the external interrupts
•TRAP (Single Step-Type1) is an internal interrupt having the lowest
priority
•The NMI is activated on a positive transition (low to high).
•The assertion of the NMI interrupt is equivalent to an execution of
instruction INT 02. I.e. Type 2 interrupt
•However, if an internal interrupt is being serviced and an NMI (or INTR if
IF is set) occurs, the ISR for the internal interrupt will be suspended and
the external interrupt is honored, even though it is of lower priority.
•The priority structure applies only to simultaneous interrupt
requests.
91
 NMI interrupt contd..

•When the NMI is activated, the current instruction being executed is

completed and then the NMI is served
•In case of string manipulation instructions, this interrupt will be served
only after the complete string has been manipulated
•Another high going edge on the NMI pin, during the period in which the
first NMI is served , triggers another response
•The signal on the NMI pin must be free of logical bounces to avoid
erratic NMI responses

92
 NMI interrupt contd..

•NMI is a nonmaskable interrupt, which means that it cannot be blocked.

•INTR, on the other hand, is maskable via the IF flag.
•Only when this flag is set, interrupt on this input will be accepted.
•Although internal interrupts have priority over external interrupts, the NMI
request will be honored as soon as the internal interrupt’s ISR begins
•The same is not true for the INTR input.
•Because the NMI input is nonmaskable, care must be taken when using this
interrupt.
•This is because there may be some programs that you do not want interrupted—
reading or writing data to a disk drive, for example.
•For this reason, the NMI input is normally reserved for catastrophic events such
as memory error or an impending power failure.
93
 Interrupt Programming

•While programming for any type of interrupt, the programmer must,

either externally or through the program, set the interrupt vector
table for that type preferably with the CS and IP addresses of the
interrupt service routine.
•The method of defining the interrupt service routine for software as
well as hardware interrupt is the same.
•Fig shows the execution sequence in case of a software
interrupt

94
Interrupt Programming-Transfer of control during
execution of an interrupt

95
 Interrupt Programming-transfer of control for
the nested interrupts

•It is assumed that the interrupt vector table is initialised suitably to

point to the interrupt service routine. Fig. below shows the transfer of
control for the nested interrupts

96
 Timings and Delays

•Every instruction requires a definite number of clock cycles for its

execution.
•The duration required for the execution of an instruction can be used to
derive the required delays
•A sequence of instructions, if executed by a processor, will require a
time duration that is the sum of all the individual time durations
required for execution of each instruction
•When a loop instruction is used in the program, the number of
instructions in the program may be less but the number of instructions
actually executed by the processor depends on the loop count
97
 Timings and Delays contd..

The procedure of generating delays using a microprocessor is as follows

1. Determine the exact delay required
2. Select the instructions for delay loop
•While selecting the instructions care should be taken that the execution of
these instructions does not interfere with the main program execution
•I.e. Any memory location or register used by the main program must not
be modified by the delay routine.
•The instructions executed for the delay loop are dummy instructions in the
sense that the result of those instructions is useless but the time required
for their execution is an elemental part of the required delay.

98
 MACROS
• Whenever it is required to use a group of instructions several times in
a program, there are two ways to use that group of instructions:
• Procedure
• Macro

• A macro is a group of instructions to which a name is given.

• Each time a macro is called in a program, the assembler will replace
the macro name with the group of instructions.

99
 Advantages
• Macro reduces the amount of repetitive coding.
• Program becomes more readable and simple.
• Execution time is less as compared to calling procedures.
• Reduces errors caused by repetitive coding

• Disadvantage of macro is that the memory requirement of a program

becomes more.

100
Comparison Macros and Procedures
• A big advantage of using procedures is that the machine codes for the
group of instruction in the procedures needs to be loaded in to main
memory only once.
• Disadvantage using the procedures is the need for the stack.
• A macro is the group of instruction we bracket and give a name to at
the start of the program.
• Using macro avoids the overhead time involved in calling and
returning from a procedures.

101
Defining and Calling a Macro
Without Parameters
• Before using macros, we have to define them.
• Macros are defined before the definition of segments

Macro Definition:
MACRO-NAME MACRO
; MACRO DEFINITION
;
ENDM
Invoking a Macro:
MACRO-NAME
102
Example
Macro Definition:
CLRSCR MACRO
MOV AH, 00H
MOV AL, 02H
INT 10H
ENDM

Macro Invocation:
CLRSCR

103
Defining and calling a Macro with
parameters

• Syntax :

NameMacro MACRO [parameter1, parameter2...]

Code of the macro
ENDM

104
Passing Parameters to Macros

Example:
Macro definition:
SETCURSOR MACRO X, Y
MOV DL, Y
MOV DH, X
MOV BH, 00H
MOV AH, 02H
INT 10H
ENDM

105
Contd..
• If the macro invocation statement is SETCURSOR 12,
40 then the macro will be replaced by:
MOV DL, 40
MOV DH, 12
MOV BH, 00H
MOV AH, 02H
INT 10H

106