PLL
Disha L
Ankitha A Renjal
Chandrashekar A R
Ksheeraj S K
Phase lock loop
A control system that generates an output signal whose phase is fixed
relative to the phase of an input signal.
PLL synchronises the output signal with input signal in the phase as well as
frequency.
Basic elements are phase detector, low pass filter, voltage controlled
oscillator and feedback path.
WORKING:
Whenever loop is turned on, VCO runs at fo(free running frequency), now
phase detector refers the input frequency(fin) with oscillator frequency(fo),
based on that it generates error signal(E(t)). Now this error signal is passed to
LPF, it generates error voltage(Ev) based on the error signal. Based on this Ev,
VCO either increases or decreases the fo until the fo locks the fin. Under lock
condition, no phase difference or constant phase difference between two
signals.
Loop in lock condition : f0=fin and ΔФ=0 or constant.
Capture range : The range of input frequencies around the VCO centre
frequency onto which the loop can lock when starting from the unlocked
condition.
Lock range : The range of input frequencies over which the loop remains in
lock condition once it has captured the input signal.
Tuning range : The range over which the frequency of VCO can be tuned.
Supply pushing : Change in output frequency with the change in supply
voltage.
Pull in time : Total time taken by the system to get locked.
Variations :
Analog or linear PLL (APLL) : Phase detector is an analog multiplier, Loop
filter is active or passive, Uses a VCO. APLL is said to be a type II if its loop
filter has transfer function with exactly one pole at the origin.
Digital PLL (DPLL) : An analog PLL with a digital phase detector (such
as XOR, edge-triggered JK flip flop, phase frequency detector). May have
digital divider in the loop.
All digital PLL (ADPLL) : Phase detector, filter and oscillator are digital. Uses
a numerically controlled oscillator (NCO).
Neuronal PLL (NPLL) : Phase detector is implemented by neuronal non-
linearity, oscillator by rate-controlled oscillating neurons.
Software PLL (SPLL) : Functional blocks are implemented by software rather
than specialized hardware.
Charge-pump PLL (CP-PLL) : CP-PLL is a modification of phase-locked loops
with phase-frequency detector and square waveform signals.
LM565/LM565CN
General purpose phase locked loops containing a stable, highly linear
voltage controlled oscillator for low distortion FM demodulation, and a
double balanced phase detector with good carrier suppression. The VCO
frequency is set with an external resistor and capacitor, and a tuning range
of 10:1 can be obtained with the same capacitor.
The characteristics of the closed loop system—bandwidth, response speed,
capture range and pull in range may be adjusted over a wide range with an
external resistor and capacitor.
It is specified for operation over the 0°C to +70°C temperature range.
200 ppm/°C frequency stability of the VCO.
Power supply range of ±5 to ±12 volts with 100 ppm/%.
Adjustable hold in range from ±1% to > ±60%.
TTL and DTL compatible phase detector input and square wave output.
Ratings:
Supply Voltage ±12V
Power Dissipation (Note 2) 1400
mW
Differential Input Voltage ±1V
Operating Temperature Range 0°C
to +70°C
Operating Principle:
A phase detector is a comparator, – Compares phase of input frequency 𝑓𝐼𝑁
with the phase feedback signal frequency 𝑓𝑂𝑈𝑇 .
Output of the phase detector is,
Proportional to the phase difference between input and feedback signals.
DC in nature.
Often referred to as error voltage.
Output of the phase detector is passed through the low pass filter.
LPF → removes the high frequency noise
The output of the LPF is given as an input to the Voltage Controlled Oscillator.
VCO → is a oscillator circuit whose output frequency is proportional to the input
DC level.
Without any input, produces a free running frequency 𝑓𝑂 .
Frequency of VCO output is varied until the its frequency is equal to the input
frequency, → phase difference remains constant.
Output frequency ∝ phase difference between signal
Familiarization with the function of PLL 565:
To study the working of this IC a similar circuit is arranged.
Without connecting any input signal, power is applied and the frequency of the
VCO output at pin-4 is observed. This is the free-running frequency of the VCO.
Free-running frequency observed : 3.36kHz
Used function generator to output a square wave at measured frequency ---.
Applied it to PLL input (pin-2).
‘Locking’ is observed.
Slowly increased the input frequency until the PLL lost lock .This is the upper
limit of lock range.
Observed value : 4.57kHz
Slowly reduced the frequency until the PLL suddenly captures the input signal
and locks again. This is the upper limit of PLL capture range which is
somewhat lower than upper lock range.
Observed value : 3.45kHz
Slowly reduced again the input frequency below fo until the PLL lost lock. This
is the lower limit
Observed value : 2.82kHz
Again slowly increased the frequency of the input until the PLL suddenly
captures the input and locks again. This is the lower limit of PLL capture range.
Observed value : 3.27kHz
Lock range : 1.75kHz
Capture range : 0.18kHz
A 65nm CMOS Phase-locked Loop for 5G Mobile
Communications(Paper Summary):
This paper presents a 65 nm CMOS phase- locked loop (PLL) designed for
5G mobile communications. The PLL consists of a phase/frequency
detector, a charge pump, a third-order loop filter, and a rotary traveling-
wave voltage-controlled oscillator (RTW VCO).
The RTW VCO is used to achieve low phase noise, high oscillation
frequency, and multi-phase clock generation.
The PLL can operate in the frequency range of 24.1-27.6 GHz, covering one
of the frequency bands allocated for 5G in China.
Key design techniques include a source-switching charge pump with a rail-
to-rail operational amplifier for accurate current matching, and a set of
switched capacitors in the VCO to reduce the voltage-frequency gain
without reducing the tuning range.
Key Points:
Designed a 65 nm CMOS PLL for 5Gmobile communications.
Used a rotary traveling-wave VCO to achieve low phase noise, high
frequency, and multi-phase clocks .
Covered the 24.75-27.5 GHz frequency band allocated for 5G in China.
Employed a source-switching charge-pump with a rail-to-rail op-amp for
accurate current matching .
Used switched capacitors in the VCO to reduce voltage-frequency gain
without reducing tuning range.
