Unit 1-Basic Structure of Computers
Unit 1-Basic Structure of Computers
and Organization
CMOS Battery
BUS
Course Description
This course aims to provide a strong foundation
for students to understand computer system
architecture and to apply these in sights and
principles to future computer designs. The course
is structured around the three primary building
blocks of general purpose computing systems:
processors, memories and input/output.
Lesson 1.
Basic Structure of
Computers
1. Input Unit
2. Memory Unit
3. Arithmetic and Logic Unit (ALU)
4. Output Unit
5. Control Unit
I/O Processor
Input and Output Unit is collectively referred to as Input – Output (I/O) Unit
Arithmetic and Logic Unit in conjunction with control unit is known as Processor
2. Mouse 2
1
3. Joy Stick
4. Light Pens
5. Microphones
5
3 4 5
Data -Are numbers and encoded characters that are used as operands (the value on
which an operation is to be done) by the instructions.
Programs and Data can be written into memory or read out from memory under
the control of processor.
Logical decisions involve comparison of two data to see which one is larger
or smaller or equal.
The resulting sum may then be stored in the memory or retained in the
processor for immediate use.
When operands are brought into processor, they are stored in high speed
storage elements-Registers. Each register can store one word of data.
Control unit is the nerve center that sends control signals to other units
and senses their status.
Units/devices gets the data, process the data and stores/displays the data.
Output of this register is available to the control unit which generate timing
signals that control the various processing elements involved in executing the
instruction.
Contain the memory address of the next instruction to be fetched and executed.
BUS
A common approach is to include buffer registers with the devices to hold the
information during transfers.
0 , 1 , 0 , 0 , 1 , ……..
The bus and the processor are no longer needed and can be released for
other activity.
Thus Buffer Registers smooth out the timing differences among
processors, memories and I/O Devices.
Bus is used for connecting the different devices with low cost.
Bus is used to transfer the data between different devices which are
connected in it.
In-order for a user to enter and run the application software, the computer
must contain system software in its memory.
Printer
Disk
OS
routine
Program
t1
t1 t2 t3 t4 t5 Time
During t0 to t1 and t2 to t3, operating system can arrange to print the previous
programs result.
During t4 to t5, the operating system can load the next program to be executed
in the memory from the disk.
Operating system manages the concurrent execution of several application
programs to make the best possible use of computer resources.
This pattern of concurrent execution is called Multiprogramming or
Multitasking.
It also used to control the hardware which are connected in that particular
system.
It is affected by speed of the processor, disk and the printer (i.e elapsed time for
the execution of a program depends on all units in a computer system).
Cache
memory
Bus
At the start of execution, all program instructions and data are stored in the
main memory.
As execution proceeds, instructions are fetched one by one over the bus into
processor and a copy is placed in the cache.
Later if the same instruction or data item is needed second time, it is read
directly from the cache.
© Kalasalingam Academy of Research and Education COMPUTER ARCHITECTURE AND ORGANIZATION
5.2 - Processor Clock
Processor circuits are controlled by a timing signal called clock.
The term
Million is denoted by Mega(M)
Billion is denoted by Giga (G).
500 million cycles per second 500 Megahertz (Mhz)
1250 million cycles per second 1250 Gigahertz (Ghz)
Basic Performance
Calculation Equation
Adds the contents of registers R1 & R2 and places the sum into R3.
The contents of R1 and R2 are first transferred to the inputs of the ALU. After
the add operation is performed, the sum is transferred to R3.
The processor can read the next instruction from the memory while the
addition operation is being performed.
2. Reducing the amount of processing done in one basic step also makes it
possible to reduce the clock period P.
First word
Second word
Third word
ith word
Last word
Practical Problem:
0 0 1 2 3 0 3 2 1 0
4 4 5 6 7 4 7 6 5 4
2k–4 2k–4 2k–3 2k–2 2k–1 2k–4 2k–1 2k–2 2k–3 2k–4
Big-endian assignment Little-endian assignment
Beginning of the string is indicated by giving the byte address containing its first
character.
To execute an instruction, the processor control circuits must cause the word
containing the instructions to be transferred from the memory to the processor.
Operands and results must also be moved between memory and the processor.
To start a load operation, the processor sends the address of the desired
locations to the memory and requests that its contents be read.
The memory reads the data stored at that address and sends them to the
processor.
The processor sends the address of the desired location to the memory,
together with the data to be written into that location.
Sequencing
The task carried out by a computer program consist of sequence of small steps.
4) I/O Transfers
Ex: 1) R1 [LOC]
2) R3 [R1] + [R2]
Right hand side of an RTN Expression always denote a value, Left hand
side of an expression is the name of the location where the value is to be
placed.
Add A,B,C
This instruction has the format
Operation, Source1, Source2, Destination
i + 4n - 4 Add NUMn, R0
i + 4n Move NUMn, R0
The addresses of the memory locations
containing the n numbers are symbolically
given as NUM1, Num2 …… Num n and a SUM
separate add instruction is used to add each NUM 1
number to the contents of register R0. NUM 2
If total number of instructions are less, then execution time will be less
and branching/loop may be used to reduce the execution time .
Programs are usually written in high level language which enables the
programmer to use constants, variables, pointers and arrays.
© Kalasalingam Academy of Research and Education COMPUTER ARCHITECTURE AND ORGANIZATION
Implementation of Variables and
Constants
Variables and Constants are the simplest data types and are found in
almost every computer program.
Variable gives data to the computer for processing.= sign is used to
assign a value to variables.
Ex. A=3 (The operand to the left of the = sign is known as name of the variable
and the operand to the right of the = sign is known as value assigned to the
variable.
Constant is a type of variable whose value cannot be changed.
In assembly language, a variable is represented by allocating a register or
memory location to hold its value.
User can access an operand by specifying the name of the register or
address of the memory location where the operand is located.
Move LOC, R2
Move 200, R0
This instruction places the value 200 in register R0 immediately.
The Immediate mode is only used to specify the value of a source operand.
Immediate operand is represented by placing the sharp sign(#) infront of the
value.
Move #200, R0
Constant Values are used frequently in high level language.
Indirect Mode:
The effective address of the operand is the contents of register or memory
locations whose address appears in the instruction.
Indirection is denoted by placing the name of the register or memory address
given in the instruction in parentheses.
© Kalasalingam Academy of Research and Education COMPUTER ARCHITECTURE AND ORGANIZATION
Indirect Addressing
Indirect addressing can possible through General Purpose Register or
through a Memory Location.
Main
memory
B Operand A B
R1 B Register B Operand
Then processor requests a read operation from the memory to read the
content of location B.
The value read is the desired operand is added to the content of register
R0.
Here processor first read the contents of memory location A (i.e B, effective
address of the operand).
Processor request a read operation from the memory to read the contents of
memory location B.
The value read is the desired operand, is added to the content of register R0.
Address Contents
Move N, R1
Move #NUM1, R2 Initialization
Clear R0
Add (R2), R0
Add #4, R2
LOOP Decrement R1
Branch > 0 LOOP
Move R0, SUM
If the condition is not satisfied, PC gets incremented and next condition in sequential
order is fetched and executed.
This means that loop is repeated as long as there are entries in the list that are yet to be
added to R0.
At the end of the nth pass through the loop, decrement instruction produces a value of 0
and hence branching does not occur. Instead Move instruction is fetched and executed.
Move R0, SUM - Content present in R0 is moved into memory location SUM.
Offset = 20
1020 Operand
1000 20 R1
Offset = 20
1020 Operand
tests. Test 1
Student 2
Test 2
Represents a 2D Array having n rows and n columns. Test 3
.
Each row contain the entries for one student and the .
.
columns gives the student ID and Test Scores.
Here effective address is the sum of the content of X and the contents of
registers Ri and Rj.
Relative Mode:
3302 3300
6B
7F
3302
Register Set
Each address mode can be used in different places to reduce the number
instructions.
Name Mnemonic
Branch BR
Jump JMP
Skip SKP
Call CALL
Return RET
Tested
Mnemonic Branch Condition
Condition
BZ Branch if zero Z=1
BNZ Branch if not zero Z=0
BC Branch if carry C=1
BNC Branch if no carry C=0
BP Branch if plus S=0
BM Branch if minus S=1
BV Branch if overflow V=1
BNV Branch if no overflow V=0
First Assembler Directive: EQU-informs the assembler about the value of SUM
In this case, location specified has the address 204. This location is to be added
with the value 100, DATAWORD directive is used to inform the assembler about
this requirement.
The last statement in the source program is the assembler directive END,
which tells the assembler that this is the end of the source program.
END directive includes the label START, which is the address of the location
at which execution of the program is to begin.
On Output side, processor sends the first character and then waits for a
signal from the display that the character has been received. It then sends
the second character and so on.
Likewise, input is sent from keyboard, the processor waits for a signal
indicating that the character has been struck and its code is available in
some buffer register associated with the keyboard. Then the processor
proceeds to read that code.
SIN SOUT
Keyboard Display
Under program control, the processor monitors SOUT, and when SOUT is
set to 1, the processor transfers a character code to DATAOUT.
The buffer registers DATAIN and DATAOUT, status flags SIN and SOUT are
part of circuit known as device interface.
Data input accepts from Input unit and it will be stored in DATAIN register.
Output data will send it to Output unit and it will be stored in DATAOUT
register.
Input unit and output units are having the status flags (SIN & SOUT) which
are used to know the status of the unit.
This end is called top of the stack and other end is called bottom. This
structure is sometimes referred as pushdown stack.
Stack follows last in first out technique-last data element placed on the
stack is the first one removed from the stack.
Stack contains numerical values with 43 at the bottom and -28 at the top.
Stack Pointer
A processor register keep track of the address of the element of the stack
that is at the top at any given time.
Subtract #4, SP- : Subtract instruction subtracts the source operand 4 from
the destination operand(SP) and places the result in SP.
Move NEW ITEM, (SP)- : Move the New Item(19) to Stack Pointer.
-54 -54
Stack 25 SP 25
Pointer (SP) 504
504
45 45
ITEM -28
Data added into queue is known as REAR End and Data removed from
the queue is known as front end.
Queue follows First in First out technique-data item stored first will be
deleted first.
Reference books:
R1. William Stallings, Computer Organization and Architecture – Designing for
Performance, Pearson Education, 6th Edition, 2003.
R2. David A.Patterson and John L.Hennessy, Computer Organization and design:
The hardware software interface, Morgan Kaufmann, 2nd Edition, , 2002.
R3. John P.Hayes, Computer Architecture and Organization, McGraw Hill, 3rd
Edition, 1998.