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UNIT NO 2
8086 FAMILY ASSEMBLY LANGUAGE
PROGRAMMING
2.4 System Bus Timing
III V
20ESEC50
2
MICROPROCESSORS
AND
MICROCONTROLLERS
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MICROPROCESSORS AND MICROCONTROLLERS
Data Transfer Table
EC 8691
MICROPROCESSORS AND MICROCONTROLLERS
Minimum Mode 8086 System
● In a minimum mode 8086 system, the microprocessor 8086 is
operated in minimum mode by strapping its MN/MX pin to logic 1.
● In this mode, all the control signals are given out by the
microprocessor chip itself. There is a single microprocessor in the
minimum mode system.
● The remaining components in the system are latches,
transreceivers, clock generator, memory and I/O devices.
● Some type of chip selection logic may be required for selecting
memory or I/O devices, depending upon the address map of the
system.
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MICROPROCESSORS AND MICROCONTROLLERS
Minimum Mode 8086 System
● Latches are generally buffered output D-type flip-flops like
74LS373 or 8282.
● They are used for separating the valid address from the multiplexed
address/data signals and are controlled by the ALE signal
generated by 8086.
● Transreceivers are the bidirectional buffers and some times
they are called as data amplifiers. They are required to separate the
valid data from the time multiplexed address/data signals.
● They are controlled by two signals namely, DEN and DT/R.
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MICROPROCESSORS AND MICROCONTROLLERS
Minimum Mode 8086 System
● The DEN signal indicates the direction of data, i.e. from or to the
processor. The system contains memory for the monitor and users
program storage.
● Usually, EPROM are used for monitor storage, while RAM for users
program storage. A system may contain I/O devices.
EC 8691
MICROPROCESSORS AND MICROCONTROLLERS
Minimum Mode 8086 System
● The clock generator generates the clock from the crystal oscillator
and then shapes it and divides to make it more precise so that it
can be used as an accurate timing reference for the system.
● The clock generator also synchronizes some external signal with
the system clock.
● It has 20 address lines and 16 data lines, the 8086 CPU requires
three octal address latches and two octal data buffers for the
complete address and data separation.
EC 8691
MICROPROCESSORS AND MICROCONTROLLERS
Minimum Mode 8086 System
● The working of the minimum mode configuration system can be
better described in terms of the timing diagrams rather than
qualitatively describing the operations.
● The opcode fetch and read cycles are similar. Hence the timing
diagram can be categorized in two parts, the first is the timing
diagram for read cycle and the second is the timing diagram for
write cycle.
● The read cycle begins in T1 with the assertion of address latch
enable (ALE) signal and also M / IO signal. During the negative
going edge of this signal, the valid address is latched on the local
bus.
EC 8691
MICROPROCESSORS AND MICROCONTROLLERS
Minimum Mode 8086 System
● The BHE and A0 signals address low, high or both bytes. From T1
to T4 , the M/IO signal indicates a memory or I/O operation.
● At T2, the address is removed from the local bus and is sent to the
output. The bus is then tristated. The read (RD) control signal is
also activated in T2.
● The read (RD) signal causes the address device to enable its data
bus drivers. After RD goes low, the valid data is available on the
data bus.
● The addressed device will drive the READY line high. When the
processor returns the read signal to high level, the addressed
device will again tristate its bus drivers.
EC 8691
MICROPROCESSORS AND MICROCONTROLLERS
Minimum Mode 8086 System
● A write cycle also begins with the assertion of ALE and the emission
of the address. The M/IO signal is again asserted to indicate a
memory or I/O operation. In T2, after sending the address in T1, the
processor sends the data to be written to the addressed location.
● The data remains on the bus until middle of T4 state. The WR
becomes active at the beginning of T2 (unlike RD is somewhat
delayed in T2 to provide time for floating).
● The BHE and A0 signals are used to select the proper byte or bytes
of memory or I/O word to be read or write.
● The M/IO, RD and WR signals indicate the type of data transfer as
specified in table below.
EC 8691
MICROPROCESSORS AND MICROCONTROLLERS
Read Cycle Timing Diagram for Minimum Mode
EC 8691
MICROPROCESSORS AND MICROCONTROLLERS
Write Cycle Timing Diagram for Minimum Mode
EC 8691
MICROPROCESSORS AND MICROCONTROLLERS
Minimum Mode 8086 System
● Hold Response sequence: The HOLD pin is checked at leading
edge of each clock pulse. If it is received active by the processor
before T4 of the previous cycle or during T1 state of the current
cycle, the CPU activates HLDA in the next clock cycle and for
succeeding bus cycles, the bus will be given to another requesting
master.
● The control of the bus is not regained by the processor until the
requesting master does not drop the HOLD pin low. When the
request is dropped by the requesting master, the HLDA is dropped
by the processor at the trailing edge of the next clock.
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MICROPROCESSORS AND MICROCONTROLLERS
Bus Request and Bus Grant Timings in Minimum Mode System
EC 8691
MICROPROCESSORS AND MICROCONTROLLERS
Maximum Mode 8086 System
● In the maximum mode, the 8086 is operated by strapping
the MN/MX pin to ground.
● In this mode, the processor derives the status signal S2, S1,
S0. Another chip called bus controller derives the control
signal using this status information .
● In the maximum mode, there may be more than one
microprocessor in the system configuration.
● The components in the system are same as in the minimum
mode system.
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MICROPROCESSORS AND MICROCONTROLLERS
Maximum Mode 8086 System
● The basic function of the bus controller chip IC8288, is to
derive control signals like RD and WR ( for memory and
I/O devices), DEN, DT/R, ALE etc. using the information
by the processor on the status lines.
● The bus controller chip has input lines S2, S1, S0 and CLK.
These inputs to 8288 are driven by CPU.
● It derives the outputs ALE, DEN, DT/R, MRDC, MWTC,
AMWC, IORC, IOWC and AIOWC. The AEN, IOB and
CEN pins are specially useful for multiprocessor systems.
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MICROPROCESSORS AND MICROCONTROLLERS
Maximum Mode 8086 System
● AEN and IOB are generally grounded. CEN pin is usually
tied to +5V. The significance of the MCE/PDEN output
depends upon the status of the IOB pin.
● If IOB is grounded, it acts as master cascade enable to
control cascade 8259A, else it acts as peripheral data enable
used in the multiple bus configurations.
● INTA pin used to issue two interrupt acknowledge pulses
to the interrupt controller or to an interrupting device.
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MICROPROCESSORS AND MICROCONTROLLERS
Maximum Mode 8086 System
● IORC, IOWC are I/O read command and I/O write command signals
respectively . These signals enable an IO interface to read or write the
data from or to the address port.
● The MRDC, MWTC are memory read command and memory write
command signals respectively and may be used as memory read or
write signals.
● All these command signals instructs the memory to accept
or send data from or to the bus.
● For both of these write command signals, the advanced
signals namely AIOWC and AMWTC are available.
EC 8691
MICROPROCESSORS AND MICROCONTROLLERS
Maximum Mode 8086 System
● They also serve the same purpose, but are activated one clock cycle
earlier than the IOWC and MWTC signals respectively.
● The maximum mode system timing diagrams are divided in two
portions as read (input) and write (output) timing diagrams.
● The address/data and address/status timings are similar to the
minimum mode.
● ALE is asserted in T1, just like minimum mode. The only difference
lies in the status signal used and the available control and advanced
command signals.
EC 8691
MICROPROCESSORS AND MICROCONTROLLERS
Maximum Mode 8086 System
● Here the only difference between in timing diagram between
minimum mode and maximum mode is the status signals used
and the available control and advanced command signals.
● R0, S1, S2 are set at the beginning of bus cycle.8288 bus
controller will output a pulse as on the ALE and apply a required
signal to its DT / R pin during T1.
EC 8691
MICROPROCESSORS AND MICROCONTROLLERS
Maximum Mode 8086 System
● In T2, 8288 will set DEN=1 thus enabling transceivers, and for
an input it will activate MRDC or IORC. These signals are
activated until T4. For an output, the AMWC or AIOWC is
activated from T2 to T4 and MWTC or IOWC is activated from
T3 to T4.
● The status bit S0 to S2 remains active until T3 and become
passive during T3 and T4.
● If reader input is not activated before T3, wait state will be
inserted between T3 and T4.
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MICROPROCESSORS AND MICROCONTROLLERS
Maximum Mode 8086 System
● Timings for RQ/ GT Signals :The request/grant response
sequence contains a series of three pulses. The Request/grant pins
are checked at each rising pulse of clock input.
● When a request is detected and if the condition for HOLD request
are satisfied, the processor issues a grant pulse over the RQ/GT
pin immediately during T4 (current) or T1 (next) state.
● When the requesting master receives this pulse, it accepts the
control of the bus, it sends a release pulse to the processor using
RQ/GT pin.
EC 8691
MICROPROCESSORS AND MICROCONTROLLERS
Memory Read Timing in Maximum Mode
EC 8691
MICROPROCESSORS AND MICROCONTROLLERS
Memory Write Timing in Maximum Mode
EC 8691
MICROPROCESSORS AND MICROCONTROLLERS
RQ/GT Timings in Maximum Mode
EC 8691
MICROPROCESSORS AND MICROCONTROLLERS
Minimum and Maximum Mode
EC 8691
MICROPROCESSORS AND MICROCONTROLLERS
Minimum Mode
EC 8691
MICROPROCESSORS AND MICROCONTROLLERS
SOURCES
1. https://nptel.ac.in/content/storage2/courses/106108100/pdf/Teacher_Slide
s/mod1/M1L3.pdf
2. https://youtu.be/8VdXXLPHSAQ
3. https://youtu.be/TfRSuEV6qo8
EC 8691
MICROPROCESSORS AND MICROCONTROLLERS
Thank You
