VLSI Digital Circuits

Lecture 14: Dynamic Sequential

Circuits

[Adapted from Prof. Mary Jane Irwin’s slides, Rabaey’s Digital Integrated
Circuits, Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]
Review: Sequential Definitions
 Static versus dynamic storage
 static uses a bistable element with feedback (regeneration) and
thus preserves its state as long as the power is on
 static is preferred when updates are infrequent (clock gating)
 dynamic stores state on parasitic capacitors so only holds the
state for a period of time (milliseconds) and requires periodic
refresh
 dynamic is usually simpler (fewer transistors), higher speed, lower
power
 Latch versus flipflop
 latches are level sensitive with two modes: transparent - inputs
are passed to Q and hold - output stable
 fliplflops are edge sensitive that only sample the inputs on a clock
transition
Review: Timing Metrics
In D Q Out

clock
clock

tsu thold time

In data
stable
tc-q time

Out output output

stable stable
time
Review: System Timing Constraints

Inputs Outputs
Combinational
Logic

Current Next

Registers
State State

State
T (clock period)
clock

tcdreg + tcdlogic  thold T  tc-q + tplogic + tsu

Dynamic ET Flipflop
master slave

!clk clk

QM
D T1 I1 T2 I2 Q

C1 C2
clk !clk
tsu = tpd_tx
thold = zero
master transparent
tc-q = 2 tpd_inv + tpd_tx
slave hold
clk

!clk master hold

slave transparent
Pseudostatic Dynamic Latch
 Robustness considerations limit the use of dynamic FF’s
 coupling between signal nets and internal storage nodes can
inject significant noise and destroy the FF state
 leakage currents cause state to leak away with time
 internal dynamic nodes don’t track fluctuations in VDD that
reduces noise margins
 A simple fix is to make the circuit pseudostatic
clk

QM
Q

!clk

 Add above logic added to all dynamic latches

Dynamic ET FF Race Conditions

!clk clk

QM
D T1 I1 T2 I2 Q

C1 C2
clk !clk

0-0 overlap race condition

clk toverlap0-0 < tT1 + tI1 + tT2
!clk
1-1 overlap race condition
toverlap1-1 < thold
Fix 1: Dynamic Two-Phase ET FF

clk1 clk2

QM
D T1 I1 T2 I2 Q

C1 C2
!clk1 !clk2
master transparent
slave hold

clk1
tnon_overlap
clk2
master hold
slave transparent
C2MOS (Clocked CMOS) ET Flipflop
 A clock-skew insensitive FF
Master Slave

M2 M6

clk Mon
4
!clk Moff
8
off QM on
D Q
!clk Mon
3
C1 clk Moff
7
C2
off on
M1 M5

master transparent
slave hold
clk

!clk master hold

slave transparent
C2MOS FF 0-0 Overlap Case
 Clock-skew insensitive as long as the rise and fall times
of the clock edges are sufficiently small

M2 M6

0 M4 0 M8
QM
D Q
C1 C2

M1 M5

clk clk
!clk !clk
C2MOS FF 1-1 Overlap Case

M2 M6

QM
D Q
1 M3 C1 1 M7 C2

M1 M5

clk clk

!clk !clk

1-1 overlap constraint

toverlap1-1 < thold
 C2MOS Transient Response

3
For a
2.5
QM(3) 0.1 ns clock
2 Q(3)
Volts

1.5
Q(0.1)
1 clk(0.1)
0.5 For a
clk(3) 3 ns clock
0 (race condition
exists)
-0.5
0 2 4 6 8
Time (nsec)
 Pipelining using C2MOS

clk !clk clk

F G Out
In
!clk C1 clk C2 !clk C3

aka NORA (NO RAce) Logic

What are the constraints on F and G?

Only Non-Inverting Logic Allowed

clk on !clk (off)

In = 1
on clk (off)
!clk

The number of static inversions should be even.

Fix 3: True Single Phase Clocked (TSPC) Latches

Negative Latch Positive Latch

clk clk Q
In In clk clk
Q

hold when clk = 1 transparent when clk = 1

transparent when clk = 0 hold when clk = 0
 Embedding Logic in TSPC Latch

PUN A B

Q Q
In clk clk clk clk

A
PDN
B
TSPC ET FF
Master Slave

clk on clk on on on Q
D
off off QM clk off clk off

master transparent
slave hold
master hold
clk slave transparent
Simplified TSPC ET FF

off
M3 clk on
M 6 M9
QM 1  D
QD
clk Mon
D off 2 X !D M5 clk Moff
on 8
M1 clk Moff
4 M7
on

master transparent
slave hold
master hold
clk slave transparent
Sizing Issues in Simplified TSPC ET FF

clk
!Qmod Transistor sizing
2 !Qorig
Original width
Volts

M4, M5 = 0.5m
1 M7, M8 = 2m
Qorig
Modified width
0 M4, M5 = 1m
Qmod
0 0.2 0.4 0.6 0.8 1 M7, M8 = 1m
Time (nsec)
 Split-Output TSPC Latches
Positive Latch Negative Latch

Q A
In clk In clk
A Q

transparent when clk = 1 hold when clk = 1

hold when clk = 0 transparent when clk = 0

When In = 0, A = VDD - VTn When In = 1, A = | VTp |

Split-Output TSPC ET FF

clk
D clk QM
Q

clk
Fix 4: Pulsed FF (AMD-K6)
 Pulse registers - a short pulse (glitch clock) is generated
locally from the rising (or falling) edge of the system clock
and is used as the clock input to the flipflop
 race conditions are avoided by keeping the transparent mode time
very short (during the pulse only)
 advantage is reduced clock load; disadvantage is substantial
increase in verification complexity
0/1 on/off
off
clk 0 1
P1 on P3 Q 1/0
X 1

M3 off M6 off
on on
1/0
D M2 on/ P2 M5
1 off
1 0 1 on
M1 M4
on !clkd
0 off
Fix 5: Sense Amp FF (StrongArm SA100)
 Sense amplifier (circuits that accept small swing input
signals and amplify them to full rail-to-rail signals) flipflops
 advantages are reduced clock load and that it can be used as a
receiver for reduced swing differential buses

onoffon
1
D 1
M9
M2
on M5 M7
01 11
off on on off 1 0
offonoff !Q
M1 M4
Q
on off off on 0 1
11 01
off M6 M8
M3
0 M10
clk onoffon
Flipflop Comparison Chart

Name Type #clk ld #tr tsu thold Tc-q

Mux Static 8 (clk-!clk) 20 3tpinv+tptx 0 tpinv+tptx
PowerPC Static 8 (clk-!clk) 16
2-phase Ps-Static 8 (clk1-clk2) 16
T-gate Dynamic 4 (clk-!clk) 8 tptx to1-1 2tpinv+tptx
C2MOS Dynamic 4 (clk-!clk) 8
TSPC Dynamic 4 (clk) 11 tpinv tpinv 3tpinv
S-O TSPC Dynamic 2 (clk) 10
AMD K6 Dynamic 5 (clk) 19
SA 100 SenseAmp 3 (clk) 20
Choosing a Clocking Strategy
 Choosing the right clocking scheme affects the
functionality, speed, and power of a circuit
 Two-phase designs
 + robust and conceptually simple
 - need to generate and route two clock signals
 - have to design to accommodate possible skew between the
two clock signals
 Single phase designs
 + only need to generate and route one clock signal
 + supported by most automated design methodologies
 + don’t have to worry about skew between the two clocks
 - have to have guaranteed slopes on the clock edges