Embedded Real-Time

Systems
Lecture: ARM
architecture

Dimitris Metafas, Ph.D.

 Program Translation

C program
Compiler Assembly

Assembly
Obj Library
Assembler

Object Linker

Executable
Loader

Memory

Source : D. Patterson,J. Hennessey Computer Organization & Design

Slide 2
 Translation to Binary
 Assembler
 Converts assembly to object code for each module (source file)
 Symbol table for undefined/extern references

 Linker
 Searches program libraries to find library routines used by the program
 Resolves external references

 Loader
 Loads the executable into memory
 Copies instructions and data from executable to memory
 Copy arguments to the program into stack
 Jumps to a start-up routine which copies program arguments from stack to
registers and calls programs main routine

Slide 3
ARM Architecture
 ARM
 Founded in November 1990
 Spun out of Acorn Computers

 Designs the ARM range of RISC processor cores

 Licenses ARM core designs to semiconductor partners who
fabricate and sell to their customers.
 ARM does not fabricate silicon itself

 Also develop technologies to assist with the design-in of the

ARM architecture
 Software tools, boards, debug hardware, application software,

bus architectures, peripherals etc

Slide 5
 ARM partnership model

Slide 6
 ARM Powered Products

Slide 7
 ARM architecture
 Address register
address register

 Register bank
 ALU increm enter

 Barrel shifter PC
PC
 Data in/out registers Rd register bank instruction
decode
&
control
Rn

m ultiply
barrel shifter
register

A LU

data out register data in register

Slide 8
 Data Sizes and Instruction Sets
 The ARM is a 32-bit architecture.

 When used in relation to the ARM:

 Byte means 8 bits

 Halfword means 16 bits (two bytes)

 Word means 32 bits (four bytes)

 Most ARM’s implement two instruction sets

 32-bit ARM Instruction Set

 16-bit Thumb Instruction Set

 Jazelle cores can also execute Java bytecode

Slide 9
 ARM processor
 ARM is a Reduced Instruction Set Computer (RISC)
 A large, regular register file


Any register can be used for any purpose
 A load-store architecture

Instructions which reference memory just move data, they do no
processing

Processing uses values in registers only
 Fixed-length 32-bit instructions

Slide 10
 ARM based System

16 bit RAM 32 bit RAM

Interrupt
Controller
Peripherals I/O
nIRQ nFIQ

ARM
Core
8 bit ROM

Slide 11
 AMBA bus

Arbiter Reset

ARM
TIC
Remap/
External Bus Interface Timer
Pause
ROM External

Bridge
Bus
Interface
External
RAM On-chip Interrupt
Decoder RAM Controller

AHB or ASB APB

System Bus Peripheral Bus

Slide 12
 ARM architecture development

Improved
5TE Jazelle
Halfword
and signed
4 ARM/Thumb
Interworking Java bytecode 5TEJ
1 halfword /
CLZ execution
byte support
System SA-110 Saturated maths ARM9EJ-S ARM926EJ-S
2 mode
DSP multiply-
SA-1110 ARM7EJ-S ARM1026EJ-S
accumulate
instructions
3 ARM1020E SIMD Instructions
Thumb
instruction 4T Multi-processing
6
set XScale
Early ARM V6 Memory
architectures architecture (VMSA)
ARM7TDMI ARM9TDMI ARM9E-S
Unaligned data
ARM720T ARM940T ARM966E-S support ARM1136EJ-S

Slide 13
 Application Specific
Processors based on ARM core -
examples
 INTRACOM’s ASPIS processor

INTRACOM’s ASPIS processor

Slide 15
 INTRACOM’s ASPIS processor
R F & A u d io C o n tro ls

B -S can C h ain

1 k x 1 6 -b it
B u ILD B u s A rb iter SRAM
re q _ 3 a c k _ 3 re q _ 1 a c k _ 1 re q _ 2 a c k _ 2 b _ re q

re q ack re q a c k re q a c k

ARM 7TD M I DM A RF D M A A u d io
(T H U M B ) I/F I/F
JT A G DSP
JTA G IC E B reak er
P o rt B u s I/F
(slave) re q nack

B u IL D -B u s (3 2 -b it a d d ress/d a ta )

b _ re q d _ re q d _ w a it
2 k x 3 2 -b it Bus E xtern al M em o ry
SRAM S lave S lave ... S lave
C trl In terface
(M M U & A rb iter)

T est
In terface
E xt. B u s E x te rn a l M e m o ry
K e yp a d , L C D , S IM I/F , U A R T C on trol
D e v ic e s
(S R A M , F L A S H )

Slide 16
 Application Specific
processors design flow
 System-on-a-Chip Co-design flow
S pecifications & S ystem D esign

P artitioning

S oftw are m odules H ardw are m odules

H igh-level m odels H igh-level m odels
design (S D L, C ++, C ) design (C ++, C )

H igh-level M odel Testing (E xecutable M odel S im ulation)

S oftw are blocks H ardw are blocks

Im plem entation Im plem entation
(C ++, C , A ssem bly) (V H D L)

Low -level Testing (C o-sim ulation)

S ystem testing R eference design

S oftw are Integration C hip fabrication
S oftw are Im plem entation (B oards)

S ystem Integration / Testing

Slide 18
 Cycle-accurate model of the processor

Extended Memory Map Model

LCD
Timer Watchdog Keypad Buzzer
Interface
Model Model Model Model
Model

ARMulator
Interrupt Audio RF
ARM DSP
Controller Interface Interface
Core Model
Model Model Model
Model

Build Bus Model / Bus Arbitration Model

Instruction mapped Extended
Coprocessor Memory Map
Model Model

Internal Static Models

Memory RAM Mirror
Memory Memory
Flash
Memory

Slide 19
 Co-verification

Real-Time software group VLSI design group

Co-processors
Memory ARM Mem-Processing
Oute
Mapped & r
VHDL
interrupt Regs control I/F
VHDL ARM model
•Primitives synthesisable VHDL
•Test suites

SDL, C, Mentor - Modelsim

ASM RT L VHDL
ARM SDT, Netlist - Vital libs
RTOS

Slide 20
Prototype system boards
 ASPIS boards

Synthesiser Programming

RF board FPGA I ASPIS board

PA DAC
GMSK SRAM
Modulator

Synth Baseband board

FLASH
GFSK
FIR Detector ASPIS
LNA ADC

DC offset value
DC offset
cancelation
FPGA setting
FPGA II

Slide 22
 INTRACOM’s WLAN Processor

Local PCI
Bus Bus

Channel #1
PCI irq Timers, Watchdog,
Channel #2 DMA SDRAM
Controller fiq
Auxiliary
POCO, Aux. I/O
controller I/O
Channel #3 Controller &Bridge ARM's DMA channel
ARM7TDMI/
Interrupt Controller
Channel #4 ARM9TDMI
Buffer SRAM

Local Bus #3 (Ext. System Bus) Local Bus #1 (Protocol/CL)

Local/Cache (Flash) ROM

AHB AHB SRAM
Bus I/F Bus I/F

Test
Test Controller AMBA
Port Arbiter HIPERLAN/2
Baseband
AmBa AHB (Trunk Bus) Processor
& Modem
Chip
AHB
Bus I/F

Local Bus #2 (User Plane)

(1)
Bus Isolation
Rate-Matching
Local Bus #2 (User Plane) Buffers (Tx/Rx)
RF- Analog
Ctrl
irq Modem /

ARM Integrator platform

Timers, Watchdog, Local/Cache I/F
ARM's DMA channel fiq (Flash) ROM RF
SRAM
Interrupt Controller ARM7TDMI/ Front-
ARM9TDMI End

Slide 23