Example: Overflow in fixed point addition

Base 2 Base 8 Base 16

1011.1 7.25 C36.A

+1110.0 +6.76 +72B.3
c 1100 c 11 .1 c 1010
s 11001.1 s 16.23 s 1361.D

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Review

2
 Continued

r is an input
If r = 0  addition process
If r = 0  subtraction process

3
 Continued

• We feed the carry from previous

stage to the next stage.
• At nth stage, we have output
carry.
• Output carry could be 0 or 1.

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 CS501
Advanced Computer
Architecture

Lecture 35

Dr.Noor Muhammad Sheikh

5
 Binary bit adders
For a binary adder the sum bit,
sj=xjyjcj+xjyjcj+xjyjcj+xjyjcj
And the carry bit
cj+1=xjyj+xjcj+yjcj

These can be computed using

• Ripple Carry Adder
• Carry Lookahead Adder

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 Ripple Carry Adder
• For 64 bit addition, 126 logic
levels are required between the
input and output bits
• The logic levels can be reduced
by using a higher base ( Base 16)
• Relatively slow
7
Complement adder/subtractor

To perform subtraction using an

unsigned adder
• Complement the second input
• Supply overflow detection
hardware

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Base b Radix Complement Subtractor
y
x
(b-1)’s complement

Base b Adder +1

x-y
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 2’s Complement Adder/Subtractor
• A combined adder/subtractor can
be built using a mux to select the
second adder input
• The mux also determines the
carry-in to the adder
• The equation for mux output is
qj=yjr+yjr
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 2’s complement Adder/Subtracter
am-1 bm-1 a1 b1 a0 b0
Subtract
control
r

qm-1 q1 q0

Cm Cm-1 c2 c1
FA … FA FA co

sm-1 s1 so
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 Carry Lookahead Adder
• This results in faster addition by
generating or propagating the carry bits
• Two logical variables Gj( generate)and
Pj(propagate) are defined as,
Gj=xjyj
Pj=xj+yj
• Hence the carry out will be
cj+1=Gj+Pjcj
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 Carry Lookahead Adder
k=2 c0

Lookahead
Level 3 G 03 c4 P 03

Lookahead
Level 2 G 12 c6 P1 2 G 02 c2 P0 2

Lookahead
G31 P31 G21 P21 G11 P11 G01 P01
Level 1 c7 c5 c3

Compute
G7 P7 G6 P6 G5 P5 G4 P4 G3 P3 G2 P2 G1 P1 G0 P0
G and P

b7 a7 b6 a6 b5 a5 b4 a4 b3 a3 b2 a2 b1 a1 b0 a0

Adders
FA FA FA FA FA FA FA FA
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s7 s6 s5 s4 s3 s2 s1 s0
 Digital Multiplication Schema

multiplicand x3 x2 x1 x0
multiplier y3 y2 y1 y0
(xy0)4(xy0)3(xy0)2(xy0)1(xy0)0 pp0
(xy1)4(xy1)3(xy1)2(xy1)1(xy1)0 pp1
(xy2)4(xy2)3(xy2)2(xy2)1(xy2)0 pp2
(xy3)4(xy3)3(xy3)2(xy3)1(xy3)0 pp3

p7 p6 p5 p4 p3 p2 p1 p0
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 Multiplication

• Digital multiplication is based on

addition and shifting of digits
• The hardware involves a
combination of parallel and
sequential operations

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 Parallel Array Multiplier
a b pk(in)
0 0 0
cin a2 a1 a0
cout b0
pk (out)

… 0

b1

… 0

b2

… 0

p 2m-1 … p2 p1 p0

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Unsigned Series Parallel
Multiplier Hardware
am-1 am-2 … a1 a0

Partial Product bj
Multiplier digit
…
m+1 digit adder

0 …

Product register p
2m digits wide
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 Multiplication Procedure
1. Clear product shift register p
2. Initialize multiplier digit j=0
3. Find the partial product abj
4. Add partial product to upper half of p
5. Increment j=j+1, if j=m go to step 8
6. Shift p right 1 digit
7. Repeat from step 3
8. The 2-m digit product is in the p register
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2’s complement multiplication

1. Provision for sign extension

2. Overflow prevention
3. Subtraction as well as addition of the partial
product

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 2’s complement multiplication hardware

m-bit multiplicand 0 m-bit multiplier

subtract

Carry in
Sign m=1-bit adder
extension m-1 bits

2m-bit accumulator
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 Booth Recoding Table
yi yi-1 zi Value Situation

0 0 0 0 String of zeros

0 1 1 +1 End of string of
1s
1 0 1 -1 Begin string of
1s
1 1 0 0 String of 1s
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Example: Recode the integer 485
according to Booth procedure
Original number:
00111100101
=256+128+64+32+4+1
=485
Recoded Number:
01000101111
=+512-32+8-4+2-1
=485

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 Unsigned binary divide hardware

load Dividend left shift register 0

Divisor register 2 m bit

dividend
register
Positive result m bit
subtractor divisor

m bit
quotient register Left shift quotient
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 Integer division
1. Clear upper half of dividend register and put
dividend in lower half. Initialize quotient
counter bit to 0
2. Shift dividend register left 1 bit
3. If difference is +ve, put it into upper half of
dividend and shift 1 into quotient. If –ve, shift
0 into quotient
4. If quotient bits<m, goto step 2
5. m-bit quotient is in quotient register and m-bit
remainder is in upper half of dividend register

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 Fraction division
1. Clear lower half of dividend register and put
dividend in upper half. Initialize quotient
counter bit to 0
2. If difference is +ve, report overflow
3. Shift dividend register left 1 bit
4. If difference is +ve, put it into upper half of
dividend and shift 1 into quotient. If –ve, shift
0 into quotient
5. If quotient bits<m, goto step 3
6. m-bit quotient has decimal at the left end and
remainder is in upper half of dividend register
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Example: Divide 4710 by 510
D=000000 101111, d=000101
D 000001 011110 Dividend shifted left 1 bit
d 000101
Diff(-) q 0
D 000010 111100
d 000101
Diff(-) q 00
D 000101 111000
d 000101
Diff(+) q 001
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 Example contd: Divide 4710 by 510
D=000000 101111, d=000101
D 000001 110000 Upper half of dividend replaced
by difference and shifted left 1 bit
d 000101
Diff(-) q 0010
D 000011 100000
d 000101
Diff(-) Remainderq 00100 Quotient
D 000111 000000 210 910
d 000101
Diff(+)000010 q 001001
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 Parallel Array Divider
d1 D 1 d2 D2 dm Dm Dm+1 D2m

q0 b0 bi 0
c c …
R d

q1
… 0

Inputs: Dividend Dk …
Divisor dj
Control c qm
0
Borrow-in bi
…

r1 rm 28
Outputs: borrow-out bo, partial remainder Rk
 Branch Architecture

Branch architecture of a machine is

based on

1. condition codes
2. conditional branches

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 Condition Codes

• Computed by ALU and stored in

processor status register
• ‘Comparison’ and ‘branching’ are
treated as two separate
operations
• Not used in the SRC
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Condition codes and flag settings after a subtraction ax-y
Unsigned integers 2’s complement signed integers

Condition Arithmetic Flags Arithmetic condition Flags

condition
ah=1 C ah=1 C
Carry-out
ah=1 C Xh-1 yh-1 ah-1 + V
Overflow
Xh-1 yh-1 ah-1
N.A. N.A. ah-1=1 N
Negative
ah=0&a!=0 CZ a>0& !O ~ a<0&O (NV+NV)Z
>
ah=0 C a>=0&!O~a<0&O NV+N V
>=
a=0 Z a=0 Z
=(zero)
a!=0 Z a!=0 Z
!=
ah=1or z=0 C+Z a<0&!O~a>0&O~a=0 (NV+NV)+Z
<=
31
ah=1 C a<0&!O~a>0&O (NV+NV)
<
 The SRC Approach
In SRC, the comparison is made by sub instruction
and the branch decision is made on its result
e.g. the C code
if (A>B)
C=D;
results in the following SRC code
lar r4, Over
ld r1,a
Test is made on the result of the
ld r2,b
sub operation
sub r3,r2,r1
brpl r4,r3
ld r3,c
st r3,d
Over:
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 Continued

• Multiplication of two numbers

having m-bits and n-bits
respectively results in a (m+n)-
bits result.
• Example :
8-bits numbers * 8-bit number
= 16-bit number

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 Continued

• At machine level, the

expression/condition is evaluated
using ALU and based on decision,
next instruction is executed.

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