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 Contents:

Introduction
8051
Architecture

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• 8051-generic part no-8031 to
8751
• An example for CISC Processor.
• Harvard Architecture
• Collection of 8 and 16 bit
registers and 8 bit memory
locations.
• External Memory can be
interfaced.
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Organization: von Neumann vs.
Harvard
 Organization: von Neumann vs.
Harvard
von Neumann Harvard
•Separate memories for data and
• Same memory holds data, instructions.
instructions. • Two sets of address/data buses
• A single set of address/data between CPU and memory
buses between CPU and •This allows two simultaneous memory
memory fetches.
• Most DSPs use Harvard architecture
for streaming data:
• greater memory bandwidth;
• • more predictable bandwidth.

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 Block Diagram
External Interrupts

Interrupt 4k 128 bytes Timer 1

Control ROM RAM Timer 2

CPU

OSC Bus
4 I/O Ports Serial
Control

P0 P2 P1 P3 TXD RXD
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• Internal ROM and RAM
• I/O Ports with programmable Pins
• ALU
• Working Registers
• Clock Circuits
• Timers and Counters
• Serial Data Communication.

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 8051 Family
Comparison of 8051 Family Members

Feature 8051 8052 8031

ROM (on chip program space in bytes) 4K 8k 0k
RAM (bytes) 128 256 128
Timers 2 3 2
I/O pins 32 32 32
Serial port 1 1 1
Interrupt sources 6 8 6
 Specific Features of 8051
• 8 bit cpu with registers A and B
• 16 bit PC and DPTR(data pointer).
• 8 bit program status word(PSW)
• 8 bit Stack Pointer
• 4K Internal ROM
• 128bytes Internal RAM
- 4 register banks each having 8 registers
16 bytes,which may be addressed at the bit level.
80 bytes of general purpose data memory

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 Specific Features
• 32 i/o pins arranged as four 8- bit ports:P0 to P3
• Two 16 bit timer/counters:T0 and T1
• Full duplex serial data receiver/transmitter
• Control registers:TCON,TMOD,SCON,PCON,IP and IE
• Two external and Three internal interrupt sources.
• Oscillator and Clock Circuits.

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 Pin Description of the 8051
P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0
P1.2 3 38 P
) 0.1(AD1)
P1.3
P1.4
4
5
8051 37
36
P0.2(AD2
P
) 0.3(AD3)
P1.5 6 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RXD)P3.0 10 31 EA/VPP
(TXD)P3.1 11 30 ALE/PROG
(INT0)P3.2 12 29 PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14
(T1)P3.5 15 26 )P2.5(A13
(WR)P3.6 16 25 P
) 2.4(A12
(RD)P3.7 17 24 )P2.3(A11
XTAL2 18 23 P ) 2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8) 

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 Pins of 8051 （ 1/4 ）
• Vcc （ pin 40 ）：
– Vcc provides supply voltage to the chip.
– The voltage source is +5V.
• GND （ pin 20 ）： ground
• XTAL1 and XTAL2 （ pins 19,18 ）：
– These 2 pins provide external clock.(Using a quartz crystal
oscillator)
– Acts as internal clock frequency of the microcontroller.
– Max and minimum frequency-typically 1MHz to 16 MHz
– The oscillator formed by the crystal ,capacitors and an on-chip
inverter generates a pulse train at the frequency of the crystal.

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 Pins of 8051 （ 2/4 ）
C2 30pF
XTAL2
C1
XTAL1
30pF
GND

• RST （ pin 9 ）： reset

– It is an input pin and is active high （ normally low ） .
• Upon applying a high pulse to RST, the microcontroller will
reset and all values in registers will be lost.

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 Pins of 8051 （ 3/4 ）

• /EA （ pin 31 ）： external access

– The /EA pin is connected to GND to indicate the code is stored
externally.
– For 8051, /EA pin is connected to Vcc.
• /PSEN （ pin 29 ）： program store enable
– This is an output pin and is connected to the OE pin of the ROM

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 Pins of 8051 （ 4/4 ）

• ALE （ pin 30 ）： address latch enable

– It is an output pin and is active high.
– 8051 port 0 provides both address and data.
– The ALE pin is used for de-multiplexing the address and data by
connecting to the G pin of the 74LS373 (74LS373.ppt) latch.
• I/O port pins
– The four ports P0, P1, P2, and P3.
– Each port uses 8 pins.
– All I/O pins are bi-directional.

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 Pins of I/O Port

• The 8051 has four I/O ports

– Port 0 （ pins 32-39 ）： P0 （ P0.0 ～ P0.7 ）
– Port 1 （ pins 1-8 ） ： P1 （ P1.0 ～ P1.7 ）
– Port 2 （ pins 21-28 ）： P2 （ P2.0 ～ P2.7 ）
– Port 3 （ pins 10-17 ）： P3 （ P3.0 ～ P3.7 ）
– Each port has 8 pins.
• Named P0.X （ X=0,1,...,7 ） , P1.X, P2.X, P3.X
• Ex ： P0.0 is the bit 0 （ LSB ） of P0
• Ex ： P0.7 is the bit 7 （ MSB ） of P0
• These 8 bits form a byte.
• Each port can be used as input or output (bi-directional).
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 Program Counter & Data Pointer
• They are both 16 bit registers.
• Each is to hold the address of a byte in memory
• PC contains the address of the next instruction to
be executed.
• DPTR is made up of two 8 bit register DPH and
DPL;
• DPTR contains the address of internal &
external code and data that has to be accessed.

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 A and B CPU registers
• Totally 34 general purpose registers or working registers.
• Two of these A and B hold results of many instructions,
particularly math and logical operations of 8051 cpu.
• The other 32 are in four banks,B0 – B3 of eight registers
each.
• A(accumulator) is used for addition, subtraction, mul, div,
boolean bit manipulation and for data transfers.
• But B register can only be used for mul and div
operations.

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 RS1 RS0 Register Bank Address
0 0 0 00H-07H
0 1 1 08H-0FH
1 0 2 10H-17H
1 1 3 18H-1FH

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 8051 Flag bits and the PSW
register

CY AC F0 RS1 RS0 OV - P

Carry flag PSW.7 CY

Auxiliary carry flag PSW.6AC •
Available to the user for general purpose PSW.5F0 •
Register Bank selector bit 1 PSW.4RS1 •
Register Bank selector bit 0 PSW.3RS0 •
Overflow flag PSW.2OV •
User define bit PSW.1 -- •
Parity flag Set/Reset odd/even parity PSW.0 P •

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•Two flag bits are stored in PCON(Power
control) registers also.

•They are the GF1 (3RD) and GF0(2nd) bits

•They are general purpose user flag bit 1 and 0

respectively

•They can be set or cleared by the program

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 Memory Organization
• RAM memory space allocation in the 8051

7FH
Scratch pad RAM

30H
2FH
Bit-Addressable RAM

20H
1FH Register Bank 3
18H
17H Register Bank 2
10H
0FH Register Bank 1 )Stack(
08H
07H Register Bank 0
00H
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 Stack in the 8051
• The register used to access
7FH
the stack is called SP (stack
pointer) register. Scratch pad RAM

30H

• The stack pointer in the 2FH

Bit-Addressable RAM
8051 is only 8 bits wide,
which means that it can take 20H
1FH
value 00 to FFH. When 18H
Register Bank 3

8051 powered up, the SP 17H

10H
Register Bank 2
register contains value 07. 0FH Register )Stack(
08H Bank 1
07H
Register Bank 0
00H

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 Special Function Registers

Name Function Name Function

A Accumulator SBUF Serial Port data

buffer
B Arithmetic SP Stack Pointer
DPH Addressing Ext TMOD Timer/Counter mode
Memory cntrl
DPL Addressing Ext TCON Timer/Counter cntrl
Memory
IE Interrupt enable TL0 Timer0 lower byte
IP Interrupt Priority TH0 Timer0 higher byte
P0 I/O Port Latch TL1 Timer1 lower byte
P1 I/O Port Latch TH1 Timer1 higher byte
P2 I/O Port Latch
P3 I/O Port Latch
PCON Power Control
PSW Pgm Status
Word
 INTERNAL ROM
• The data memory and program code
memory can be in two entirely different
physical memory entities but each has
same address ranges.
• Address space ranges from 0000h to
0FFFFh.

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 I/O Port Programming
Port 0 （ pins 32-39 ）
• When connecting an 8051 to an external memory, the
8051 uses ports to send addresses and read
instructions.
– 16-bit address ： P0 provides address A0-A7, P2
provides address A8-A15.
– Also, P0 provides data lines D0-D7.
• When P0 is used for address/data multiplexing, it is
connected to the 74LS373 to latch the address.

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 Port 0 with Pull-Up Resistors
Vcc
10 K

P0.0
DS5000 P0.1

Port 0
8751 P0.2
8951 P0.3
P0.4
P0.5
P0.6
P0.7

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 Port 1 （ pins 1-8 ）


• Port 1 is denoted by P1.

– P1.0 ~ P1.7
– P1 as an output port (i.e., write CPU data to the external pin)
– P1 as an input port (i.e., read pin data into CPU bus)

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 HARDWARE STRUCTURE OF
I/O P1.X PIN
Read latch Vcc
TB2
Load(L1)

Internal CPU D Q P1.X

bus P1.X pin

Write to latch Clk Q M1

TB1
Read pin data

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 Writing “1” to Output Pin
P1.X
Read latch Vcc
2. output pin is
Load(L1)
1. write a 1 to the pin Vcc
1
Internal CPU D Q P1.X
bus P1.X pin
0
Write to latch Clk Q M1

Read pin

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 Writing “0” to Output Pin
P1.X
Read latch Vcc

Load(L1) 2. output pin is

1. write a 0 to the pin Vcc
0 P1.X
Internal CPU D Q
bus P1.X pin
1
Write to latch Clk Q M1 output 0

Read pin

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 ALE Pin
• The ALE pin is used for de-multiplexing the
address and data by connecting to the G pin of
the 74LS373 latch.
– When ALE=0, P0 provides data D0-D7.
– When ALE=1, P0 provides address A0-A7.

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 Port 3 （ pins 10-17 ）
• Although port 3 is configured as an output port upon reset,
this is not the way it is most commonly used.
• Port 3 has the additional function of providing signals.
– Serial communications signal ： RxD, TxD
– External interrupt ： /INT0, /INT1
– Timer/counter ： T0, T1
– External memory accesses ： /WR, /RD

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 Port 3 Alternate Functions
P3 Bit Function Pin

P3.0 RxD 10
P3.1 TxD 11
P3.2 INT0 12
P3.3 INT1 13
P3.4 T0 14
P3.5 T1 15
P3.6 WR 16
P3.7 RD 17 

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 Registers
A

R0
DPTR DPH DPL
R1

R2 PC PC
R3

R4 Some 8051 16-bit Register

R5

R6

R7

Some 8-bitt Registers of

the 8051
Memory Map (RAM)