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Comparative Power Analysis of

CMOS and Adiabatic Logic Gates

Speaker Name
Date:
Date:03/12/2024
Sai Venu Satya Ram Lalith Vaduguru-243120101

Dr. Shyama Prasad Mukherjee

International Institute of Information
Technology, Naya Raipur

International Institute of Information Technology, Naya Raipur

 Introduction
• Introduction to CMOS and Adiabatic Logic Gates:
CMOS (Complementary Metal-Oxide-Semiconductor) logic gates dominate
digital circuits due to their simplicity, high-speed operation, and low static power
consumption.
• However, they suffer from significant dynamic and leakage power dissipation.
• Adiabatic logic gates, in contrast, aim to minimize energy loss by recovering and
reusing charge through gradual transitions and clocked power supplies.

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 Importance of Low-Power Designs
• As modern electronics evolve toward portable, wearable, and IoT devices, energy
efficiency is critical to extend battery life, reduce heat dissipation, and support
sustainable technology growth.
• Low-power designs enable compact, reliable systems, essential for meeting these
demands.

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 Objectives of the Study
• Compare power consumption between CMOS and Adiabatic designs.
• Highlight efficiency improvements in Adiabatic gates using CPAL
(Complementary Pass Transistor Adiabatic Logic).

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 Conventional CMOS Logic Gates
Overview of CMOS Logic Gates:
•Inverter: Converts input to its opposite. PMOS pulls output high when input is
low, NMOS pulls it low when input is high.
•NAND Gate: Outputs 0 only when all inputs are 1. Uses parallel PMOS and series
NMOS transistors.
•XOR Gate: Outputs 1 when inputs are different, combining CMOS stages for
exclusive OR logic.
Key Characteristics:
•Dynamic Power Dissipation: Power lost during charging/discharging of
capacitors.
•Dependence: Proportional to load capacitance (CCC), switching frequency (fff),
and supply voltage (VVV) as P∝CV2fP \propto C V^2 fP∝CV2f.
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 Adiabatic Logic Design
• Concept of Adiabatic Switching
Adiabatic design is an innovative low-power design technique used in
VLSI technology. It focuses on minimizing power dissipation by reusing energy
during the circuit’s operation. This approach deviates from conventional CMOS
design principles by employing reversible logic and recycling charge stored in
capacitors.

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 Cont.
• Key Features:
1.Energy Transfer via Constant Current Source:
A constant current source ensures gradual voltage changes during
switching, preventing rapid charging and discharging of capacitors, thus reducing
energy loss.
2.Reuse of Stored Charge in Capacitors:
The system reuses the charge stored in capacitors instead of dissipating it
as heat. This is achieved by slowly varying the supply voltage, enabling efficient
energy recovery during transitions.

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 Adiabatic Logic Gate Implementation
Conventional CMOS Inverter

No of Transistors are 2
For 180nm
Delay =0.35ns
Power consumption =0.15µW
For 90nm
Delay =0.3ns
Power consumption =0.0601µW

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 Cont.
Conventional CMOS NAND Gate
No of Transistors are 4
For 180nm
Delay =0.18ns
Power consumption =0.13µW
For 90nm
Delay =0.4ns
Power consumption =0.062µW

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 Cont.
• Conventional CMOS XOR Gate
No of Transistors are 12
For 180nm
Delay =0.55ns
Power consumption =0.7µW
For 90nm
Delay =0.5ns
Power consumption =0.364µW

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 Cont.
• Power Gating Switch using CPAL
No of Transistors are 12

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 Excepted Simulation Results
Power-
Power Delay
Logic Gate Technology Logic Type Delay (ns)
(μW) Product
(PDP) (fJ)
Inverter 90nm CMOS 0.916 0.1 91.6
Adiabatic 0.0601 0.3 18.03 Power: Adiabatic gates use much
180nm CMOS 1.8 0.12 216 less power than CMOS.
Adiabatic 0.15 0.35 52.5 Delay:Adiabatic gates are slightly
NAND 90nm CMOS 0.7055 0.15 105.825 slower due to gradual operations.
Adiabatic 0.062 0.4 24.8 PDP:Adiabatic gates are more
180nm CMOS 1.5 0.18 270 energy-efficient, ideal for low-
power needs.
Adiabatic 0.13 0.45 58.5
XOR 90nm CMOS 3.066 0.2 613.2
Adiabatic 0.364 0.5 182
180nm CMOS 5.0 0.25 1250
Adiabatic 0.7 0.55 385

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Power Savings
• Bar graph representations for the
simulated results
• CMOS (90nm): High power consumption.
• Adiabatic (90nm): Significant power savings.
• CMOS (180nm): Power increases due to larger
transistors.
• Adiabatic (180nm): Slightly higher power than
90nm but still far more efficient than CMOS.

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 Applications of Adiabatic Designs
• Portable Devices
• IoT Devices
• Medical Devices
• High-Performance Computing

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 Advantages of Adiabatic Logic
• Significant Power Savings
• Heat Reduction
• Scalability

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 Challenges and Limitations
• Complex Design:
Requires precise control of power clocks and careful timing analysis.
• Performance Overheads:
Slower operation due to gradual charging/discharging processes.
• Area Penalty:
Additional components (e.g., clocking circuitry) can increase the silicon area.

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 Conclusion
• Adiabatic logic is much more power-efficient than CMOS logic due to energy
recovery during operation, significantly reducing power dissipation.
• Adiabatic logic's efficiency makes it a strong candidate for future low-power
technologies, despite its design complexity.

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 References
• H. Sharma and R. Singh, "Comparative power analysis of CMOS & adiabatic logic gates," IEEE, 2015.
• S. Wairya, R. K. Nagaria, and S. Tiwari, "Comparative performance analysis of XOR-XNOR function-based high-speed CMOS full
adder circuits for low voltage VLSI design," Int. J. VLSI Design & Commun. Syst. (VLSICS), vol. 2, no. 4, pp. 123-133, 2012.
• N. S. Kim and T. Austin, "Leakage current: Moore's law meets static power," Computer, vol. 36, no. 12, pp. 68-74, 2003.
• F. Fallah and M. Pedram, "Standby and active leakage current control and minimization in CMOS VLSI circuits," IEICE Trans.
Electron., vol. E88-e, no. 4, pp. 520-528, 2005.
• J. G. Koller, L. Svensson, and W. C. Athas, "An energy-efficient CMOS line driver using adiabatic switching," in Proc. Great Lakes
Symp. VLSI, 2005, pp. 243-246.
• R. Singh, A. Sharma, and R. Singh, "Power efficient design of multiplexer-based compressor using adiabatic logic," Int. J. Comput.
Appl., vol. 81, no. 10, pp. 12-16, 2013.
• C. H. Chang, J. Gu, and M. Zhang, "Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits,"
IEEE Trans. Circuits Syst., vol. 51, no. 1, pp. 114-118, 2004.
• Y. Jiang, M. Al-Sheraidah, Y. Wang, E. Sha, and J. G. Chung, "A novel multiplexer-based low-power full adder," IEEE Trans.
Circuits Syst. II: Express Briefs, vol. 51, no. 9, pp. 450-454, 2004

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..

Thank You

Dr. Shyama Prasad Mukherjee International Institute

of Information Technology, Naya Raipur

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