What is System-on-Chip?
Application Specific Chip with:
Embedded hard/soft/firm processor
cores
Embedded memories
GPP DSP Multiple peripherals
Modules interconnected via “standard”
Memory
busses
Periphera User logic 500K+ gates
ls
User logic Analog
Analog Modules ( ADC, DAC)
Application S/W for the processor
core(s)
1
Why SoCs: Potential chip-level savings?
A typical broadband application consists of following chips: DSP, CPU, Data
Converters, ASIC/FPGA (Peripherals and Custom Logic), Ethernet, and Memories.
Memory Ethernet Data
Memory Phy
CPU DSP ASIC Converter
$9 - $10 s
$1.5 $5 $5 $15 - $2.5
$20
Die area
Number of SoC reduction
packages
$16 - $24
in
reduced from 5
integrated
1.
solution
Typical chip-level Savings of 30% - 45% using SoC
2
Why SoCs: Potential board-level savings
1998 Memory F Memory
Internet
Ethernet P
Switch CPU DSP
G Area: ~32 sq. in.
Power: ~6 Watts
SLIC SLAC
A Cost: ~$100
2003
Memory Area: ~8 sq. in. IMPROVEMENTS
Power: ~1.5 Watts
Internet Cost: <$25 Area: 4x
SOC
Power:
SLIC
4x
Cost: 4x
Advanced technologies enabling more integration on a chip
Reduced Product Cost.
Physical size of products shrinking Minimize number of parts on a
board.
Consumer electronics requiring low cost products More
integration.
Minimize number of silicon vendors for a product Reduced 3
Business Cost.
Needs for SoC design Methodology:
Time-to-Market extremely important for business.
Easy integration of Intellectual Properties (IPs) Cores from
multiple sources.
Resource management
• Minimize number of resources required to complete a
design.
• Efficiently manage resources across projects.
• Share domain expertise across multi-site design teams.
• Make effective use of design automation.
Advancement in technology : Handle Increased Complexity of
Integration.
Maximize Performance.
Manage Feature Creep and Engineering Changes quickly.
SOC LOGIC CORES available in three forms:
Soft
Firm
Hard
4
5
DESIGN METHODOLOGY FOR SOC LOGIC
CORES
1. General Guidelines for Design Reuse
2. Design Process for soft and firm cores
3. Design Process for Hard Cores
Clock and Reset
Pin Placement, and Aspect Ratio
6
• Design Reuse a MUST for SoC success:
Design reuse is the inclusion of previously designed components (e.g., intellectual
property (IP) in software and hardware. Reusing designs makes it quicker, easier, and
less expensive to design and build a new product. That's because existing components
much more re reliable and well-tested than new components.
Design reuse can expedite system-on-chip (SoC) and IC design and development.
General Guidelines for DESIGN REUSE:
● Synchronous Design
● Memory and Mixed‐Signal Design
● On‐Chip Buses
● Clock Distribution
● Clear/Set/Reset Signals
● Deliverable Models
SYNCHRONOUS DESIGN
● Use registers for synchronization in core
logic and its inputs and outputs to manage
core
● Creates a wrapper around a core.
❖ portability
❖ manufacturing test application
● Avoid latches in random logic
Use them only in blocks such as
FIFOs, memories, and stacks
• Avoid asynchronous loops.
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M E M O RY AND MIXED‐SIGNAL DESIGN
● Large memories: different parasitics at boundary cells and a cell
in the middle of an array.
Include rows and columns of dummy cells at the
periphery of large memories.
Make these rows and columns part of the built‐in self
repair (BISR) mechanism, to minimize area overhead.
● most commonly used analog/mixed‐ signal circuits ‐
used in SoC, ADCs/DACs, and temperature sensors. .
extremely sensitive to noise and technology
parameters place them at the corners.
ON‐CHIP B U S E S
● On‐chip buses and data transaction protocol must be
designed prior to the core selection process.
● Parameterized interfaces should be used in core design.
❖ FIFO‐based interfaces are flexible and versatile in handling varying data rates between cores and
the system buses.
❖ support multiple masters, separate entity for data and control signals, fully synchronous and
multiple cycle transactions, bus request‐and‐grant protocol.
C L O C K D I S T RI BU T I O N
● Isolate each clock in an independent domain.
● Use buffers at the clock boundary.
● Use synchronization method at the clock boundaries.
E.g., clock buffering and dual stage FIFOs at the clock boundary.
● Distribute a low‐frequency chip‐level synchronization.
CLEAR/SET/RESET S I G N A L S
● Document all reset schemes for the entire design:
Synchronous/asynchronous, internal/external power‐on‐resets.
any software reset schemes used, does any functional block has local
generated resets check.
Check whether resets are synchronized with local clocks.
● Use synchronous reset if possible
avoids race conditions on reset.
static timing analysis difficult with asynchronous resets.
DESIGN PROCESS OF SOFT/FIRM CORES
● Design with a conventional
EDA RTL synthesisflow.
● Reusability requirement
n
DESIGN PROCESS OF HARD CORES
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D E V E L O P M E N T P R O C E S S F O R SOC CORES
● Required design specification at every step in development process:
1. Functional (purpose and operation)
2. Physical (packaging, area, power, technologylibraries, …)
3. Design requirements (architecture and block diagrams with dataflow)
4. Interface requirements to specify signal names and functions, timing
diagrams, and DC/AC parameters
5. Test and debug (testing, DFT methodology, test vector
generation method)
6. Software requirements
