Unit-3

AVR MICROCONTROLLER
 Contents
The AVR RISC microcontroller architecture:
• Introduction
• AVR family architecture
• register file
• Pin diagram of AVR
• memory organization
• I/O ports
• timers
• USART
• Interrupt structure.
AVR MICROCONTROLLER
INTRODUCTION
• The architecture of AVR was developed by Alf-Egil Bogen and Vegard Wollan. AVR derives its
name from its developers and stands for Alf-Egil Bogen Vegard Wollan RISC microcontroller, also
known as Advanced Virtual RISC.
• The AT90S8515 was the first microcontroller which was based on AVR architecture.
• However the first microcontroller to hit the commercial market was AT90S1200 in the year 1997.

• AVR microcontrollers are available in three categories:

TinyAVR – Less memory, small size, suitable only for simpler applications

MegaAVR – These are the most popular ones having good amount of memory (upto 256 KB),
higher number of inbuilt peripherals and suitable for moderate to complex applications.
XmegaAVR – Used commercially for complex applications, which require large program
memory and high speed.
AVR MICROCONTROLLER
INTRODUCTION
• The following table compares the above mentioned AVR series of
microcontrollers:
AVR MICROCONTROLLER
INTRODUCTION
• What’s special about AVR?
AVR MICROCONTROLLER
INTRODUCTION
• AVR is an 8-bit microcontroller belonging to the family of Reduced Instruction Set Computer
(RISC). In RISC architecture the instruction set of the computer are not only fewer in number
but also simpler and faster in operation.
• This microcontroller is capable of transmitting and receiving 8-bit data. The input/output
registers available are of 8-bits. The AVR family controllers have register based architecture
which means that both the operands for an operation are stored in a register and the result of
the operation is also stored in a register.
• The specific aspect of RISC is that almost all instructions execute in one machine cycle.
• The next RISC principle adopted by AVR is the load-store architecture which means that the
only instructions that access memory are load and store.
• Load instruction loads data from memory into the register where as store moves the data from
register into the memory.
• For an ALU instruction to be executed the operands are brought into the registers using LOAD
and the result is stored back in the memory after execution.
• Another aspect of RISC architecture is larger register file which is taken care by the AVR design.
AVR MICROCONTROLLER
INTRODUCTION
Atmega16 microcontroller, which is a 40-pin IC and belongs to the megaAVR category of AVR family. Some of the
features of Atmega16 are:
 16KB of ISP Flash memory
 1KB of SRAM
 512 Bytes of EEPROM
 Available in 40-Pin DIP
 8-Channel 10-bit ADC
 Two 8-bit Timers/Counters
 One 16-bit Timer/Counter
 4 PWM Channels
 Serial USART
 SPI Interface
 Digital to Analog Converter.
AVR MICROCONTROLLER
Architecture
• The Atmel®AVR®ATmega32 is a low-power CMOS 8-bit microcontroller based on the AVR
enhanced RISC architecture. By executing powerful instructions in a single clock cycle,
the ATmega32 achieves throughputs approaching 1 MIPS per MHz
Atmega32 Features:
• 2 Kilo bytes of internal Static RAM
• 32 X 8bit general working purpose registers
• 32 Kilo bytes of in system self programmable flash program
memory.
• 1024 bytes EEPROM
• Programmable serial USART
• 8 Channel, 10 bit ADC
• One 16-bit timer/counter with separate prescaler, compare mode
and capture mode.
AVR MICROCONTROLLER
Architecture
• Two 8-bit timers/counters with separate prescalers and compare modes
• Available in 40 pin DIP, 44-pad QFN(Quad Flat no lead)/MLF(Micro lead
frame) and 44-lead QTFP(thin quad flat package)
• 32 programmable I/O lines
• In system programming by on-chip boot program
• Master/slave SPI serial interface
• 4 PWM channels
• Programmable watch dog timer with separate on-chip oscillator
• a JTAG interface for Boundary scan, On-chip Debugging support and programming
• a serial programmable USART
• A Two Wire Interface(I2C) for serial communication
• six software selectable power saving modes(Idle mode, Power-down mode, Power-save
mode, ADC Noise Reduction mode, Standby mode, Extended Standby mode )
 AVR MICROCONTROLLER
Architecture
• The Idle mode stops the CPU while allowing the USART, Two-wire interface, A/D Converter, SRAM,
Timer/ Counters, SPI port, and interrupt system to continue functioning.
• The Power-down mode saves the register contents but freezes the Oscillator, disabling all other
chip functions until the next External Interrupt or Hardware Reset.
• In Power-save mode, the Asynchronous Timer continues to run allowing the user to maintain a
timer base while the rest of the device is sleeping.
Note: The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external 32kHz
clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when the device is in sleep
mode.
• The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and
ADC, to minimize switching noise during ADC conversions.
• In Standby mode, the external crystal/resonator clock remains running while the rest of the device
is sleeping.
• In Extended Standby mode, both the external crystal/resonator clock and the Asynchronous Timer
continue to run.
Architecture of AVR
• The architecture of AVR is divided into two parts:
1)The core: Computing Engine of the microcontroller.
2)Peripherals: No. and type of peripherals vary between different microcontrollers.
Function of the core is to ensure correct program execution.
It has an 8-bit data BUS and the memory is based on Harvard Architecture(Data memory
and program memory and associate BUSES are separate).
Instructions in the program memory are executed with single level pipelining i.e while one
instruction is being executed the next instruction is prefetched from the program memory.
Fig: AVR MCU ARCHITECTURE
Architecture of AVR
Atmel's ATmega32 is an 8-bit RISC processor, based on Harvard architecture.
On-chip Memory: Atmega32 consist of three different memory sections
1)Flash EEPROM: Flash EEPROM or simple flash memory is used to store the program dumped or burnt by
the user on to the microcontroller. It can be easily erased in blocks. Flash memory is non-volatile i.e., it
retains the program even if the power is cut-off. Atmega32 is available with 32KB of in system programmable
Flash EEPROM. Program Flash memory space is divided in two sections, the Boot program section and the
Application Program section. On-chip Boot program running on the AVR core can use any interface to
download the application
program in the Application Flash memory.
2) EEPROM: This is also a nonvolatile memory used to store data which is more or less a constant once the
design is finalized. Atmega32 has 1KB of EEPROM.

3)

The Size of SRAM in Atmega32 is 2KB.During interrupts and subroutine calls, the return address Program
Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM
Architecture of AVR
Program Counter:

For Each Member of the AVR series ,the bit size of the program counter corresponds to how much of program memory is
available. For Atmega32 chip ,there is 32KB of ROM organized as 16K x 16-bits.For address numbering to 16K(24 x 210 =214 ),14
bits are needed and hence this microcontroller has 14-bit PC.

Register File:
Atmega32 is equipped with 32 general purpose registers of 8-bit size, which are coupled directly with the Arithmetic Logical
Unit (ALU) of CPU. These registers are used as operand registers for computation . Of these 32 registers, 6 registers can be
used as address registers to act as data address pointers.(Two registers each from X, Y, Z registers)
• The I/O memory space contains 64bytes of space for CPU peripheral functions such as Control Registers, SPI, and other I/O
functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, $20
- $5F.
Note: The registers have names as well as addresses which correspond to the locations in RAM space.
Architecture
of AVR
• When using the I/O
specific commands IN
and OUT, the I/O
addresses $00 - $3F
must be used. When
addressing I/O Registers
as data space using LD
and ST instructions, $20
must be added to these
addresses
Architecture of AVR
• Status and Control Register: After an arithmetic operation, the Status Register is updated
to reflect information about the result of the operation. The Status Register contains
information about the result of the most recently executed arithmetic instruction. This
information can be used for altering program flow in order to perform conditional
operations.

Fig: Status register

Architecture of AVR
I/O Ports: Atmega32 has four (PORTA, PORTB, PORTC and PORTD) 8-bit input-output ports. In
Atmega32, I/O operations are controlled through three types of registers: DDRX (Data Direction
Register), PORTX (Port Output Register), and PINX (Port Input Register).
Internal Calibrated Oscillator: Atmega32 is equipped with an internal oscillator for driving its clock.
By default Atmega32 is set to operate at 1 MHz . The maximum frequency of internal oscillator is
8MHz. Alternatively, ATmega32 can be operated using an external crystal oscillator with a maximum
frequency of 16MHz.
ADC Interface: Atmega32 is equipped with an 8 channel ADC (Analog to Digital Converter) with a
resolution of 10-bits.
Timers/Counters: Atmega32 consists of two 8-bit and one 16-bit timer/counter. Timers are useful for
generating time delays between two operations.(T0 and T2:8-bit Timers, T1:16-bit timer)
• Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
• 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode

Watchdog Timer: The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at
1MHz.Watchdog timer continuously monitors and resets the controller if the code gets stuck at any
execution point for more than a defined time interval.
Architecture of AVR
Interrupts: Atmega32 consists of 21 interrupt sources out of which three are
external(INT0,INT1,INT2).Upon activation of these interrupts the Atmega32 controller gets
interrupted in whatever task it is doing and jumps to perform Interrupt Service Routine. The
remaining are internal interrupts which support various operations in the microcontroller like USART,
ADC, Timers etc.
USART: Universal Synchronous and Asynchronous Receiver and Transmitter interface is available
for interfacing with external device capable of communicating serially by using TXD and RXD pins.
SPI: Serial Peripheral Interface, SPI port is used for serial communication between two devices on a
common clock source. The data transmission rate of SPI is more than that of USART.
TWI(I2C): Two Wire Interface (TWI) can be used to set up a network of devices, many devices can be
connected over TWI interface forming a network, the devices can simultaneously transmit and receive
and have their own unique address.
MCU Timing and Control: It is used for the generation of timing and control signals.
Architecture of AVR
• The Analog Comparator compares the input values on the positive pin AIN0 and negative
pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the
negative pin AIN1, the Analog Comparator Output, ACO, is set. The comparator’s output
can be set to trigger the Timer/Counter1 Input Capture function. In addition, the
comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
Register File
• The register file is optimized for the AVR enhanced RISC instruction set. Most of the
instructions that operate on the register file have direct access to all the registers.
• Most of these instructions are just single instruction that run in one clock cycle . Since there
are 32 of these registers combined with direct accessibility by the ALU, programmers can
have more registers for storage of values for faster processing.

• Figure in the next slide shows the structure of the 32 general purpose working registers in
the CPU:
Register File
Register File
• Each register is also assigned a data memory address, mapping them directly into the first
32 locations of the user Data Space , although not being physically implemented as SRAM
locations.
• The registers R26..R31 have some added functions to their general purpose usage.
• These registers are 16-bit address pointers for indirect addressing of the Data Space. The
three indirect address registers X, Y, and Z are defined as described in figure in the next
slide:
• The registers have names as well as addresses which correspond to their location in RAM
space.
• The registers R27 and R26 are concatenated to form the X-register ,R29 and R28 to form
the Y register ,R31 and R30 to form the Z Register
AVR general purpose Registers
Register File
• Status and Control Register: After an arithmetic operation, the Status Register is updated
to reflect information about the result of the operation. The Status Register contains
information about the result of the most recently executed arithmetic instruction. This
information can be used for altering program flow in order to perform conditional
operations.

Fig: Status register

• Bit 7 – I: Global Interrupt Enable:The Global Interrupt Enable bit must be set for the
interrupts to be enabled.
• Bit 6 – T: Bit Copy Storage
• The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or
destination for the operated bit. A bit from a register in the Register File can be copied into
T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register
File by the BLD instruction.
Register File
• Bit 5 – H: Half Carry Flag(Auxiliary Carry): The Half Carry Flag H indicates a Half Carry in
some arithmetic operations. This bit is set to 1 , when a carry is generated after four bits.
• Bit 4 – S: Sign Bit, S = N ⊕ V :The S-bit is always an exclusive or between the Negative Flag N
and the Two’s Complement Overflow Flag V.
• Bit 3 – V: Two’s Complement Overflow Flag: The Two’s Complement Overflow Flag V
supports two’s complement arithmetic. Overflow flag indicates that result is too large to fit
in the 8-bit destination operand.
• Bit 2 – N: Negative Flag:The Negative Flag N indicates a negative result in an arithmetic or
logic operation
• Bit 1 – Z: Zero Flag:The Zero Flag ‘Z’ indicates a zero result in an arithmetic or logic
operation
• Bit 0 – C: Carry Flag: The Carry Flag C indicates a carry in an arithmetic or logic operation
Register File
• Stack Pointer:The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the
Stack. The Stack Pointer must be set to point above $60.
• The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is
decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt.
• The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is
incremented by two when data is popped from the Stack with return from subroutine RET or return from
interrupt RETI. The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space.
• The number of bits actually used is implementation dependent. Note that the data space in some
implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will
not be present.

To push a register onto a stack, we use PUSH instruction.

PUSH Rr;
Rr can be any general-purpose register (R0 - R31)
Register File
To retrieve back the data from the stack, we use POP instruction.
POP Rr;
Rr can be any general-purpose register (R0 - R31)
PC(Program Counter):Program Counter contains the address of the next instruction to be executed in the
flash program memory. For Atmega32 chip ,there is 32KB of ROM organized as 16K x 16-bits.For address
numbering to 16K(24 x 210 =214 ),14 bits are needed and hence this microcontroller has 14-bit PC.
IR(Instruction Register):The instruction register (IR) is the part of a CPU's control unit that holds the
instruction currently being decoded. When the CPU fetches an instruction from memory, it is stored in the IR,
and the Control Unit decodes the instruction and executes it. The IR is an important part of the CPU's pipeline,
which is a technique used to increase the CPU's processing speed by overlapping the execution of multiple
instructions. By fetching the next instruction while the current instruction is being executed, the CPU can reduce
the amount of time spent waiting for instructions to be fetched, which can improve its overall performance.
PIN DIAGRAM OF AVR(Atmega32)
 PIN DESCRIPTION OF AVR

Atmega32 is a 40-pin IC with 4 8-bit ports named as

PA,PB,PC,PD constituting 32 GPIO lines. All port pins
have dual functions.
ATMega32 gives four power pins, power input for digital
pins and analog power input for ADC and the remaining
two are ground pins.
 VCC: Digital supply voltage (PIN-10)
 AVCC(PIN-30): It should be externally connected to
VCC, even if the ADC is not used. If the ADC is used, it
should be connected to VCC through a low-pass filter.
 GND(PIN11,PIN31): Ground
 Port A (PA7..PA0): PIN 33 to 40 come under PORT A.
Port A serves as the analog inputs to the A/D Converter.
Port A also serves as an 8-bit bi-directional I/O port, if
the A/D Converter is not used. Port pins are provided
with internal pull-up resistors.
PIN DESCRIPTION OF AVR
• Port B (PB7..PB0) : Port B is an 8-bit bi-directional I/O port with internal pull-up resistors.
Port B also serves the functions of various special features of the ATmega16
PIN DESCRIPTION OF AVR
(PB4-PB7):
SS’ – GPIO5
MOSI – GPIO6
MISO – GPIO7
SCK – GPIO8
SPI: SPI protocol is one of the best serial communication protocols for communication with multiple modules. It
can be used in the case when multiple peripherals have to communicate efficiently with the microcontroller. The
communication wires consist of two wires for data to support full duplex communication(MOSI ,MISO) and
one for the clock(SCK), and also a wire which is used for device selection. The device selection pin is knowing as
Select Slave pin and it is predefined in the micro controller but any output pin can be made as a select slave
pin(SS’) by programming. SPI protocol is not only used for communication, but it can also be used to program
the microcontroller.
PIN DESCRIPTION OF AVR
(PB3-PB2),PD2,PD3:
Analog Comparator: To compare two analog signals an analog comparator is used in the
microcontroller.
AN0(Analog Comparator positive input) – PB2
AN1 (Analog Comparator negative input) – PB3
PB3(Timer/Counter0 Output Compare Match Output): The Output Compare Register of
timer/counter0 contains an 8-bit value that is continuously compared with the counter value (TCNT0)
to generate an output signal on OC0 pin. The pin has to be configured as an output (DDB3 set (one))
to serve this function. The OC0 pin is the output pin for the PWM mode timer function.
• INT2(PB2):External Interrupt 2
• INT0(PD2) – GPIO16
• INT1(PD3) – GPIO17
In this microcontroller, there are total three interrupt pins which can be used by external
modules or by an external button to get the attention of CPU.
 PIN DESCRIPTION OF AVR
PB1-PB0:
T0/XCK – Port B, Bit 0
XCK(USART EXTERNAL CLOCK):This pin acts as the clock pin when USART operates in synchronous mode.
The Data Direction Register (DDB0) controls whether the clock is output (DDB0 set) or input (DDB0
cleared).
T0(T0, Timer/Counter0 Counter Source)
T1 – Port B, Bit 1(T1, Timer/Counter1 Counter Source)
The frequency of external pulses connected to T0 and T1 pin are counted . Timer/counter
0 and Timer/Counter 1 should be configured as a counter to count the external clock
pulses.
PIN DESCRIPTION OF AVR
• Port C (PC7..PC0):Pins 22-29
PIN DESCRIPTION OF AVR
PC7: TOSC2( TOSC2, Timer Oscillator pin 2 )
PC6: TOSC1(Timer Oscillator pin 1)
• Timer2 can be operated in the asynchronous mode by connecting an external crystal oscillator
betweenTOSC1 AND TOSC2 pins.(When the AS2 bit in the ASSR Register is written to logic one, the clock source is
taken from the Timer/Counter Oscillator connected to TOSC1 and TOSC2 .)
(PC2-PC5):
These pins are present in most of the boards for testing purposes . JTAG could be connected to the internal
test port , it can also be used for programming the microcontroller and even the bootloader . The JTAG
interface is a standard for testing and debugging electronic devices and systems and it uses a serial
communication protocol to access and control the devices internal registers. JTAG pins in the microcontroller
are:
TDI(test data in)-PC5:used to input test data into the device during a JTAG operation
TDO(test data out)- PC4:used to ouput test data from the device during JTAG operation.
TMS( test mode selects)– PC3:shifts the JTAG state machine from one state to the next.
TCK (JTAG Test Clock )– PC2:Used to provide clock signal for JTAG operations. Clock is generated by an external
test equipment such as a JTAG debugger.
PIN DESCRIPTION OF AVR
PC1 - SDA
PC0 - SCL
I2C: Some sensors and servos come with serial communication protocol called I2C(Inter
Integrated Circuit). To communicate with those peripherals ATMega32 also gives I2C pins
interface. One pin is used for data communication and one for a clock. Both pins are listed
below:
• SDA(Serial Data) – GPIO23
• SCL(Serial Clock) – GPIO22
PIN DESCRIPTION OF AVR
• Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors
(selected for each bit). Port D also serves the functions of various special features of the
ATmega32
PIN DESCRIPTION OF AVR
PD7-OC2 (OC2, Timer/Counter2 Output Compare Match output): The Output Compare Register of
Timer/counter2 contains an 8-bit value that is continuously compared with the counter value (TCNT2).
A match can be used to generate an output compare interrupt, or to generate a waveform output on
the OC2 pin. The pin has to be configured as an output (DDD7 set (one)) to serve this function. The
OC2 pin is the output pin for the PWM mode timer function.
PD6-ICP1 (Input Capture Pin): The Timer/Counter value at a given external (edge triggered)
event can be captured on the Input Capture Pin.
OC1A – PD5
OC1A, Output Compare Match A output: The PD5 pin can serve as an external output for the
Timer/Counter1 Output Compare A. The pin has to be configured as an output (DDD5 set (one)) to
serve this function. The OC1A pin is the output pin for the PWM mode timer function.
OC1B – PD4
OC1B, Output Compare Match B output: The PD4 pin can serve as an external output for the
Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDD4 set (one)) to
serve this function. The OC1B pin is the output pin for the PWM mode timer function.
PIN DESCRIPTION OF AVR
• TXD – PD1
TXD, Transmit Data (Data output pin for the USART). When the USART Transmitter is enabled,
this pin is configured as an output regardless of the value of DDD1.
• RXD – PD0
RXD, Receive Data (Data input pin for the USART). When the USART Receiver is enabled this
pin is configured as an input regardless of the value of DDD0.
PIN DESCRIPTION OF AVR
• RESET(Pin-9) Reset Input. A low level on this pin for longer than the minimum pulse
length will generate a reset.
• External Oscillator: ATMega32 has internal oscillator which can be configured up to 8MHz
but to extend the clock speed till 16MHz , an external oscillator will be used at the
oscillator pins of the microcontroller which are given below:
XTAL2 – GPIO12
XTAL1 – GPIO13
• AREF: AREF is the analog reference pin for the A/D Converter.(The voltage of the AREF
should be in between 0V and AVcc)
Memory Organization
• In Atmega32 there are two kinds of Memory space:
Code Memory(where program is stored)
Data Memory(where data is stored)
• The Data Memory space has three components:
General Purpose Registers
I/O Memory
Internal SRAM
The General Purpose Registers use 32 bytes of the Data Memory space. They
take the address location $00 to $1F in the data memory space.
Memory Organization
• I/O Memory: The I/O memory is dedicated to specific functions such as status register,
timers, serial communication ,I/O ports, ADC and so on .
• The function of each of the I/O memory location is fixed at the time of design because it is
used for the control of the microcontroller or peripherals . The AVR I/O memory is made of
8-bit registers .
• The Atmega32 microcontroller has 64bytes of I/O memory locations . The 64-byte section is
called the standard I/O Memory . The I/O registers are also called as special function
registers since each one is dedicated to a special function.
Memory Organization
• When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be
used. When addressing I/O Registers as data space using LD and ST instructions, $20 must
be added to these addresses.
Memory Organization
• Internal Data SRAM: Size of SRAM in Atmega32 is 2KB.It is widely used for storing data and
parameters by AVR programmers and C compilers. It is also called as scratch pad.
• Each location in the SRAM can be directly accessed by its address. Each location is 8-bits
wide.
• The three parts of the memory (GPR’S, SFR’S and Data SRAM ) are made of SRAM.
• EEPROM:Atmega32 has an EEPROM of size 1KB. EEPROM is used for storing data that
should be rarely changed and should not be lost when the power is off.
Memory Organization

The program memory of any AVR microcontroller is word addressable.

In case of a 14-bit program counter the code space is 16K(214) which occupies the
0000-$3FFF address range.

-tion where the startup code is written.

-tions starting at 0000.

I/O Ports
• Atmega32 has 4 ports each having 8 pins. PortA, PortB, PortC and PortD.
• To use any of these ports as an input or output port , it must be programmed .
• In addition to being used as a simple I/O port each port has some other
functions such as ADC , timers, interrupts and serial communication pins.
 I/O Ports

DDRB represents the direction of PB0 pin and so on.

I/O Ports
DDRX Register:
I/O Ports

for that port and then bring in the data present at the pins. When DDR contains 0’S the port gets data.
• Upon reset ,all ports have the value 0x00 in their DDR registers . This means all ports are configured
as inputs.
I/O Ports
• PINx and PORTx:

• PORTX register dual role:

I/O Ports
Note: There is a pull up resistor for
each of the AVR pins. If we put 1’s
into the pins of PORTx register the
pull up resistors are activated. If we
put 0’s into the bits of the PORTx
register, the pull-up resistor is
inactive.
I/O Ports
I/O Ports
Timers

Hence there are timer/counter registers for this purpose.

A General View of Timers and
Counters in Microcontrollers
Timers
Timers
• In Atmega32 there are three timers
Timer0
Timer1
Timer2
Timer0 and Timer2 are 8-bit timers while timer1 is a 16-bit timer.

through one of the AVR pins . This is called a counter.

Timers
• In AVR each timer has TCNTn register. That means in Atmega32 we have
TCNT0,TCNT1,TCNT2 registers.
• Upon reset TCNTn contains zero.It counts up(increments) with each pulse.
• The contents of the timers/counters can be accessed using TCNTn register.We can load a
value into TCNTn or we can even read its value.
• Each timer has a TOVn(Timer Overflow) flag as well. When a timer overflows its TOVn flag
will be set.
Timers
Timers in Atmega32
Timers
• Timer0:

• TCCR0 Register:
TCCR0 is an 8-bit register and used for the control of timer0.
Timers
• Timer/Counter Interrupt flag register(TIFR):This register contains the
flags of different timers.
Timers
• TOV0 Flag: The TOV0 flag is set when the timer rolls over from $FF to 00 and it remains set until the software clears it.

-itored.

CTC Mode(Clear Timer0 on Compare Match):The OCR0 register is used with CTC mode.In the CTC mode the timer is
incremented with the clock. But it counts up until the contents of TCNT0 register becomes equal with the contents of OCR0
register. Then the timer will be cleared and the OCF0 flag will be set.
Timer 2:
• Like timer0 , Timer2 also has the above set of registers and hence the working of timer0 and timer 2 are almost
similar with few differences.

For timer0 and timer2.

meanings for Timer0 and Timer2.
Timers
• TCCR2(Timer/ counter Control Register 2):

Asynchronous Status Register:

Timers
Timer1 : Timer1 is a 16-bit timer.

• These are referred to as TCNT1L (Timer1 lower byte) and TCNT1H(Timer1 higher Byte)

1:256, 1:1024.
• There are two OCR registers each of 16-bit in timer1:OCR1A and OCR1B.There are two separate flags for
each of the OCR registers which act independently of each other.
• When TCNT1 equals OCR1A, THE OCF1A flag will be set. When the TCNT1 equal OCR1B the OCF1B flag will
be set.
• There is also an auxiliary register named ICR1(Input Capture Register) which is used in operations such as
capturing.ICR1 is a 16-bit register made of ICRH and ICRL.
Timer1 High and low Registers

Simplified diagram of timer1

USART
USART

UDR: Universal Data Register

Simplified USART BLOCK DIAGRAM
USART
• UCSR Registers(USART CONTROL STATUS REGISTERS):

• UCSRA Register:

• Bit 7 – RXC: USART Receive Complete

This flag bit is set when there is unread data in the receive buffer. The RXC Flag can be used to generate a Receive
Complete interrupt.
• Bit 6 – TXC: USART Transmit Complete
This flag bit is set when the entire frame from Tx Buffer is shifted out and there is no new data currently present
in the transmit buffer (UDR). The TXC Flag can generate a Transmit Complete interrupt.
USART
• Bit 5 – UDRE: USART Data Register Empty
• If UDRE is one, the buffer is empty which indicates the transmit data buffer (UDR) is ready to receive new data.
The UDRE Flag can generate a Data Register Empty Interrupt. UDRE is set after a reset to indicate that the
transmitter is ready.
USART
• UCSRB Register:
USART
• UCSRC Register:
USART
 USART
• Universal Baud Rate Register:
USART

FIG:UBRR REGISTER
USART
Interrupt Structure
• A single microcontroller can serve several devices. There are two methods by
which devices receive service from the microcontroller.
1. Interrupts
2. Polling
In the interrupt method whenever any device needs microcontroller’s service ,
the device notifies it by sending an interrupt signal. Upon receiving the
interrupt signal the microcontroller stops whatever it is doing and serves the
device.
The program associated with the interrupt is called Interrupt service Routine or
Interrupt Handler.
The group of memory locations set aside to hold the addresses of ISRs is called
the interrupt vector table.
Interrupt Structure

Interrupt Vector Table of Atmega32

Interrupt Structure
• Sources of Interrupts in AVR:
Interrupt Structure
• Upon reset all the interrupts are disabled(masked). The interrupts must be enabled by software in
order for the microcontroller to respond to them.
• The D7 bit(I-bit) of the SREG(Status Register) is responsible for enabling and disabling interrupts
globally . With a single instruction “CLI” (Clear Interrupt) we can make I=0 during the operation of a
critical task.
• All interrupts are assigned individual enable bits which must be written logic one together with the
Global Interrupt Enable bit in the Status Register in order to enable the interrupt
Interrupt Structure
• The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The
complete list of vectors is shown below. The list also determines the priority levels of the different interrupts. The
lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External
Interrupt Request0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the
IVSEL bit in the General Interrupt Control Register (GICR).
Interrupt Structure
• The Reset Vector can also be moved to the start of the boot Flash section by programming the
BOOTRST fuse.
• There are basically two types of interrupts.
1. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program
Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine,
and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing
a logic one to the flag bit position(s) to be cleared.
2. The second type of interrupts will trigger as long as the interrupt condition is present. These
interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the
interrupt is enabled, the interrupt will not be triggered.
External Interrupts: There are three external hardware interrupts in Atmega32.They are INT0,INT1 and INT2.
• The hardware interrupts must be enabled before they can take effect. These interrupts are controlled by the
following registers:
1. GICR
2. GIFR
3. MCUCR
4. MCUCSR
Interrupt Structure
• GICR(General Interrupt Control Register): The General Interrupt Control Register controls the placement of the
Interrupt Vector table.

• INT0:When this bit is ‘1’ and global interrupt bit in SREG is ‘1’ the external interrupt INT0 is
enabled. The ISC01 and ISC00 of MCUCR register control when the interrupt is to be
activated(Rising or falling edge or level triggered)
• INT1:When this bit is ‘1’ and global interrupt bit in SREG is ‘1’ the external interrupt INT1 is
enabled. The ISC11 and ISC10 of MCUCR register control when the interrupt is to be
activated(Rising or falling edge or level triggered)
• INT2:When this bit is ‘1’ and global interrupt bit in SREG is ‘1’ the external interrupt INT2 is
enabled. The ISC2 of MCUCSR register control when the interrupt is to be activated(Rising or
falling edge)
Interrupt Structure
• INT0 and INT1 can be edge triggered or level triggered but INT2 can only be edge
triggered.
• The MCUCR and MCUCSR registers decide the triggering options of the external hardware
interrupts INT0,INT1 and INT2.
Bit 1 – IVSEL: Interrupt Vector Select
• When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the
Flash memory. When this bit is set (one), the interrupt vectors are moved to the beginning
of the Boot Loader section of the Flash.
Bit 0 – IVCE: Interrupt Vector Change Enable
• The IVCE bit must be written to logic one to enable change of the IVSEL bit
Interrupt Structure
• MCUCR(MCU Control Register):The MCU Control Register contains control bits for
interrupt sense control and general MCU functions.

• ISC01 and ISC00(Interrupt Sense Control Bits):These bits define whether the signal should
be level or edge triggered at INT0 pin.
Interrupt Structure
• ISC11 and ISC10: These bits define whether the signal should be level or edge triggered at
INT1 pin.

• MCUCSR(MCU Control and Status Register):

ISC2:This bit controls the INT2 interrupt trigger condition

ISC2 =0:The interrupt is detected on falling edge
ISC2 =1: The interrupt is detected on rising edge
Interrupt Structure
• General Interrupt Flag Register(GIFR):

Bit 7 – INTF1: External Interrupt Flag 1

When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1 becomes set (one). If the I-bit
in SREG and the INT1 bit in GICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag
is cleared when the interrupt routine is executed.
Bit 6 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set(one). If the I-bit
in SREG and the INT0 bit in GICR are set (one), the MCU will jump to the corresponding interrupt vector. The flag
is cleared when the interrupt routine is executed.
Bit 5 – INTF2: External Interrupt Flag 2
• When an event on the INT2 pin triggers an interrupt request, INTF2 becomes set (one). If the I-bit in SREG and
the INT2 bit in GICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared
when the interrupt routine is executed
 Interrupt Structure(CHAT GPT)

The ATMega16 microcontroller has a flexible interrupt system that allows the user to
handle interrupt requests from various peripherals and external devices.
The interrupt structure of the ATMega16 consists of the following components:
1.Interrupt Vector Table: This is a table of memory addresses that correspond to each of
the interrupt sources. When an interrupt occurs, the microcontroller jumps to the
corresponding interrupt vector to handle the interrupt.
2.Interrupt Request (IRQ) Pin: The microcontroller has several interrupt request (IRQ) pins
that can be used to generate interrupt requests from external devices.
3.Interrupt Mask Register (IMR): This register allows the user to enable or disable specific
interrupt sources.
 Interrupt Structure(CHAT GPT)

4.Interrupt Flag Register (IFR): This register holds the interrupt flags,
which indicate the status of the interrupt sources.
5.Interrupt Service Routine (ISR): This is a function that handles the
interrupt request. The ISR is executed when an interrupt occurs, and it
performs the necessary operations to process the interrupt.
To use the interrupt system of the ATMega16, the user must configure
the interrupt sources by setting the appropriate bits in the IMR and IFR
registers. The user must also define the ISR functions that correspond
to each interrupt source. When an interrupt occurs, the microcontroller
jumps to the corresponding ISR to handle the interrupt. After the ISR is
executed, the microcontroller returns to the main program.
Architecture(Chat GPT)
• The architecture of an AVR microcontroller is based on the Harvard architecture, which separates the data
memory and the program memory. The AVR architecture consists of the following components:
1. Central Processing Unit (CPU): The CPU is responsible for executing instructions, performing arithmetic and
logic operations, and managing the flow of the program.
2. Program Memory: The program memory stores the executable instructions that the CPU executes. It is usually
flash memory, which can be reprogrammed multiple times.
3. Data Memory: The data memory stores the variables and data used by the program. It includes both static and
dynamic RAM.
4. Input/Output (I/O) Ports: The AVR microcontroller has a number of I/O ports that can be used to interface with
external devices, such as sensors and actuators.
5. Timers/Counters: The AVR microcontroller has several timers and counters that can be used for timing and
counting purposes.
6. Analog-to-Digital Converter (ADC): The ADC converts analog signals to digital signals, which can be processed
by the CPU.
7. Serial Communication Interfaces: The AVR microcontroller has several serial communication interfaces, such as
USART, SPI, and I2C, that can be used for communication with other devices.
8. Interrupt Controller: The interrupt controller handles interrupt requests from external devices and peripherals,
allowing the CPU to respond to events in a timely manner.
9. Clock Generator: The clock generator generates the clock signal used by the microcontroller to synchronize its
operations.
• Overall, the architecture of an AVR microcontroller is designed to be simple, flexible, and efficient, making it a
popular choice for a wide range of applications.
PIN DESCRIPTION OF ATMEGA16
The ATMega16 is a popular AVR microcontroller that has the following pin description:
1.Power Pins: The ATMega16 has two power pins: VCC (positive power supply, typically 5V) and
GND (ground).
2.I/O Pins: The ATMega16 has up to 31 I/O pins that can be used as inputs or outputs. These
pins are labeled as PORT A, PORT B, PORT C, and PORT D.
3.Reset Pin: The reset pin (labeled RESET) is used to reset the microcontroller and is typically
connected to a push-button switch.
4.Oscillator Pins: The ATMega16 has two oscillator pins (XTAL1 and XTAL2) that are used to
connect an external crystal oscillator. This oscillator is used to generate the clock signal that
drives the microcontroller.
PIN DESCRIPTION OF ATMEGA16
5.Analog Input Pins: The ATMega16 has up to 6 analog input pins (labeled ADC0
to ADC5) that can be used with the built-in analog-to-digital converter (ADC).
6.Serial Communication Pins: The ATMega16 has several serial communication
pins that can be used for communication with other devices, including USART
(Universal Synchronous/Asynchronous Receiver/Transmitter), SPI (Serial
Peripheral Interface), and I2C (Inter-Integrated Circuit).
7.Interrupt Pins: The ATMega16 has several interrupt pins that can be used to
handle interrupt requests from external devices and peripherals.
8.Other Pins: The ATMega16 has several other pins, including a programming pin
(labeled MISO), a clock pin (labeled SCK), and a data pin (labeled MOSI), which
are used for programming the microcontroller using an in-system programmer.