Lecture 18.

Sequential Circuits
ECE 407/507

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Sequential Circuits
 Midterm 2
 April
20. Tue, in Class Midterm
 Cover after Midterm 1 to Chapter 7
 Openbook, notes, homeworks

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Sequential Circuits
 Sequential Logic
Inputs Outputs
COMBINATIONAL
LOGIC

Current State
Next state
Registers
Q D

CLK

2 storage mechanisms
• positive feedback
• charge-based

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Sequential Circuits
 Positive Feedback: Bi-Stability
V i1 V o1 =V i2 V o2

Vo1 Vi2
V o2 =V i1

V i1 V o2

A
V i2 =V o1

B
V i1 =Vo2

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Sequential Circuits
 Meta-Stability
A A
V i2 5 V o1

V i2 5 V o1
|| ||

C C

B B
V i1 5
= V
o2 V i1 5= V o2
d d
Gain should be larger than 1 in the transition region

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Sequential Circuits
 Writing into a Static Latch
Use the clock as a decoupling signal,
that distinguishes between the transparent and opaque states
CLK
CLK

Q D D
CLK
CLK
D

CLK
Forcing the state
Converting into a MUX (can implement as NMOS-only)

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Sequential Circuits
 Mux-Based Latches
Negative latch Positive latch
(transparent when CLK= 0)
(transparent when CLK= 1)

Q 0 Q
1

D 0 D 1

CLK CLK

Q Clk Q  Clk In Q Clk Q  Clk In

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Sequential Circuits
 Latches
Positive Latch Negative Latch

In D Q Out In D Q Out
G G

CLK CLK

clk clk

In In

Out Out

Out Out Out Out

stable follows In stable follows In

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Sequential Circuits
 Mux-Based Latch
CLK

CLK

CLK

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Sequential Circuits
 Mux-Based Latch

CLK
QM
CLK

QM

CLK

CLK

NMOS only Non-overlapping clocks

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Sequential Circuits
 Storage Mechanisms

Static Dynamic (charge-based)

CLK
CLK

D Q
Q

CLK
CLK
D

CLK

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Sequential Circuits
 Making a Dynamic Latch Pseudo-Static

CLK

D D

CLK

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Sequential Circuits
 Cross-Coupled Pairs
NOR-based set-reset

S R Q Q
S
Q
S Q 0 0 Q Q
1 0 1 0
R Q
0 1 0 1
Q
R 1 1 0 0

Forbidden State

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Sequential Circuits
 Cross-Coupled NAND
Added clock
Cross-coupled NANDs VDD

S M2 M4
Q
Q
Q

Q CLK M6 M8 CLK
R M1 M3

S M5 M7 R

This is not used in datapaths any more,

but is a basic building memory cell

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Sequential Circuits
 Naming Conventions
 In our text:
 a latch is level sensitive
 a register is edge-triggered
 There are many different naming
conventions
 For instance, many books call edge-
triggered elements flip-flops
 This leads to confusion however

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Sequential Circuits
 Latch versus Register
 Latch  Register
stores data when stores data when
clock is low clock rises

D Q D Q

Clk Clk

Clk Clk

D D

Q Q

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Sequential Circuits
 Latch-Based Design
• N latch is transparent • P latch is transparent
when  = 0 when  = 1


N P
Logic
Latch Latch

Logic

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Sequential Circuits
 Master-Slave (Edge-Triggered)
Register
Slave
Master

0 Q D
1 QM
1
QM
D 0 Q

CLK
CLK

Two opposite latches trigger on edge

Also called master-slave latch pair

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Sequential Circuits
 Master-Slave Register

Multiplexer-based latch pair

I2 T2 I3 I5 T4 I6 Q

QM
D I1 T1 I4 T3

CLK

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Sequential Circuits
 Timing Definitions

CLK
t Register
tsu thold D Q

D DATA CLK
STABLE t
tc 2 q

Q DATA
STABLE t

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Sequential Circuits
 Characterizing Timing

tD 2 Q

D Q D Q

Clk Clk

tC 2 Q tC 2 Q

Register Latch

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Sequential Circuits
 Clk-Q Delay

2.5
CLK

1.5
Volts

D
tc 2 q(lh) tc 2 q(hl)
Q
0.5

2 0.5
0 0.5 1 1.5 2 2.5
time, nsec

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Sequential Circuits
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Sequential Circuits
 Setup Time
3.0 3.0
Q
2.5 2.5

2.0 QM 2.0 I 2 2 T2

1.5 1.5 Q
Volts

Volts
CLK CLK
D D
1.0 1.0
I 2 2 T2 QM
0.5 0.5

0.0 0.0

2 0.5 2 0.5
0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1
time (nsec) time (nsec)
(a) Tsetup5 0.21 nsec (b) Tsetup5 0.20 nsec

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Sequential Circuits
 Setup/Hold Time Illustrations
Circuit before clock arrival (Setup-1
case)
CN

TG1
Inv2 Clk-Q Delay
D1 SM QM
D

Inv1

CP
TClk-Q

TSetup-1 Time

Data Clock
TSetup-1

Time
t=0

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Sequential Circuits
 Setup/Hold Time Illustrations
Circuit before clock arrival (Setup-1
CN
case)
TG1
Inv2 Clk-Q Delay
D1 SM QM
D

Inv1

CP
TClk-Q

TSetup-1 Time

Data Clock
TSetup-1

Time
t=0

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Sequential Circuits
 Setup/Hold Time Illustrations
Circuit before clock arrival (Setup-1
case)
CN

TG1
Inv2 Clk-Q Delay
D1 SM QM
D

Inv1
TClk-Q

CP

TSetup-1 Time

Data Clock
TSetup-1

Time
t=0

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Sequential Circuits
 Setup/Hold Time Illustrations
Circuit before clock arrival (Setup-1
case)
CN

TG1
Inv2 Clk-Q Delay
D1 SM QM TClk-Q
D

Inv1

CP

TSetup-1 Time

Data Clock
TSetup-1

Time
t=0

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Sequential Circuits
 Setup/Hold Time Illustrations
Hold-1 case
CN

TG1 Clk-Q Delay

Inv2
D1 SM QM
D

Inv1

0
CP
TClk-Q

THold-1
Time

Clock Data
THold-1

Time
t=0

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Sequential Circuits
 Setup/Hold Time Illustrations
Hold-1 case
CN

TG1 Clk-Q Delay

Inv2
D1 SM QM
D

Inv1

0
CP
TClk-Q

THold-1
Time

Clock Data
THold-1

Time
t=0

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Sequential Circuits
 Setup/Hold Time Illustrations
Hold-1 case
CN

TG1 Clk-Q Delay

Inv2
D1 SM QM
D

Inv1

0
CP TClk-Q

THold-1
Time

Clock Data
THold-1

Time
t=0

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Sequential Circuits
 Setup/Hold Time Illustrations
Hold-1 case
CN

TG1 Clk-Q Delay

Inv2
D1 SM QM
D

Inv1 TClk-Q

0
CP

THold-1
Time

Clock Data
THold-1
Time
t=0

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Sequential Circuits
 Setup/Hold Time Illustrations
Hold-1 case
CN

TG1 Clk-Q Delay

Inv2 TClk-Q
D1 SM QM
D

Inv1

0
CP

THold-1
Time

Clock Data
THold-1 
Time
t=0

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Sequential Circuits