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Slidesaver - App Tcebhm

The document discusses the Serial Peripheral Interface (SPI) protocol, highlighting its need for reduced wiring in embedded systems and its operation in master/slave mode with multiple slave devices. It details the pin descriptions, data transmission process, clock configuration, and the control registers associated with SPI. Additionally, it outlines the lack of acknowledgment mechanisms and addressing schemes in SPI communication.

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0% found this document useful (0 votes)
30 views86 pages

Slidesaver - App Tcebhm

The document discusses the Serial Peripheral Interface (SPI) protocol, highlighting its need for reduced wiring in embedded systems and its operation in master/slave mode with multiple slave devices. It details the pin descriptions, data transmission process, clock configuration, and the control registers associated with SPI. Additionally, it outlines the lack of acknowledgment mechanisms and addressing schemes in SPI communication.

Uploaded by

sauravpant0987
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Serial Peripheral Interface

Need of Serial 8us Protocol


• Peripheral devices in embedded systems =>
ai'ailel address and data bus => lots of wiring and
requires number’ of pins =+ additlOiial decoding
logic required.

• To rd ccit i d a d w s - > cost -> Serial


bus
protocol => SPl (4-wire) & l2C (2-wire).

• Penalty => Slower coiniiiuiiicalion.


Various Serial Bus Protocol
• UART
• SPI E bedd d S st i Proto
ol
• l2C- Embedded S stem
Protocol
• CAN
• USB
• SATA ctc..
• The Sei ial Pei'iphera1 Interface Bus or SPl bus is
a sYnchioiious sei•ial data link standard named
by Motorola that operates in tull d i x node.

• Devices communicate in irastci’/slave mode


where the master device initiates the data frarrle.
Multiple slave devices are allowed with
individual slave select (chip select) lines.
•During a data transfer the master always sends S
to 16 bits of data to the slave, and the slave
always sends a byte of data to the master.

• Maximum data bit rate is one eiuhtli of the input


clock i ate.
• One Central device (Master), initiates
coiiiinunication with all slaves.

• No address decoding logic reqtiiied.

• SPI Master wishes to send the data to slave or


request iiifoi’inatioB from the slave, it activates thc
clock signal.

• Master generates information on one line


(MOSI) while islal s (i'ead) from anothcr linc
(MISO).
Pin Description

• SCL Serial Clock (output from


K master)
• MOS Master Output, Slave Input (output
Imaster) frOm

• MISO Master Input, Slave Output (output


slave) from

• SSSlave Select (active low; output from master)


SCK

SPI, SSP0 MOS


I
INTERFACE MISO
SSEL
Pin :SCK (Serial
Name Clock)
Type
• The SPI used clock signal to s ch zc
o the
transfer of data across the SPl interface.
• The SCK is always driven by the master and
received by thc slave, The clock is UP ab1
to be active high or’ active low.

•The SCK is only active during a data transfer. Any


other’ time, it is either in its inactive state, or tri-
stated.
Pin Name : MiSO
(Master in Slave out)
Type : Input / Output

• The MISO signal is a unidirectional signal


used to tiansfer serial data front the slave to the
lTlaster.
• When a device is a slave, set ialdata is
output on this signal.
• When a device is a master, serial data is
input on
this signal.
• When a slave device is not selected, the
slave drives the signal hi h in
Pin Name : MO Sl
(Master out Slave in)
Type : Input / Output

• The MOSI signal is a unidii•ectional signal used


to transfer serial data morn the Master to the
Slave.

•When n device is a Master, serial data is otxt


on this signal.

• When a device is a Slavc, serial data is i ut


on this
signal.
Pin Name : SSEL (Slave
Select)
Type : Inst
• The SPI slave select signal is an active low signal
that indicates which slave is currently selected to
pauicipatc in a data transfci’.

• EaCli slave has its own unique slave select


signal input.

•The SSEL Nrust be low before data transactions


begin and normally tsta s how foi e t oeo t c
transaction.

• If the SSEL signal goes h i l l any time during a


data transfer, the transfer’ is considered to be aborted.
• In this event, the slave retriiais to idle, and tiny data that
was received is thrt»x ii away. There are no other
indications ot this exception.

•Th is signal is innoct dircctl d b the i astcr. lt


could be driven by a siiiiplc eciici‘a1 orirPosc l/O adder
soiin'arc cOl;lro!.

•On the L PC230O the SSEL pin c«» be used for a


dilTei’ent
iunctioB when the SP i e ace is i u ed Ma t iode

• For exaiiiple, pin hOstiiip the SSEL hiiictioo can be


configui'cd as an output digital GPlO oin and it is also
uscd to select one of the SPI slaves.
Operation

• The SPI bbls can Operate with a single


master device and with one or more slave
devices.

• SPl bus: single inastei and single slave


sct
uos
xPCS sPl
i Ma•
O e
• IN a single slave device is used, the SSEL pin
iii‹i'
be fixed to logic low if the slave pei'iuits it.

• Some slaves require the I Ili cd e (high-flow


ti ansition) oft1 c xJavc scTcct to initiate an action
such as the MAX 1242 by Maxiisi, an ADC, that
starts conversion on said transition.
Configuration

• oTzs multiple slave configuratiOfl:

• Typical SPl bus: Master and independent Slaves

• CDmaids SPI bus: Master and cooperative


slaves
Typical SPI Bus
•With multiple slave devices, an
independent SSEL signal is required Tom
the master for each slave device (3).
• ln the independent slave configuration, there is an
indeoendent slave select line for each slave. This is the
way SPI is normally used.

• Since the MISO pins of the slaves ai•e connected


togetliei, they are required to be tri-state tins.
Daisy-Chained SPI Bus

Daisy-chained SPI bus: Master and Cooperative


Slaves
" OlJiC QfOdiicts with SPI bus are designed to be capable
of
being connected in a d is c aii configuration, the fiist
slave output being connected to the second slave input, etc.

• The SPI port of each slave is designed to send out


during the second gi’Oup of clock pulses an exact copy of
what it ieceived during the first group of clock pulses.

•Such a feature only requii'es a si i lc SSEL line from the


master, rnthei’ than a c arat SEL l c for each slave.
Points

• Not have ack mechanism to confirm receipt of data


and does not have flow control.

• SPI Master, not have knowledge of whether


slave exist or Not

Not particular addressing scheme.

• Not defined any maximum data rate.


Data Transmission
• A typical hardware setup using two shift registers to
form an inter-chip circular buffcr

Master Slave
• TO begin a coiniiiiinication, the lHastei’
first configures the Clock, using a frequency less
than or equal to the maximum frequency the
slave device supports.

•Stich frequencies are commonly in the range


of
I-70 MHz.

•Thc mastertheirpulls the slave select SSEL


low
for the desii'ed chip.

•During each SPI clock cycle, a ftill duplex


•The master sends a bit on the MOSI line; the
slave reads it fi•oin that sameline

• The slave sends a bit on the MISO line;


the waster reads it ti•oin that same line

•Traiisinissions normally involve two sliifi registers


of some given word size, such as eight bits, one in
the master and one iii the slave; they are connected
•After that register has been shifted out, the
and slave have xch ed
master
values.
•Theo each device takes that value and
does
something with it, such as writing it to memorr.

• If there are iuoi'c data tO exchange, the shift


registers are loaded with new data and the pi
ocess repeats.
Clock Polarity and
Phase
•ln addition to setting the clock fiequency,
the irastei intist also configure the clock polarity
and phase with respect to the data.

• SPl Block Guide names these two options as C


POL and CPHA respectively, and most vendors
have adopted that convention.
CPOL-
SC 0
KS CPOL=
1
S Cycle
CPHA= #
0 MIS
O
MOSa
Gycle
CPHA= I
MISO
1 MOSI

A timing diagraln showing cloCk polarity and


At CPOL 0, the base value of the clock is
zero

• For CPHA=0, data are read on the clock's


risings edge (low->high transition) and data
are changed on a falling educ (high->low
clock transition).

• For CPHA= 1, data are read on the clock's


fallin ed e and data are chan 'ed on a
risen
At CPOL- l, the base value of the clock is
one (inversion of CPOL=0)

•For CPHA=0, data are read on clock's


falling edge and data are chased on a ii
tede.

•For C PHA 1, data are read on clock's


i s i b dyeand data are chased on ed e.
CPOL & First data driven Other data Data
CPHA driven Sampled
0&0 Prior tO fifst SCK falling SCK rising
SCK rising edge edge edge
0 & l First SCK rising SCK rising SCK falling
edge edge edge
1&0 Prior to first SCK rising SCK falling
SCK falling edge edge
edge
1&I First SCK SCK falling SCK rising
falling edge edge edge
Microchip SPI EEPROM
(Slave)
ROtJRE 8ERW.llJPtJTTIglftG
2:
• 8-bit data transfei•,device is master/slaveand setting
of CPHA variable.

•Device, Master => Stan of ti'ansfer, master having a


data ie.idy to transfer. Activate the clock and begin
the transfer.

•Dcvice, Slave and CPHA=0, traiisfei’ stai't when


SSEL=0.

•Device, Slave and CPHA= 1, transfer


starts on first clock cdgc when slavc is
sclcctcd.
Mode Numbers
•The combinations of polarity and phases are
ofien refciTed tO as modes

Mode CPOL CPHA


0 0 0
i 0 1
2 1 0
3 1 i
Register Descri
tion
• SPI has seven c see s, from that
programmers
intcrfacc for SPI peripheral has miv i s t .

• The bits in the rest of twO TEST registers


are
intended for functional verification Only.
Name Description Access
SOSPCR SPI Control Register.
This register controls the R/W
operation of the SPI.

SOSPS SPl t a Rne ser.


R This register shows R
the status of the SPI. O
Name Description Access

SOSPD P Data Re t
R 1. This bi-
directional register ›r
provides the w
transmit and
receive data for the
SPI.
Name Description Access
SOSPCCR SPI Clock Counter Register.
This register controls the MW
frequency of a master’s SCK

SOSPIN SPI Interru t Fla


T This register contains R/
the interrupt flag for the W
SPI interface.
Control Register
(SOSPCR - 0xE002 0000)
Bit Syinbol Value Description

1:0 Reserved, user software


should not write ones
to
i'eserved bits.
SPI Control
Register- 0xE002 0000)
(SOSPCR
Bit Symbol Value Description

2 BitEnable The SPI controller sends


0 and receives 8 bits of
data pei• transfer.
l The SPI controller sends
and
receives the number of
bits
Control
Register
(SOSPCR - 0xE002 0000)
Bit Syinbol Value Description

3 Clock pliase control


CPHA 0 Data is Salnpled on the
first
clock edge of SCK.
i Data is sampled on the
second clock edge of
the
Control Register
(SOSPCR - 0xE002 0000)
Bit Symbol Value Description
4 CPOL Clock polarity control.
0 SCK is active high.
1 SCK is active low.
5 MSTR Master node select.
0 The SPI operates in Slave
mode.
l The SPl operates in
Master
SPI Control Register
(SOSPCR - 0xE002 0000)
Bit Symbol Value Description
6 LSBF LSB First, controls in
which
direction each byte is
shifted when transferred.
0 SPI data is transferred
MSB
(bit 7) first.
1 SPI data is transferred LSB
Control Register
(SOSPCR - 0xE002 0000)
Bit Symbol Value Description
7 SPIE Serial peripheral interrupt
enable.
0 SPI interrupts are
inhibited.
1 A hardware interrupt is
generated each time the
SPIF or MODF bits are
activated.
SPI Control Register
(SOSPCR - 0xE002 0000)
Bit Syinbol Value Description
11:8 BITS When bit 2 of this register is
1, this field controls the
number of bits per ti'ansfer:
1000 8 bits e t a sfe
1001 9 bits per transfer
1010 10 bits per Transfer
1011 11 bits per transfer
Control Register
(SOSPCR - 0xE002 0000)
Bit Syinbol Value Description

1100 12 bits per transfer


1101 13 bits per transfer
1110 14 bits per
transfer
1111 15 bits per
transfer
0000 16 bits er Transfer
Control
Register
(SOSPCR - 0xE002 0000)
Bit Syinbol Value Description

15:12 Reserved, user


software should not
write ones to reserved
bits.
Data Register
(SOSPDR - 0xE002 0008)
• This bi-directional data register provides
the transmit and receive data for the SPI.

• Transmit data is provided to the SPI by


wi‘itinJ
to this registcr.

• Data received by the SPI can be read from


this register.
Data Regicters

Naster Slave

NlS
0
• There is no buffer between the data register
and
the internal shift register. A write to the data
register goes directly into the internal shift
register.

• Therefore, data should only be written to


this register when a transmit is not currentl
ro ress
• Read data is buffered.

• When a transfer is co plete, the receive data


is transferred to a sin le b te data buffer,
where it is later read.

• A read of the SPI data register returns the


value
of the read data buffer.
SPI Data Register
(SOSPDR - 0xE002
Bit Symbol
0008) Description
7:0 SPI bi-directional data port
DataLow 15:S If bit 2 of the SPCR is 1 and
DataHigh bits 11:8 are other than 1000,
some or all of these bits contain
the additional transmit and
receive bits. When less than 16
bits are selcctcd, the most
Significant among these bits
Status Register
(SOSPSR 0xF002
Bit Symbol Description
7 SPIF SPI transfer com lete fla

When 1, this bit indicates when


a SPI data transfer is co lete.

When a master, thls bit is set at


the end of the last cvclc of the
transfei•.
Stams
(SOSPSR 0xE002
Register
Bit Symbol Description
7 SPIF SPl transfer com

When a slave, this bit is set on the


last data sanipling edge of the
SCK.

THIS bit is cleared by first readin,.,


this register tiren accessing t14O
SPI Stams Register
(SOSPSR - 0xF002 0004)
Bit Symbol
Description
6 Write Collision. When 1, this bit
WCOL indicates that a write collision has
occurred. This bit is cleared by
reading this register then
accessing the SPI data register.
Exception conditions Write Collision

• As stated previously, there is no


wi•itc buffer between the SPI block bus
interface, alid the intenial shift
registei•.

• As a result, data must not be written


to the SPI data register when a SPI
data transfer is curi•cntl root css.
• The time frame where data cannot be written to
the SPI data register is from when the transfei
stars, until after the states reeister has been read
when the
SPI F status is activc.

•If the SPI data register is written in this time


frame, the writc data will bc lost, and thc write
collision (WCOL) bit in the isntct is i tcr will be
activated.
Stams Register
(SOSPSR - 0xF002 0004)
Bit Symbol Description

5 ROVR Read overrun. When 1, this bit


indicates that a read overrun
has
occurred. This bit is cleared by
reading this register.
Exception conditions Read Ovemn
• A read ovei'ruii occui's when the SPI block intei’Bal
read buffer contains data that has not been read by
the rOcessor, and a new transfer meted.

• The iead buffer containing valid data is indicated


by the SPlF bit in the status registei• being active.
Exception conditions Read
Overrun
•When a transfer completes, the SPI block needs
to
move the received data to the read buffer.

•lf the SPlF bit is active (the read buffer is


full), the new receive data will be lost, and the
i ead overrun (ROVR) bit in the status register
will be activated.
Stams
Register
(SOSPSR - 0xF002
0004)
Bit Symbol Description
4 Mode fault. when 1, this bit
MODF indicates that a Mode fault
error has occurred. This bit is
cleared by reading this register,
then writing the SPI Control
register.
Exception conditions Mode Fault
•11 the SSEL Si*nal Eoes active, when the
SPI block is a inastci‘, this indicates another inastei’
has selected the same device to be a slave.
This condition is known as a node fault.

• When a mode fault is detected, the node fault


(MODF) bit in the status register will be activated.
SPI Status Register
(SOSPSR - 0xF002 0004)
Bit Symbol Description
3 ABRT Slave abon. When 1, this bit
indicates that a slave abort has
occurred. This bit is cleared by
reading this register.
2•0 - Reserved, user software should
not
write ones to reserved bits.
Exception conditions Slave Abort
• A slave transfer is considered to be aboi
ed, lf the SSEL signal goes inactive before
the transfer is complete.

• In the event of a slave abort, the transmit


and receive data for the transfer that was
in progress are lost, and the slave
abort(ABRT) bit in the status register
will be activated.
SPI Intempt Register
(SOSPINT - 0xE002 001C)
• This register contains the interrupt flag for
the SPI interface.

Bit Symbol Description


0 SPI SPl interrupt flag. Set by the
SP1
Interrupt interface to generate an
interrupt.
Flag Cleared bv writing a 1 to this
7: l - bit.
SPI Clock Counter Register
(SOSPCCR - 0xE002 OOOC)
• This register controls the frequency of
a master’s SCK.
• The register indicatesthe number of
PCLK cycles that make up an SPI clock.
• The value of this register must always be
an even number. As a result, bit 0 must
always be 0.
Configuration

• SPI can be configured as MASTER or


SLAVE.
Configuration Master operation

• The following sequcnce describes


how one should process a data transfer
with the SPI block when ii is set up to
be the master.

• This process assumes that any


r or data ti•ansfer has alread
leted.
Configuration - Master
operation
1. Set the SPI Clock counter register
to the desired clock rate.

2. Set the SPI Contro e 1s er to


the
desired settings.
3. Write the data that transmitted to
the aSrPe I da e . This write starts
the SPI data transfer.
Configuration Master
operation
4. Wait for the SPIF bit in the SPI
status le ister to be set to 1.
The SPIF bit will be set after
the clasyt c l e of the SPI data
transfer.

5. Read the SPI status re ister.


Configuration Master
operation
6. Read the received data from the
SPI
rdoaeta ste (optional).

7. Go to ste 3 if more data is


required to transmit.
Configuration Master
operation NOTE:
• A read or wi ite of the SPI data re
lstcr is required in
order to clear the SPIF
status bit.
• Therefore, if the optional iead of
the SPI data register does not take
place, a write to this register is
required in
Configuration Slave operation

• The following sequence describes


how one should process a data transfer
with the SPI block when it is set up to
be the slave.

• This process assumes that any


o data transfer has alieady
completed.
Configuration Slave
operation
1. Set the SPI control re istei to
the desired settings.

2.Write the data to transmitted to the


SPI roeta ster (optional). Note that
this can only be done when a slave SPl
transfer is not in progress.
Configuration Slave
operation
3. Wait for the SPIF bit in the SPI
status ir en t e r to be set to 1. The
SPIF bit will be set after the last sa
lln clock edee of the SPI data
ti•ansfer.

4. Read the SPI states register.


Configuration Slave
operation
5. Read the received data from the SPI
rdoaeta ster (optional).

6. Go tO sfeo 2 lf luOre data is


required to ti•ansmit.
Configuration Slave
operation NOTE:
• A read or write of the SPI data
register is required in order to clear
the SPIF
status bit.

• Therefore, at least one of the


optional reads or writes of the SPI
data register must take place, in
SPI- Ma»ter (C-
• Code’)
#lnclude <LPC2300.h> • Void intt () // fun
declared
• Void init (void) . (
• P1NSEL0=0xAA000;
• # define.SPIfi 1
• # define datn 0xC I (SCK I, SSEL1, MOSI I;MISO l)
. ( • VBPDIV x1;// set PCLK
to
• While
• (1}( • SPCR— 0x20;// device
• SPDR= data; // write data selected master
• out
While (!(SPSRñ. SPIF)) ( }
)
Tabte Pln functJon aelem register 0 /91N8EL0 - eddreee 0xE003 C0tt0} titt
W deacHptJon

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OO
8CK0
and Cons
Of
SPI
Advantages
• Full duplex coiuiiiunication

• Higher throughput than IzC

• Complete protocol flexibility for the


bits
transferred
* Not limited to 8-bit words
* Arbitrary choice of
Advantages
Extremely simple hardware interfacing

* Typically lower power requirements than


I2C due to less circuitry
* No arbitration or associated failure
modes
* Slaves use the master's clock, and
don't need precision oscillators
* Transceivers are not needed
Disadvantages
• Requires more pins on IC Cs
packa than
I2C, even in the "3-Wire"
• variant
No hardware flow control

• No hardware slave acknowledgment (the


master cotild be "talking" to nothing and
not know it)
Disadvantages

• Suppoos only one master device

• Only handles short distances


compared to RS-232, RS-455, or
CAN-bus
Applications

SPI is used to talk to a variety


of peripherals, such as:

•Sensors: Temperature, pressure. ADC,


touch-screens
•Control devices: audio codecs,
digital
potentiometers, DAC
Applications

• Memory: flash and EEPROM


• Real-time clocks
• LCD displays, sometimes even
for managing image data
• Any MMC or SD card

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