Session 4

DFT
LEC
Prepared by:
ICpedia PnR Team
Contents
• DFT

• LEC
DFT Introduction
• Designing with taking into
consideration test problem.
• What kind of problems we focus on in
DFT?
• DFT Challenges
DFT Introduction
• Designing with taking into
consideration test problem
• What kind of problems we focus on in
DFT?
• DFT Challenges
DFT Problem
• Designing with taking into
consideration test problem
• What kind of problems we focus on in
DFT?
• DFT Challenges
Ex. Physical Defects
Fault Models
• A logical model representing the effects of a physical defect
 Stuck-at
 At-speed
 Quiescent Current
 Bridge
Ex. STUCK AT
• A signal, or gate output/input, is stuck at a 0 or 1 value,
independent of the inputs to the circuit
 Ex. STUCK AT
A B C D
0 0 0 0 A

0 0 1 0
B
0 1 0 0 D

0 1 1 1
C
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1
 Ex. STUCK AT
A B C D
0 0 0 0 A Expected logic
1
Actual ?
0 0 1 0
B
0 1 0 0 D

0 1 1 1
C
1 0 0 0
1 0 1 0 GND
1 1 0 0
1 1 1 1
 Ex. STUCK AT
A B C D
0 0 0 0 A Expected logic
1
Actual ?
0 0 1 0
B
0 1 0 0 D

0 1 1 1
C
1 0 0 0
1 0 1 0 GND
1 1 0 0
1 1 1 1
Multiplexed Flop Scan

• “compile –scan” command in Design Compiler causes the normal flops to be scan-
replaced during the synthesis process
• Adding scan flop in the design and connecting DFT circuit is called Scan Insertion
Scan Ready Design

• Shift in – Capture – Shift out

Automatic Test Pattern Generation “ATPG”
• Automatic generation of test
patterns for scan ready
design
• Tools for pattern generation:
Synopsys Tetramax
Siemens (Mentor) Tessent
Cadence Modus DFT
• ATPG tool is used for
generating test pattern file
and testbench for simulating
test patterns
• Test patterns are loaded into
automatic test equipment to
classify functioning / faulty
ICs.
Contents
• DFT

• LEC
What is Formal Verification?
• Formal verification is an alternative to verification through simulation.
• As designs become larger and more complex and require more simulation
vectors, regression testing with traditional simulation tools becomes a
bottleneck in the design flow.
• A 100% coverage

• Equivalence checkers prove or disprove that one design

representation is logically equivalent to another. In other words, two
circuits exhibit the same exact behavior under all conditions despite
different representations-.

22
What is Formality?
• The purpose of Formality is to detect unexpected differences that
might have been introduced into a design during development.
• It uses a formal verification comparison engine to prove or disprove
the equivalence of two given designs and presents any differences
for follow-on detailed analysis.
Design level 1 Design process Design level 2

Formality
Equivalent
Yes/No ?

23
Logic synthesis and Formality: Basic Flow

RTL & SC .
Uncertainties Constrain
header libs
ts

Logic Synthesis (DC/Yosys)

RTL & Prefloorplan SC .

header .svf files netlist (.v) libs

Formal Verification (Formality)

24
Key Concepts
• Main concepts in Formality are
• Compare Point
• Primary output of a circuit
• Registers within a circuit
• Input to black boxes within a circuit
• Logic Cone
• A block of combinational logic which drives a compare point

25
Equivalence Checking Verification Process

• Equivalence checking is a four-phase process:

• Reading and elaborating language descriptions into logical
representations
• Setting Up Designs to Preempt Differences
• Mapping of corresponding compare points between pairs of
designs (Matching)
• Comparison of logic cones that drive the compare points
(Verification)

26
• 0. Guidance (Load Automated Setup File)
•
• Before specifying the reference and implementation designs, an
automated setup file (.svf) can be optionally loaded into Formality. The
automated setup file helps Formality process design changes caused
by other tools used in the design flow. Formality uses this file to assist
the compare point matching and verification process. For each
automated setup file that is loaded, Formality processes the content
and stores the information for use during the name-based compare
point matching period.

27
Formality Flow Overview

Start
Setup

Read Reference
Design + Libs Match
Debug
Read Implementation Verify
Design + Libs

No
Success?

Yes

End

28
Guidance (Loading of Automated Setup File)
• The purpose of automated file (.svf) is to help Formality process
design changes caused by other tools, which it should have access to
as the changes are made.

29
 Exercise
-If a netlist ECO was wrongly implemented, removing one of the following cells by
mistake.. When will it cause formality to fail?
- An inverter.
- A buffer.
- An unconnected net.

30
 Logical DFT LVS
equivalence
(Formality)
Usage Verify different Observability and Checking spice after
Pros
implementatio Controllability to physical synthesis is
ns match each validate fabrication match GDS: devices
other (RTL VS has completed are matching,
netlist, netlist properly according to
VS netlist) "stuck-at" Model.

Limitation Only checking Extra area and Check physical

s
logic didn't power. correctness only not
change after Coverage usually is logical or
design stages. not 100%. functionality, nor
Testing equipment STA.
and testing time.
Required gatelevel Synthesize design post-PnR .gds, post-
inputs
netlist, .lib, Scan PnR .v netlist, SC
RTL/gatelevel strategy/constraints library .spice, macros
netlist, .svf .spice (if you have
macros), 33
LVS .ruleset.