Input/

Output
Module-4

Organizatio
n:
Accessing I/O devices

Processor Memory

Bus

I/O de vice 1 I/O de vice n

•Multiple I/O devices may be connected
to the processor and the memory via a
bus.

•Bus consists of three sets of lines to

carry address, data and control signals.
•Each I/O device is assigned an unique
address.

•To access an I/O device, the processor places

the address on the address lines.

•The device recognizes the address, and

responds to the commands issued on the
control signals.

•The process request either a read or a write

Accessing I/O devices (contd..)
 If I/O devices and the memory share the

same address space, then it is called as

Memory mapped I/O:
Any machine instruction that can access memory
can be used to transfer data to or from an I/O device.

Simpler software.

Any data-transfer instruction (like Move, Load) can

be used to exchange information.

For example, Move DATAIN, R0; This instruction

sends the contents of location DATAIN to register R0.
Here, DATAIN -> address of the input-buffer of the
keyboard 4
Accessing I/O devices (contd..)
 I/Odevices and the memory may have
different address spaces:
Special instructions to transfer data to and from
I/O devices.

I/O devices may have to deal with fewer address

lines.

I/O address lines need not be physically separate

from memory address lines.

In fact, address lines may be shared between I/O

devices and memory, with a control signal to
indicate whether it is a memory address or an I/O
5

address.
Accessing I/O devices
(contd..)

Address lines
Bus Data lines
Control lines

Address Control Data and I/O

decoder circuits status registers inteface

Input device
•I/O device is connected to the bus using an I/O
interface circuit which has:
- Address decoder, control circuit, and
data and status registers.
•Address decoder decodes the address placed on the
address lines thus enabling the device to recognize its
address.

•Data register holds the data being transferred to or

from the processor.

•Status register holds information necessary for the

operation of the I/O device.

•Data and status registers are connected to the data-

lines, and have unique addresses.
 (contd..)
Recall that the rate of transfer to and from
I/O devices is slower than the speed of the
processor.

This creates the need for mechanisms to

 synchronize data transfers between them.
Program-controlled I/O:
 Processor repeatedly monitors a status flag to

achieve the necessary synchronization.

 Processor polls the I/O device.

 Two other mechanisms used for synchronizing data

transfers between the processor and memory:

 Interrupts.

 Direct Memory Access.

Interrupts
Interrupts
In program-controlled I/O, when the processor
continuously monitors the status of the device,
it does not perform any useful tasks.

An alternate approach would be for the I/O

device to alert the processor when it becomes
ready.
It does it by sending a hardware signal
called an interrupt to the processor.
At least one of the bus control lines,
called an interrupt-request line is dedicated
for this purpose.
Processor can perform other useful tasks while
it is waiting for the device to be ready.
Interrupts (contd..)
Program Interrupt
1 Service
1
Routine
2

i + 1

M
Interrupts (contd..)
 Treatment of an interrupt-service routine is
very similar to that of a subroutine.

However, there are significant differences:

A subroutine performs a task that is required by the
calling program.
Interrupt-service routine may not have anything in
common with the program it interrupts.
Interrupt-service routine and the program that it
interrupts may belong to different users.
As a result, before branching to the interrupt-
service routine, not only the PC, but other
information such as condition code flags, and
processor registers used by both the interrupted
program and the interrupt service routine must be
stored.
This will enable the interrupted program to resume
Interrupts (contd..)

 Savingand restoring information can be done

automatically by the processor or explicitly by
program instructions.
Saving and restoring registers involves
memory transfers:
Increases the total execution time.
Increases the delay between the time an
interrupt request is received, and the start of
execution of the interrupt-service routine. This
delay is called interrupt latency.
Interrupts (contd..)

In order to reduce the interrupt latency,

most processors save only the minimal
amount of information:

This minimal amount of information

includes Program Counter and processor
status registers.

Any additional information that must be

saved, must be saved explicitly by the
program instructions at the beginning of the
interrupt service routine.
Interrupts (contd..)
 When a processor receives an
interrupt-request, it must branch to
the interrupt service routine.
It must also inform the device that it has
recognized the interrupt request.

This can be accomplished in two ways:

• Some processors have an explicit
interrupt-acknowledge control signal for
this purpose.
• In other cases, the data transfer that takes
place between the device and the
processor can be used to inform the
Interrupt Hardware:
Interrupt Hardware:
 We pointed out that an I/O device requests an
interrupt by activating a bus line called interrupt-
request.
 Most computers are likely to have several I/O

devices that can request an interrupt.

 A single interrupt-request line may be used to

serve n devices as depicted in Figure.

 All devices are connected to the line via switches to

ground.
 To request an interrupt, a device closes its

associated switch.
Interrupt Hardware:
 Thus, if all interrupt-request signals INTR1 to
INTRn are inactive, that is, if all switches are
open, the voltage on the interrupt-request line
will be equal to Vdd.
 This is the inactive state of the line. When a

device requests an interrupt by closing its

switch, the voltage on the line drops to 0,
causing the interrupt-request signal, INTR,
received by the processor to go to 1.

 INTR = INTR1 + ... + INTRn

Interrupts (contd..)
 Interrupt-requests
interrupt the execution
of a program, and may alter the intended
sequence of events:
Sometimes such alterations may be
undesirable and must not be allowed.

For example, the processor may not want to

be interrupted by the same device while
executing its interrupt-service routine.

Processors generally provide the ability to

enable and disable such interruptions as
desired.
Interrupts (contd..)
One simple way is to provide machine
instructions such as Interrupt-enable
and Interrupt-disable for this purpose.

To avoid interruption by the same device

during the execution of an interrupt service
routine:

First instruction of an interrupt service

routine can be Interrupt-disable.

Last instruction of an interrupt service

routine can be Interrupt-enable.
Interrupts (contd..)
Multiple I/O devices may be connected
to the processor and the memory via a
bus. Some or all of these devices may be
capable of generating interrupt requests.
Each device operates independently, and
hence no definite order can be imposed on
how the devices generate interrupt requests?

 Howdoes the processor know which device has

generated an interrupt .. ?
Interrupts (contd..)

How does the processor know which interrupt

service routine needs to be executed?

When the processor is executing an interrupt

service routine for one device, can other
device interrupt the processor?

If two interrupt-requests are received

simultaneously, then how to break the tie?
Interrupts (contd..)
Consider a simple arrangement where
all devices send their interrupt-requests
over a single control line in the bus.
 When the processor receives an interrupt
request over this control line, how does it know
which device is requesting an interrupt?

 This information is available in the status

register of the device requesting an interrupt:
The status register of each device has an IRQ

bit which it sets to 1 when it requests an

interrupt.
Interrupts (contd..)

 Interruptservice routine can poll the I/O

devices connected to the bus. The first device
with IRQ equal to 1 is the one that is serviced.

 Polling
mechanism is easy, but time consuming
to query the status bits of all the I/O devices
connected to the bus.
Interrupts (contd..)
 Before the processor started executing
the interrupt service routine for a
device, it disabled the interrupts from
the device.
In general, same arrangement is used when
multiple devices can send interrupt requests to
the processor.

During the execution of an interrupt service
routine of device, the processor does not
accept interrupt requests from any other
device.

Since the interrupt service routines are

Interrupts (contd..)

However, for certain devices this delay may

not be acceptable.

Which devices can be allowed to interrupt a

processor when it is executing an interrupt
service routine of another device?
Interrupts (contd..)
 I/O devices are organized in a priority
structure:

An interrupt request from a high-priority device

is accepted while the processor is executing
the interrupt service routine of a low priority
device.
A priority level is assigned to a processor that
can be changed under program control.

Priority level of a processor is the priority of

the program that is currently being
executed.
Interrupts (contd..)

When the processor starts executing the

interrupt service routine of a device, its priority
is raised to that of the device.

If the device sending an interrupt request has

a higher priority than the processor, the
processor accepts the interrupt request.
Interrupts (contd..)
 Processor’s priority is encoded in a few
bits of the processor status register.

• Priority can be changed by instructions

that write into the processor status
register.
• Usually, these are privileged instructions,
or instructions that can be executed only
in the supervisor mode.
• Privileged instructions cannot be executed
in the user mode.
• Prevents a user program from accidentally
or intentionally changing the priority of the
Interrupts (contd..)

If there is an attempt to execute a privileged

instruction in the user mode, it causes a
special type of interrupt called as privilege
exception.
Interrupts (contd..)

IN T R 1 INTR p
Processor

Device 1 Device 2 Device p

INTA1 INTA p

Priority arbitration
Interrupts (contd..)
INTR1 INTRp

Processor
Device 1 Device 2 Devicep

INTA1 INTAp

Priority arbitration

•Each device has a separate interrupt-request

and interrupt-acknowledge line.
•Each interrupt-request line is assigned a
different priority level.
•Interrupt requests received over these lines
are sent to a priority arbitration circuit in the
processor.
•If the interrupt request has a higher priority
level than the priority of the processor, then
 Interrupts (contd..)
Which interrupt request does the
processor accept if it receives interrupt
requests from two or more devices
simultaneously?.
If the I/O devices are organized in a priority

structure, the processor accepts the interrupt

request from a device with higher priority.
 Each device has its own interrupt request and interrupt acknowledge
line.
 A different priority level is assigned to the interrupt request line of
each device.
However, if the devices share an interrupt
request line, then how does the processor
decide which interrupt request to accept?
Daisy chain scheme:
•Devices are connected to form a
daisy chain.
•Devices share the interrupt-
request line, and interrupt-
acknowledge line is connected to
form a daisy chain.
Daisy chain scheme:
Polling the status registers of the I/O
devices is the simplest such mechanism.

In this case, priority is determined by the

order in which the devices are polled.
•When devices raise an interrupt request, the
interrupt-request line is activated.
•The processor in response activates interrupt-
acknowledge.
•Received by device 1, if device 1 does not
need service, it passes the signal to device 2.
•Device that is electrically closest to the
processor has the highest priority.
Interrupts (contd..)
•When I/O devices were organized into a priority
structure, each device had its own interrupt-
request and interrupt-acknowledge line.
•When I/O devices were organized in a daisy chain
fashion, the devices shared an interrupt-request line,
and the interrupt-acknowledge propagated through the
devices.
•A combination of priority structure and daisy chain
scheme can also used.I NTR1

Device Device
INTA1
Processor

INTR p

Device Device
INTAp
Priority arbitration
circuit
Interrupts (contd..)

I N T R 1

Device Device
INTA1
Processor

IN T R p

Device Device
INTA p

Priority arbitration

circuit
Interrupts (contd..)

•Devices are organized into groups.

•Each group is assigned a different
priority level.
•All the devices within a single group
share an interrupt-request line and are
connected to form a daisy chain.
Only those devices that are being used in a
program should be allowed to generate
interrupt requests.

To control which devices are allowed to

generate interrupt requests, the interface
circuit of each I/O device has an interrupt-
Interrupts (contd..)
If the interrupt-enable bit in the
device interface is set to 1, then the
device is allowed to generate an
interrupt-request.
Interrupt-enable bit in the device’s
interface circuit determines whether the
device is allowed to generate an interrupt
request.

Interrupt-enable bit in the processor status

register or the priority structure of the
interrupts determines whether a given
interrupt will be accepted.
Direct Memory
Access
Direct Memory Access (DMA):
A special control unit may be provided
to transfer a block of data directly
between an I/O device and the main
memory, without continuous
intervention
 Control by the
unit which processor.
performs these transfers is a
part of the I/O device’s interface circuit. This
control unit is called as a DMA controller.
 DMA controller performs functions that would be

normally carried out by the processor:

 For each word, it provides the memory address

and all the control signals.

 To transfer a block of data, it increments the

memory addresses and keeps track of the

number of transfers.
DMA controller can transfer a block of
data from an external device to the
processor, without any intervention from
the
 processor.
However, the operation of the DMA controller must be under
the control of a program executed by the processor.
 That is, the processor must initiate the DMA transfer.
 To initiate the DMA transfer, the processor informs the DMA
controller of:
 Starting address,

 Number of words in the block.

 Direction of transfer (I/O device to the memory, or

memory to the I/O device).

 Once the DMA controller completes the DMA transfer,

it informs the processor by raising an interrupt

signal.
DMA controller registers
DMA controller registers that are
accessed by the processor to initiate
transfer operations.
Two registers are used for storing the
memory
 The addresscontains
third register and thestatus
word and
count.
control flags.
 The R/W(bar) bit determines the direction of the
transfer. When this bit is set to 1 by a program
instruction, the controller performs a read
operation, that is, it transfers data from the
memory to the I/O device. Otherwise, it performs a
write operation, transferring data from the I/O
device to the memory.
 When the controller has completed transferring a

block of data and is ready to receive another

command, it sets the Done flag to 1.
 Bit 30 is the Interrupt-enable flag, IE. When this
flag is set to 1, it causes the controller to raise
an interrupt after it has completed transferring
a block of data.
 Finally, the controller sets the IRQ bit to 1 when

it has requested an interrupt.

Direct Memory
Access
Main
Processor
memory

System bus

Disk/DMA DMA Keyboard

controller controller Printer

Disk Disk Network

Interface
Direct Memory
Access
o To start a DMA transfer of a block of data from
the main memory to one of the disks, a
program writes the address and word count
information into the registers of the
corresponding DMA channel of the disk
controller.
o The DMA controller then proceeds to transfer the
block of data without further involvement of the
processor. When the transfer is completed, the DMA
controller raises an interrupt, allowing the OS to take
appropriate action.
Processor and DMA controllers have to use the
bus in an interwoven fashion to access the
memory.
 DMA devices are given higher priority than the processor to
access the bus.
 Among different DMA devices, high priority is given to high-
speed peripherals such as a disk or a graphics display device.
 Processor originates most memory access
cycles on the bus.
DMA controller can be said to “steal” memory

access cycles from the bus. This interweaving

technique is called as “cycle stealing”.
 The DMA controller has an exclusive capability
to initiate transfers on the bus, and hence
exclusive access to the main memory. This is
known as the “block or burst mode”.
 Bus Arbitration
Processor and DMA controllers both
need to initiate data transfers on the
bus and access main memory.
 The device that is allowed to initiate transfers on the
bus at any given time is called the “bus master”.
 When the current bus master relinquishes its status as the

bus master, another device can acquire this status.

 The process by which the next device to become the bus
master is selected and bus mastership is transferred to it
is called bus arbitration.
 Centralized arbitration: A single bus arbiter performs the
arbitration.
 Distributed arbitration: All devices participate in the
selection of the next bus master.
Centralized Bus
Arbitration
B BS Y

BR

Processor

DMA DMA
controller controller
BG1 1 BG2 2
Centralized Bus Arbitration(cont.,)
• Bus arbiter may be the processor or a separate
unit connected to the bus.
• Normally, the processor is the bus master,
unless it grants bus membership to one of the
DMA controllers.
• DMA controller requests the control of the bus by
asserting the Bus Request (BR) line.
• In response, the processor activates the Bus-Grant1
(BG1) line, indicating that the controller may use the
bus when it is free.
• BG1 signal is connected to all DMA controllers in a
daisy chain fashion.
• BBSY signal is 0, it indicates that the bus is busy.

• When BBSY becomes 1, the DMA controller which

asserted BR can acquire control of the bus.
 Centralized arbitration (contd..)

T ime

BR

BG1

BG2

B BS Y

Bus
master
Processor DMA controller 2 Processor
Centralized arbitration (contd..)

DMA controller 2
asserts the BR signal. Time
Processor asserts
BR
the BG1 signal

BG1 BG1 signal propagates

to DMA#2.
BG2

BBSY

Bus
master
Processor DMA controller 2 Processor

Processor relinquishes control

of the bus by setting BBSY to 1.
Distributed Arbitration
All devices waiting to use the bus
share the responsibility of carrying
out the arbitration process.
 Arbitration process does not depend on a central arbiter
and hence distributed arbitration has higher reliability.
reliability
 Each device is assigned a 4-bit ID number.
number
 All the devices are connected using 5 lines,lines 4 arbitration
lines to transmit the ID, ID and one line for the Start-
Arbitration signal.
signal
 To request the bus a device:

 Asserts the Start-Arbitration signal.

 Places its 4-bit ID number on the arbitration lines.

 The pattern that appears on the arbitration lines is the logical-

OR of all the 4-bit device IDs placed on the arbitration lines.

Distributed arbitration
 Distributed arbitration(Contd.,)

 Arbitration process:
 Each device compares the pattern that

appears on the arbitration lines to its own

ID, starting with MSB.
 If it detects a difference, it transmits 0s on

the arbitration lines for that and all lower

bit positions.
 The pattern that appears on the
arbitration lines is the logical-OR of all the
4-bit device IDs placed on the arbitration
lines.
Distributed arbitration (contd..)
•Device A has the ID 5 and wants to request the bus:
- Transmits the pattern 0101 on the arbitration
lines.
•Device B has the ID 6 and wants to request the bus:
- Transmits the pattern 0110 on the arbitration
lines.
•Pattern that appears on the arbitration lines is the
logical OR of the patterns:
Arbitration process:
- Pattern 0111 appears on the arbitration lines.
•Each device compares the pattern that appears on the arbitration lines
to its own
ID, starting with MSB.
•If it detects a difference, it transmits 0s on the arbitration lines for that
and all lower
bit positions.
•Device A compares its ID 5 with a pattern 0101 to pattern 0111.
•It detects a difference at bit position 0, as a result, it transmits a pattern
0100 on the
arbitration lines.
•The pattern that appears on the arbitration lines is the logical-OR of