EEE241 Digital Logic Design (DLD)

Lecture 21 – Combinational Circuits

Dr. Muhammad Rizwan Azam

COMSATS University Islamabad (CUI) Islamabad, Pakistan.
 Lecture Outline

• Combination Circuits
• Encoders
• Multiplexers
• De Multiplexers
 Encoders

• Performs inverse of a Decoder Only one

switch
• Put “Information” into code
should be
• A Binary Encoder has (or fewer) I/p lines and activated at
O/p lines a time
• Example: 4-to-2 Binary Encoder

x1
x3 x2 x1 y1 y0
y1 0 0 0 0 0
x2 Binary
0 0 1 0 1
Encoder
y0 0 1 0 1 0
x3 1 0 0 1 1
 Encoders

• Octal-to-Binary Encoder (8-to-3) I7

I7 I6 I5 I4 I3 I2 I1 I0 Y2 Y1 Y0 I6
0 0 0 0 0 0 0 1 0 0 0

Encoder
I5 Y2

Binary
0 0 0 0 0 0 1 0 0 0 1
I4 Y1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1 I3 Y0
0 0 0 1 0 0 0 0 1 0 0 I2
0 0 1 0 0 0 0 0 1 0 1 I1
0 1 0 0 0 0 0 0 1 1 0 I0
1 0 0 0 0 0 0 0 1 1 1 I7
I6 Y2
I5
Y2 I 7  I 6  I 5  I 4 I4
I3 Y1
Y1 I 7  I 6  I 3  I 2 I2
I1
Y0 I 7  I 5  I 3  I1 I0 Y0
 Encoders
I7 I6 I5 I4 I3 I2 I1 I0 Y2 Y1 Y0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0 Y2 I 7  I 6  I 5  I 4
0 0 0 0 1 0 0 0 0 1 1
Y1 I 7  I 6  I 3  I 2
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1 Y0 I 7  I 5  I 3  I1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1

• Issue 1: If both and , O/p = 111, but Neither binary of 3 nor 6

• Issue 2: Same O/p on Two Different I/ps
• I/p = 00000000 O/p = 0 0 0
• I/p = 10000000 O/p = 0 0 0
 Priority Encoders

• 4-Input Priority Encoder

I3 I 2 I 1 I 0 Y1 Y0 V
I3 V
0 0 0 0 x x 0

Encoder
Priority
I2 Y1
0 0 0 1 0 0 1
I1 Y0
0 0 1 x 0 1 1
I0
0 1 x x 1 0 1
1 x x x 1 1 1 I3 Y0
I2
Y1 I 3  I 2 I1
Y1
Y0 I 3  I 2 I1
V  I 3  I 2  I1  I 0 I0 V
Priority Encoders
 Encoder / Decoder Pairs
Binary Binary
Encoder Decoder

I7 Y7
I6 Y6
I5 Y5
Y2 I2
I4 Y4
Y1 I1
I3 Y3
Y0 I0
I2 Y2
I1 Y1
I0 Y0
 Multiplexers

• A comb. circuit that selects binary information from one of

many I/p lines and directs it to a single O/p line
 Multiplexers

• Normally, there are I/p lines and selection lines

• 2-to-1 MUX
I0
I0 Y
MUX Y
I1 I1
S
S
 Multiplexers

• 4-to-1 MUX
S1 S0 Y
0 0 I0 I0
0 1 I1 I1
1 0 I2 Y
I2
1 1 I3
I3

I0
I1
MUX Y
I2 S1 S0

I3 S1 S0
 Multiplexers

• Multiple-bit selection logic - Quadruple 2-to-1 MUX

A3 I0
B3 MUX Y A3
I1 S Y3
A2
Y2
A1
A2 I0
MUX Y Y1
B2 I1 S
A0
Y0
B3
I0 A3
MUX Y B2
I1 S A2
A1 B1 A1 Y3
B1 B0 A0 Y
I0 MUX 2
MUX Y B3 Y1
I1 S Y0
B2
S E B1
S B0 S E
A0
 Multiplexers
A3
• Quad 2-to-1 MUX
A3 A2
Y3
A2 A1 Y3
Y2
A0
MUX Y2
A1
Y1
A0 B3 Y1
Y0
B3 B2 Y0
B2 B1
B1 B0 S E
B0

S E
 Implementation Using
Multiplexers
I0
• A Boolean function of n variables can be
I1
implemented with a multiplexer with n Y
I2
selection inputs.
I3
• Example
F(x, y) = ∑(0, 1, 3)
S1 S0

x y F
1 I0
0 0 1 1 I1
MUX Y F
0 1 1 0 I2
1 0 0 1 I3 S1 S0
1 1 1
x y
 Implementation Using
Multiplexers
• Example
F(x, y, z) = ∑(1, 2, 6, 7)

x y z F
0 I0
0 0 0 0 1 I1
0 0 1 1 1 I2
0 1 0 1 0 I3 MUX Y F
0 1 1 0 0
I4
1 0 0 0 0
1 I5
1 0 1 0 I6
1
1 1 0 1 I7 S2 S1 S0
1 1 1 1
x y z
 Implementation Using
Multiplexers
• An efficient method
• Example
F(x, y, z) = ∑(1, 2, 6, 7)

x y z F
0 0 0 0 z I0
0 0 1 1 F=z z I1
MUX Y F
0 1 0 1 0 I2
0 1 1 0 F=z 1 I3 S1 S0
1 0 0 0
F=0 x y
1 0 1 0
1 1 0 1
F=1
1 1 1 1
 Implementation Using
Multiplexers
• Example
F(A, B, C, D) = ∑(1, 3, 4, 11, 12, 13, 14, 15)
A B C D F
0 0 0 0 0
F=D
D I0
0 0 0 1 1
0 0 1 0 0 D I1
0 0 1 1 1 F=D D
0 1 0 0 1
I2
F=D 0
0 1 0 1 0 I3 MUX Y F
0 1 1 0 0 0
0 1 1 1 0 F=0 I4
1 0 0 0 0
D
1 0 0 1 0 F=0 1 I5
1 0 1 0 0
F=D 1 I6
1 0 1 1 1
1 1 0 0 1
F=1 I7 S2 S1 S0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1 F=1 A B C
Implementation Using
Multiplexers
 Multiplexer Expansion
• 8-to-1 MUX using Dual 4-to-1 MUX

I0 I0
I1 I1
MUX Y
I2 I2
I3 I3 S1 S0
I0
MUX Y Y
I1
I0 S
I4 I1
I5 MUX Y
I2
I6 I3 S1 S0
I7
1 0 0
S2 S1 S0
 DeMultiplexers

Y3
Y2
I DeMUX
Y1
S1 S0 Y0

Y3

Y2 S1 S0 Y3 Y2 Y1 Y0
I
Y1 0 0 0 0 0 I
Y0
0 1 0 0 I 0
1 0 0 I 0 0
S1 1 1 I 0 0 0
S0
 Multiplexer / DeMultiplexer
Pairs
MUX DeMUX

I7 Y7
I6 Y6
I5 Y5
I4 Y Y4
I
I3 Y3
I2 Y2
I1 Y1
Y0
SI2 0S1 S0 S2 S1 S0

Synchronize
x2 x1 x0 y2 y1 y0
 DeMultiplexers / Decoders

Y3 Y3

Decoder
I1

Binary
Y2 Y2
I DeMUX I0
Y1 Y1
E
S1 S0 Y0 Y0

E I1 I 0 Y3 Y2 Y1 Y0
S1 S0 Y3 Y2 Y1 Y0 0 x x 0 0 0 0
0 0 0 0 0 I 1 0 0 0 0 0 1
0 1 0 0 I 0 1 0 1 0 0 1 0
1 0 0 I 0 0 1 1 0 0 1 0 0
1 1 I 0 0 0 1 1 1 1 0 0 0
 Three-State Gates

• Digital circuits that exhibit three states.

• Two of the states are signals equivalent to logic 1 and logic 0
as in a conventional gate.
• The third state is a high-impedance state in which
1. The logic behaves like an open circuit, which means that the
output appears to be disconnected,
2. The circuit has no logic significance, and
3. The circuit connected to the output of the three-state gate is not
affected by the inputs to the gate.
 Three-State Gates

• Tri-State Buffer
C A Y
0 x Hi-Z
A Y
1 0 0
1 1 1
C
• Tri-State Inverter
A Y

C
 Three-State Gates
C D Y
A
0 0 Hi-Z
Y 0 1 B
C
1 0 A
B 1 1 ?

Not Allowed
D
A
C A if C = 1
Y= B if C = 0

B
Three-State Gates
I3

I2
Y
I1

I0
Y3
Decoder

S1 I1
Binary

Y2
S0 I0
Y1
E E
Y0