Data Link Layer

A.Pratibha Meghana
319126511067
IT-B
Introduction
 Data Link Layer is second layer of OSI Layered Model. This layer is
one of the most complicated layers and has complex functionalities
and liabilities. Data link layer hides the details of underlying
hardware and represents itself to upper layer as the medium to
communicate.
 Data link layer is responsible for converting data stream to signals bit
by bit and to send that over the underlying hardware. At the
receiving end, Data link layer picks up data from hardware which are
in the form of electrical signals, assembles them in a recognizable
frame format, and hands over to upper layer.
 Data link layer has two sub-layers:
Logical Link Control: It deals with protocols, flow-control, and
error control
Media Access Control: It deals with actual control of media
Functionality of Data-link Layer

Data link layer does many tasks on behalf of upper layer. These are:
 Framing
Data-link layer takes packets from Network Layer and encapsulates
them into frames. Then, it sends each frame bit-by-bit on the hardware.
At receiver’ end, data link layer picks up signals from hardware and
assembles them into frames.
 Addressing
Data-link layer provides layer-2 hardware addressing mechanism.
Hardware address is assumed to be unique on the link. It is encoded into
hardware at the time of manufacturing.
 Synchronization
When data frames are sent on the link, both machines must be
synchronized in order to transfer to take place.
 Error Control
Sometimes signals may have encountered problem in transition and the
bits are errors are detected and attempted to recover actual data bits.
It also provides error reporting mechanism to the sender.
 Flow Control
Stations on same link may have different speed or capacity. Data-link
layer ensures flow control that enables both machine to exchange data
on same speed.
 Multi-Access
When host on the shared link tries to transfer the data, it has a high
probability of collision. Data-link layer provides mechanism such as
CSMA/CD to equip capability of accessing a shared media among
multiple Systems.
Data Link Layer Design Issues

 Services Provided to the Network Layer

 Framing
 Error Control
 Flow Control
Services Provided to Network Layer
 Unacknowledged connectionless service: source machine send
independent frames to the destination machine without having the
destination machine acknowledge them.
 Acknowledged connectionless service : When this service is
offered, there are still no logical connections used, but each frame
sent is individually acknowledged. In this way, the sender knows
whether a frame has arrived correctly.
 Acknowledged connection-oriented service.
Framing
 Data link layer must use the service provided to it by the physical
layer.
 This bit stream is not guaranteed to be error free.
 Data link layer to break the bit stream up into discrete frames and
compute the checksum for each frame.
 When a frame arrives at the destination, the checksum is
recomputed.
 If the newly-computed checksum is different from the one contained
in the frame, the data link layer knows that an error has occurred and
takes steps to deal with it
 It is too risky to count on timing to mark the start and end of each
frame, we will look at four methods:
 Character count.
 Flag bytes with byte stuffing.
 Starting and ending flags, with bit stuffing.
 Physical layer coding violations.
PHYSICAL LAYER CODING VIOLATIONS
 This Framing Method is used only in those networks in which
Encoding on the Physical Medium contains some redundancy.
 Some LANs encode each bit of data by using two Physical Bits i.e.
Manchester coding is Used. Here, Bit 1 is encoded into high- low(10)
pair and Bit 0 is encoded into low-high(01) pair.
 The scheme means that every data bit has a transition in the middle,
making it easy for the receiver to locate the bit boundaries. The
combinations high-high and low-low are not used for data but are
used for delimiting frames in some protocols
Error Detection

When data is transmitted from one device to another device, the system
does not guarantee whether the data received by the device is identical
to the data transmitted by another device. An Error is a situation when
the message received at the receiver end is not identical to the message
transmitted.
Types Of Errors
Errors can be classified into two categories:
•Single-Bit Error
•Burst Error
Single-Bit Error:
The only one bit of a given data unit is changed from 1 to 0 or from 0 to 1.

In the above figure, the message which is sent is corrupted as single-

bit, i.e., 0 bit is changed to 1.
Single-Bit Error does not appear more likely in Serial Data
Transmission. For example, Sender sends the data at 10 Mbps, this
means that the bit lasts only for 1 s and for a single-bit error to
occurred, a noise must be more than 1 s.
Single-Bit Error mainly occurs in Parallel Data Transmission. For
example, if eight wires are used to send the eight bits of a byte, if one
of the wire is noisy, then single-bit is corrupted per byte.
Burst Error:
 The two or more bits are changed from 0 to 1 or from 1 to 0 is known as
Burst Error.
 The Burst Error is determined from the first corrupted bit to the last
corrupted bit.

 The duration of noise in Burst Error is more than the duration of noise
in Single-Bit.
 Burst Errors are most likely to occurr in Serial Data Transmission.
 The number of affected bits depends on the duration of the noise and
data rate.
Error Detecting Techniques:

 The most popular Error Detecting Techniques are:

• Single parity check
• Two-dimensional parity check
• Checksum
• Cyclic redundancy check
Single Parity Check

 Single Parity checking is the simple mechanism and inexpensive to

detect the errors.
 In this technique, a redundant bit is also known as a parity bit which
is appended at the end of the data unit so that the number of 1s
becomes even. Therefore, the total number of transmitted bits would
be 9 bits.
 If the number of 1s bits is odd, then parity bit 1 is appended and if
the number of 1s bits is even, then parity bit 0 is appended at the
end of the data unit.
 At the receiving end, the parity bit is calculated from the received
data bits and compared with the received parity bit.
 This technique generates the total number of 1s even, so it is known
as even-parity checking.
Drawbacks Of Single Parity Checking
•It can only detect single-bit errors which are very rare.
•If two bits are interchanged, then it cannot detect the errors.
 Two-Dimensional Parity Check

 Performance can be improved by using Two-Dimensional Parity

Check which organizes the data in the form of a table.
 Parity check bits are computed for each row, which is equivalent to the
single-parity check.
 In Two-Dimensional Parity check, a block of bits is divided into rows, and
the redundant row of bits is added to the whole block.
 At the receiving end, the parity bits are compared with the parity bits
computed from the received data.

Drawbacks Of 2D Parity Check

 If two bits in one data unit are corrupted and two bits exactly the same
position in another data unit are also corrupted, then 2D Parity checker
will not be able to detect the error.
 This technique cannot be used to detect the 4-bit errors or more in
some cases.
Checksum

A Checksum is an error detection technique based on the concept of

redundancy.
It is divided into two parts:
Checksum Generator
A Checksum is generated at the sending side. Checksum generator
subdivides the data into equal segments of n bits each, and all these
segments are added together by using one's complement arithmetic.
The sum is complemented and appended to the original data, known as
checksum field. The extended data is transmitted across the network.
The Sender follows the given steps:
 The block unit is divided into k sections, and each of n bits.
 All the k sections are added together by using one's complement to
get the sum.
 The sum is complemented and it becomes the checksum field.
 The original data and checksum field are sent across the network.

Checksum Checker
A Checksum is verified at the receiving side. The receiver subdivides the
incoming data into equal segments of n bits each, and all these segments are
added together, and then this sum is complemented. If the complement of
the sum is zero, then the data is accepted otherwise data is rejected.

The Receiver follows the given steps:

 The block unit is divided into k sections and each of n bits.
 All the k sections are added together by using one's complement
algorithm to get the sum.
 The sum is complemented.
 If the result of the sum is zero, then the data is accepted otherwis
e the data is discarded.
Cyclic Redundancy Check (CRC)

CRC is a redundancy error technique used to determine the error.

Following are the steps used in CRC for error detection:

 In CRC technique, a string of n 0s is appended to the data unit, and this n

number is less than the number of bits in a predetermined number, known as
division which is n+1 bits.
 Secondly, the newly extended data is divided by a divisor using a process is
known as binary division. The remainder generated from this division is known
as CRC remainder.
 Thirdly, the CRC remainder replaces the appended 0s at the end of the original
data. This newly generated unit is sent to the receiver.
 The receiver receives the data followed by the CRC remainder. The receiver
will treat this whole unit as a single unit, and it is divided by the same divisor
that was used to find the CRC remainder.
 If the resultant of this division is zero which means that it has no error, and the
data is accepted.
 If the resultant of this division is not zero which means that the data consists
Hamming Code
Hamming code is a set of error-correction codes that can be used to detect
and correct the errors that can occur when the data is moved or stored
from the sender to the receiver.
General Algorithm of Hamming code –
The Hamming Code is simply the use of extra parity bits to allow the
identification of an error.
 Write the bit positions starting from 1 in binary form (1, 10, 11, 100, etc).
 All the bit positions that are a power of 2 are marked as parity bits (1, 2, 4,
8, etc).
 All the other bit positions are marked as data bits.
 Each data bit is included in a unique set of parity bits, as determined its
bit position in binary form.
a. Parity bit 1 covers all the bits positions whose binary representation
includes a 1 in the least significant
position (1, 3, 5, 7, 9, 11, etc).
b. Parity bit 2 covers all the bits positions whose binary representation
includes a 1 in the second position from
the least significant bit (2, 3, 6, 7, 10, 11, etc).
b. Parity bit 2 covers all the bits positions whose binary representation
includes a 1 in the second position from
the least significant bit (2, 3, 6, 7, 10, 11, etc).
c. Parity bit 4 covers all the bits positions whose binary representation
includes a 1 in the third position from
the least significant bit (4–7, 12–15, 20–23, etc).
d. Parity bit 8 covers all the bits positions whose binary representation
includes a 1 in the fourth position from
the least significant bit bits (8–15, 24–31, 40–47, etc).
e. In general, each parity bit covers all bits where the bitwise AND of the
parity position and the bit position is
non-zero.
 Since we check for even parity set a parity bit to 1 if the total number of
ones in the positions it checks is
odd.
 Set a parity bit to 0 if the total number of ones in the positions it checks is
even.