8085

Micro Processor
Architecture

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 Session Objectives
• Explain various types of processor architecture
• Features of 8085 μProcessor
• Internal architecture of 8085 microprocessor
• Programmer’s model of 8085 microprocessor
• 8085 pin diagram & description

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 Von Neumann Architecture

Common memory for Data & program code

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 Harvard Architecture

Separate memory blocks for program (instructions) and data

–More efficient since accessing instructions and data can be
done in parallel

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 Super-Harvard Architecture (SHARC)

– Secondary data is stored in program memory to balance the load

on both memory blocks

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 Features of 8085
• It is an 8 bit microprocessor i.e. It can accept , process or
provide 8 bit data simultaneously.
• It has 16 bit address line i.e. it can access 216 = 64 kbytes of
memory.
• It can operate with a 3 MHz clock frequency.
• It operates on a single +5v power supply.
• It supports 74 instructions with different addressing modes.
• It provides five hardware interrupts: TRAP, RST 7.5, RST 6.5,
RST 5.5 & INTR.
• It has serial I/O control which allows the serial communication.
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 It consists of following functional blocks: -
1. Registers
2. ALU
3. Instruction decoder & Machine cycle encoder
4. Address buffer
5. Address / Data buffer
6. Increment / Decrement address latch
7. Interrupt control
8. Serial I/O control
9. Timing & control circuit
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1. REGISTERS
 The 8085 includes six registers, one accumulator, and one flag
register, as shown in Figure.
 In addition, it has two 16-bit registers: the stack pointer and the
program counter.
 The 8085 has six general-purpose registers to store 8-bit data; these
are identified as B,C,D,E,H, and L as shown in the figure.

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Classification of Registers: -
1. General purpose registers
2. Temporary registers
a) Temporary data register
b) W & Z register.
3. Special Purpose registers
a) Accumulator
b) Flag register
c) Instruction register
4. 16 Bit registers
a) Program counter
b) Stack Pointer 11
1.1 General purpose registers

The 8085 has six general-purpose registers to store 8-bit

data these are identified as B,C,D,E,H, and L. They can be
combined as register pairs - BC, DE, and HL - to perform
some 16-bit operations. The programmer can use these
registers to store or copy data into the registers by using
data copy instructions.
Also HL pair works as a memory pointer. These are also
called as scratchpad registers.

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 1.2 Temporary Registers
a) Temporary data register: - The ALU has two inputs one is supplied by the
accumulator & other from the temporary data register. These registers cannot
be accessed by the programmer.
For eg. ADD B : - it adds contents of reg A with reg B and stores the result in
reg A. In this case one input to ALU is from reg A directly but contents of reg B
are first transfer to temp reg & then to the ALU.
b) W & Z Registers: - these registers are used to hold the 8 bit data during
execution of some instructions, these are not accessible by the user because
used by the processor internally.
for eg. During calling a subprogram , contents of Program Counter are pushed
to stack & load the given address into PC. This given address is temporarily
stored in W & Z.
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 1.3 Special purpose registers
a) Accumulator : - The accumulator is an 8-bit register that is a part of
arithmetic/logic unit (ALU). This register is used to store 8-bit data and to
perform arithmetic and logical operations. The result of an operation is
stored in the accumulator. The accumulator is also identified as register
A.

b) Instruction Register:- Temporary store for the current instruction of

a program. Latest instruction sent here from memory prior to execution.
Decoder then takes instruction and ‘decodes’ or interprets the
instruction. Decoded instruction then passed to next stage.

c) Flag Register : - The ALU includes five flip-flops, which are set or
reset after an operation according to data conditions of the result in the
accumulator and other registers.
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• S – Sign Flag : - IF bit D7 of the result is 1, the sign flag is set, this means
result is negative number.
• Z – Zero flag: - It is set if the result of operation in ALU is zero.

• AC – Auxiliary carry flag: - This flag is set if carry from lower nibble is
generated.
• P- Parity flag:- Parity is defined as the number of 1 present in the
accumulator after operation. For even parity flag is set & for odd parity it is
reset.
• Cy – Carry flag: - This flag is set if a overflow at D7 bit is occurred, i.e carry
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 1.4 Sixteen Bit registers
a) Program Counter (PC):- This 16-bit register deals with sequencing
the execution of instructions. This register is a memory pointer. Memory
locations have 16-bit addresses, and that is why this is a 16-bit register.
The microprocessor uses this register to sequence the execution of the
instructions. The function of the program counter is to point to the
memory address from which the next byte is to be fetched. When a byte
(machine code) is being fetched, the program counter is incremented by
one to point to the next memory location

b) Stack Pointer (SP):- The stack pointer is also a 16-bit register used
as a memory pointer. It points to a memory location in R/W memory,
called the stack. The beginning of the stack is defined by loading 16-bit
address in the stack pointer. It holds the address of most recent stack
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entry.
2. Arithmetic Logic Unit
The ALU performs the actual numerical and logic operation such as ‘add’,
‘subtract’, ‘AND’, ‘OR’, etc. Uses data from memory and from Accumulator
to perform arithmetic. Always stores result of operation in Accumulator.
3. Instruction decoder
Processor first fetches the opcode from memory & store it in the instruction
register. Then it is sent to instruction decoder to decode & accordingly it
gives the timing & control signal which control the registers & data buffers.

4. Address Buffer
It is an 8 bit unidirectional buffer, used to drive external high order address
bus (A15 – A8).

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5. Address/ data Buffer
It is an 8 bit bidirectional buffer, used to drive multiplexed lower order
address bus (A7 – A0) & data bus (D7 – D0).

6. Increment / Decrement Address Latch

This 16 bit register is used to increment or decrement the contents of
program counter or stack pointer as a part of execution of instructions
related to them.
7. Interrupt control
It controls the occurrence of interrupts during the normal execution of
program.

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8.Serial I/O control
In situations like data transmission, communication with external devices
like CRT, cassette tape etc, data transmission is done serially. This control
provides two line SID & SOD for serial communication.

9.Timing & control Circuit

Control circuit generates signals within uP to carry out the instruction,
which has been decoded. In reality causes certain connections between
blocks of the uP to be opened or closed, so that data goes where it is
required, and so that ALU operations occur. It synchronized the operations
with clock signal.

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Pins of 8085 are classified in 7 categories

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ALE : - Address Latch Enable: It occurs during the first clock cycle of a machine state
and enables the address to get latched into the on chip latch of peripherals.

Detailed working of following circuit, we will see in bus organization topic .

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 8085 System Bus
Typical system uses a number of busses, collection of wires, which
transmit binary numbers, one bit per wire. A typical microprocessor
communicates with memory and other devices (input and output)
using three busses:
 Address Bus,
 Data Bus and
 Control Bus.

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 Address Bus

 One wire for each bit, therefore 16 bits = 16 wires. Binary number carried
alerts memory to ‘open’ the designated box.
 Data (binary) can then be put in or taken out.The Address Bus consists of
16 wires, therefore 16 bits. A 16 bit binary number allows 2 16 different
numbers, or 32000 different numbers, ie 0000h up to FFFFh.
 Because memory consists of boxes, each with a unique address, the size
of the address bus determines the size of memory, which can be used.
 To communicate with memory the microprocessor sends an address on the
address bus, eg 0000000000000011 (3 in decimal), to the memory. The
memory the selects box number 3 for reading or writing data.

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 Data Bus
 Data Bus: carries ‘data’, in binary form, between μP and other
external units, such as memory. Data bus used to transmit "data", i.e.
information, results of arithmetic, etc, between memory and the
microprocessor.
 Bus is bi-directional. Size of the data bus determines what arithmetic
can be done. If only 8 bits wide then largest number is 11111111 (255
in decimal). Therefore, larger number have to be broken down into
chunks of 255. This slows microprocessor.
 Data Bus also carries instructions from memory to the
microprocessor. Size of the bus therefore limits the number of
possible instructions to 256,

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 Control Bus

Control Bus are various lines which have specific functions for
coordinating and controlling uP operations. Eg: Read/NotWrite line,
single binary digit. Control whether memory is being ‘written to’ (data
stored in mem) or ‘read from’ (data taken out of mem) 1 = Read, 0 =
Write. May also include clock line(s) for timing/synchronising,
‘interrupts’, ‘reset’ etc.

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Microprocessors

V/S

Microcontrollers

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 MICROPROCESSORS MICROCONTROLLERS

contains No RAM, No ROM, No I/O ports. Microcontroller has CPU, RAM, ROM, I/O
ports, Timers, ADC and other peripherals.

Have the advantage of versatility on the The fixed amount of on-chip ROM, RAM,
amount of RAM, ROM, and I/O ports and number of I/O ports makes them ideal
for many applications in which cost and
space are critical

Must add RAM, ROM, I/O ports, and In many applications, the space it takes,
timers externally to make them functional the power it consumes, and the price per
this Make the system bulkier and much unit are much more critical considerations
more than the computing power
expensive

The prime use of microprocessor is to read The prime use of microcontroller is to

data, perform extensive calculations on control the operation of a machine using a
that data, and store those calculations. fixed program that is stored in ROM. 37
 Microprocessor Microcontroller
• CPU is stand-alone, RAM, • CPU, RAM, ROM, I/O and timer are all
ROM, I/O, timer are on a single chip
separate • fixed amount of on-chip ROM, RAM, I/O
• designer can decide on the ports
amount of ROM, RAM and • for applications in which cost, power
I/O ports. and space are critical
• expensive • single-purpose (control-oriented)
• versatility • Low processing power
• general-purpose • Low power consumption
• High processing power • Bit-level operations
• High power consumption • Instruction sets focus on control and bit-
• Instruction sets focus on level operations
processing-intensive • Typically 8/16 bit
operations • Typically single-cycle/two-stage pipeline
• Typically 32/64 – bit
• Typically deep pipeline (5-
20 stages)

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 8085
INSTRUNCTION SET
&
ASSEMBLY LANGUAGE PROGRAMMING

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 8085
INSTRUCTIONS
TIMING DIAGRAMS

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 The fetching ,decoding, and execution of a single instruction
constitutes an instruction cycle.
 Which consist of one to five read or write operations between
processor and memory or I/O devices. Each memory or I/O operation
requires a particular time period, called machine cycle.
 A machine cycle consists of 3 to 6 clock periods/ cycles called as T-
states.

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In 8085 microprocessor, signals are activated at specific instant
for specific time period.
ALE (Address Latch Enable): -
This signal is active high signal. It is activated in the beginning of
the T1 state of each machine cycle, except bus idle machine
cycle.

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A0 – A7 (Lower Byte Address)
The lower byte of address is available on the multiplexed address/data
bus (AD0 – AD7) during T1 state of each machine cycle, except bus
idle.

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D0 – D7 (Data Bus)
 The data from memory or I/O device and from microprocessor to
memory or I/O device is transferred during T2 – T3 states.
 In read machine cycle data will appear on the data bus during the
later part of the T2 – state.
 Whereas in write cycle data will appear on the data bus at the
beginning of T2 – state.

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 Machine Cycles

The 8085 has seven machine cycles as follows: -

1. Opcode Fetch

2. Memory Read

3. Memory Write

4. I/O Read

5. I/O write

6. Interrupt Acknowledge
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7. Bus Idle
OPCODE FETCH CYCLE: - The first machine cycle of every instruction is opcode fetch
cycle, in which 8085 finds the nature of the instruction to be executed. It consists of 4T
states to 6T states depending on the instruction.

T1: - 8085 places contents of PC on

the address bus. Since we have
address on both A8 – A15 & AD0 –
AD7, 8085 also activates ALE . Also
sends IO/M = 0, S1 = 1 & S0 = 1.

T2: - 8085 sends RD signal low to

enable the addressed memory location.
The memory device then places the
contents of addressed memory location
on data bus.

T3: - 8085 loads the data from the data

bus in its instruction register and raises
RD to high which disables the memory
device.

T4: - 8085 decodes the opcode and on

the basis of instruction received, it
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decides whether to enter T5.
Memory Read Cycle: - 8085 executes the memory read cycle to read the contents
of R/W memory or Rom. The length of this cycle is 3T states.

T1: - 8085 places the address on the

address lines from stack pointer, general
purpose register pair or PC and activates
ALE. IO/M = 0, S1 = 1, S0 = 0.

T2: - 8085 sends RD signal low to enable

the addressed memory location. Memory
devices then places the contents of
addressed memory location on the data
bus.

T3: - 8085 loads the data from the data

bus to specified register and raises the RD
to high which disables the memory device. 112
Memory Write Cycle: - 8085 executes the memory write cycle to store the data into the
memory or stack. The length of this cycle is 3T states.

T1: - 8085 places the address on the

address lines from stack pointer,
general purpose register pair or PC and
activates ALE. IO/M = 0, S1 = 0, S0 =
1.

T2: - 8085 places data on the data bus

and sends WR signal low for writing
into the addressed memory location.

T3: - WR signal goes high, which

disables the memory device and
terminates the write operation.
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 In response to INTR signal, 8085 executes interrupt acknowledge machine
cycle to read an instruction from the external device.
 The external device can place any instruction on the data bus in response to
INTA. Only RST and CALL save the PC contents before transferring control
to the interrupt service routine.
 The interrupt acknowledge cycle is similar to the opcode fetch cycle with two
exceptions.
 The INTA signal is activated instead of RD signal.
 The status lines are 111 instead of 011.

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TIMING DIAGRAM OF MVI A, 30H which is stored at 2000H

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Instruction: -

A000h LXI H, F045h

Coding

A000h 21
A001h 45
A002h F0

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Timing diagram for INR M

 Fetching the Opcode 34H from the memory 4105H. (OF cycle)
 Let the memory address (M) be 4250H. (MR cycle -To read
Memory address and data)
 Let the content of that memory is 12H. Increment the memory
content from 12H to 13H. (MW machine cycle)

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Timing diagram for STA 526AH.
 STA means Store Accumulator -The contents of the accumulator is stored
in the specified address(526A).
 The opcode of the STA instruction is said to be 32H. It is fetched from the
memory 41FFH -OF machine cycle
 Then the lower order memory address is read(6A). - Memory Read
Machine Cycle.
 Read the higher order memory address (52).- Memory Read Machine
Cycle.
 The combination of both the addresses are considered and the content
from accumulator is written in 526A. - Memory Write Machine Cycle.
 Assume the memory address for the instruction and let the content of
accumulator is C7H. So, C7H from accumulator is now stored in 526A.
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Timing diagram for IN C0H

 Fetching the Opcode DBH from the memory 4125H.

 Read the port address C0H from 4126H.
 Read the content of port C0H and send it to the
accumulator.
 Let the content of port is 5EH.

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ADD M

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 8085
Programming Techniques
*To be done in LAB
**Chapter 4 of godse

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 8085
Interrupts

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 Session Objectives
• Need of Interrupts
• Explain various types of Interrupts
• Classification of RST instructions
• Features & operation of8259 interrupt controller
• Interfacing of 8259

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• When a system has one or more I/O devices

connected, any of them may demand the service at

any time.

• The microprocessor can service these devices in one

of the two ways.

– Polling

– Interrupt

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 Polling
• In this μp simply checks each of the I/O devices every so often.
During this check the μp tests to see if any device needs
servicing.
• This is very time consuming and a separate polling program
need to be run continuously this wastes processors valuable
time and slow up the speed of operation of main program.
• The speed of operation decreases with increase in number of
I/O devices.
• Hence a more desirable method would be the one that allows
the μp to be executing its main program and only stop to
service I/O device when it is requested. 138
 Types of Interrupts
Interrupts could be classified on the following basis:-
1. Hardware interrupt & Software Interrupt
2. Vectored & Non-Vectored
3. Maskable & Non-maskable

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• Hardware Interrupt: - Some pins on the 8085 allow the
peripheral device to interrupt the main program for I/O
operations. When interrupt occurs 8085 completes the instruction
it is currently executing and transfers the program control to ISR.
• Eg: - TRAP, INTR, RST7.5, RST 6.5 & RST 5.5

• Software Interrupt: - In software interrupts, the cause of

interrupt is an execution of the instruction. Each of these would send

the execution to a predetermined hard-wired memory location.

• Eg: - RST 0 – RST 7

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 8085
MEMORY & I/O
INTERFACING

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Memory in a microprocessor system is where information (data and

instructions) is kept. It can be classified into two main types:

Main memory (RAM and ROM)

Storage memory (Disks , CD ROMs, etc.)

• The simple view of RAM is that it is made up of registers that are

made up of flip-flops (or memory elements). The number of flip-flops

in a “memory register” determines the size of the memory word.

• ROM on the other hand uses diodes instead of the flip-flops to

permanently hold the information.

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 Accessing Information in Memory

For the microprocessor to access (Read or Write)

information in memory (RAM or ROM), it needs to do

the following:
 Select the right memory chip (using part of the
address bus).
 Identify the memory location (using the rest of the
address bus).
 Access the data (using the data bus).

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 8085
I/O
INTERFACING

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 8085
INTERFACING

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 Various ICs interfaced to 8085 system
• 8251 USART
• 8254 programmable interval timer
• 8255 PPI (Programmable Peripheral Interface)
• 8259 Interrupt Controller
• 8279 Keyboard/Display interface.

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 8255
Programmable Peripheral
Interface

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Control Word for BSR mode: -

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 In this mode input or output data transfer is controlled by handshaking
signals.
 Handshaking signals are used to transfer data between devices whose
data transfer speeds are not same. Eg: - computer can send data to the
printer with larger speed but printer can’t accept data and print data with
this rate. So computer has to send data with the speed with which printer
can accept.
 Hand shaking signals are used to tell computer whether printer is ready to
accept the data or not. If printer is ready to accept the data then after
sending data on data bus, computer uses another handshaking signal to
tell printer that valid data is available on the data bus.

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Control Word for I/O mode: -

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 8253/54
programmable interval
timer

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 DCR C & JNZ BACK execute number of times equal to the count stored in C
register.
 There are two values specified for the number of T states for JNZ.
 Smaller value is applied when the condition is not met & the larger value
applied when the condition is met.

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Find the Maximum delay possible for 8 bit
count?

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 The 8253/54 solves one of most common problem in any
microcomputer system, the generation of accurate time delays under
software control.
 Instead of setting up timing loops in system software, the
programmer configures the 8253/54 to match his requirements,
initializes one of the counters of the 8253/54 with the desired
quantity, then upon command the 8253/54 will count out the delay
and interrupt the CPU when it has completed its tasks.
 The 8253/54 includes three identical 16 bit counters that can operate
independently.
 To operate a counter, a 16-bit count is loaded in its register and, on
command, it begins to decrement the count until it reaches 0. At the
end of the count, it generates a pulse that can be used to interrupt
the CPU. 220
 Features
1. Three independent 16-bit down counters.
2. 8254 can handle inputs from 0 to 10 where as 8253 can operate upto
2.6 MHz.
3. Three counters are identical presettable, and can be programmed for
either binary or BCD count.
4. Counter can be programmed in six different modes.
5. Compatible with all Intel and most other microprocessors.
6. 8254 has powerful command called READ BACK command which
allows the user to check the count value, programmed mode and
current mode and current status of the counter.

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Block Diagram

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Data Bus Buffer :
This tri-state, bi-directional, 8-bit buffer is used to interface the 8253/54 to the system
data bus. The Data bus buffer has three basic functions.
• Programming the modes of 8253/54.
• Loading the count registers.
• Reading the count values.

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Control Word Register : This register is accessed when lines A0 and A1
are at logic 1. It is used to write a command word which specifies the
counter to be used (binary or BCD), its mode, and either a read or write
operation.
Counters : These three functional blocks are identical in operation. Each
counter consists of a single, 16 bit, pre-settable, down counter. The
counter can operate in either binary or BCD and its input, gate and output
are configured by the selection of modes stored in the control word
register. The counters are fully independent. The programmer can read the
contents of any of the three counters without disturbing the actual count in
process.

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Operational Description
Each counter of the 8253/54 is individually programmed by writing a control word into the
control word register The Fig shows the control word format.

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 After power-up, the state of the 8254 is undefined. The Mode, count
value, and output of all Counters are undefined.
 How each Counter operates is determined when it is programmed.
Each Counter must be programmed before it can be used. Unused
counters need not be Programmed.
 Counters are programmed by writing a Control Word and then an
initial count.
 The Control Words are written into the Control Word Register, which
is selected when A1,A0 e 11. The Control Word itself specifies which
Counter is being programmed.

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 Programming the 8254
8254 can be programmed to provide various types of output through write
operation or to check the count while counting through read operations.
WRITE Operation :
1. Write a control word into control register.
2. Load the low-order byte of a count in the counter register.
3. Load the high-order byte of count in the counter register.

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READ Operation : In some applications, especially in event counters, it is

necessary to read the value of the count in process. This can be done by three

possible methods:

1. Simple Read : It involves reading a count after stopping the counter by

controlling the gate input or the clock input of the selected counter, and two I/O

read operations are performed by the CPU. The first I/O operation reads the low-

order byte, and the second I/O operation reads the high order byte.

2. Counter Latch Command : In the second method, an appropriate control word

is written into the control register to latch a count in the output latch, and two I/O

read operations are performed by the CPU. The first I/O operation reads the low-

order byte, and the second I/O operation reads the high order byte.
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3. Read-Back Command (Available only for 8254) : The third method
uses the Read-Back command. This command allows the user to
check the count value, programmed Mode, and current status of the
OUT pin and Null count flag of the selected counter(s). Fig. shows the
format of the control word register for Read-Back command.

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MODE OF OPERATION

 MODE 0 : Interrupt on terminal count

 MODE 1 : Hardware Re-triggerable One-shot

 MODE 2 : Rate generator

 MODE 3 : Square Wave Rate Generator

 MODE 4 : Software Triggered Strobe.

 MODE 5 : Hardware triggered strobe (Retriggerable).

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 Mode 0 : Interrupt on terminal count
1. The output will be initially low after the mode set operation.
2. GATE =1 enables counting; GATE =0 disables counting. GATE has no
effect on OUT.
3. After the count is loaded into the selected count Register the output will
remain low and the counter is decremented every cycle.
4. When the terminal count is reached the output will go high and remain
high until the selected count is reloaded. This high output signal can be
used as interrupt.

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After the Control Word and initial

count are written to a Counter, the

initial count will be loaded on the

next CLK pulse.

This CLK pulse does not

decrement the count, so for an

initial count of N, OUT does not go

high until N+1 CLK pulses after

the initial count is written.

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MODE 1: HARDWARE RETRIGGERABLE ONE-SHOT

 The output will be initially high.

The output will go low on the

CLK pulse following the rising

edge at the gate input.

 The output will go high on the

terminal count and remain high

until the next rising edge at the

gate input.

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 The one shot is re-triggerable, hence

the output will remain low for the full

count after any rising edge of the gate

input.

 If the counter is loaded during one

shot pulse, the current one shot is not

affected unless the counter is

retriggered. If retriggered, the counter

is loaded with the new count and the

one-shot pulse continues until the new

count expires.

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MODE 2 : Rate generator
It is used to generate a pulse equal to the clock period at a given interval.
When a count is loaded , the OUT stays high until the count reaches 1, and
then the out goes low for one clock period. The count is reloaded automatically
and the pulse is generated continuously.

236
 MODE 3 : Square Wave Rate Generator

Initially output is high. For even count, counter

is decremented by 2 on the falling edge of

each clock pulse. When the counter reaches

terminal count, the state of the output is

changed and the counter is reloaded with the

full count and the whole process is repeated.

If the count is odd and the output is high the

first clock pulse (after the count is loaded)

decrements the count by 1. Subsequent clock

pulses decrement the clock by 2. After timeout,

the output goes low and the full count is

237
MODE 4 : Software Triggered Strobe.

OUT will be initially high. When the initial count expires, OUT will go low for

one CLK pulse and then go high again. The counting sequence is

``triggered'‘ by writing the initial count.

238
MODE 5: HARDWARE TRIGGERED STROBE (RETRIGGERABLE)

 OUT will initially be high. Counting is triggered by a rising edge of GATE. When the

initial count has expired, OUT will go low for one CLK pulse and then go high again.

 After writing the Control Word and initial count, the counter will not be loaded until the

CLK pulse after a trigger. This CLK pulse does not decrement the count, so for an

initial count of N, OUT does not strobe low until N + 1 CLK pulses after a trigger.

239
Example 1: Write a program to initialize counter 2 in mode 0 with a count of C030H.
Assume address for control register = 0BH, counter 0 = 08H, counter 1 = 09H and counter 2 =
0AH.

Source Program
MVI A,B0H
OUT 0BH ; Loads control word (B0H) in the
control register.
MVI A,30H
OUT 0AH ; Loads lower byte of (30H)the count.
MVI A,C0H ; Loads higher byte (C0H) of the
count.
OUT 0AH

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 8259
Interrupt controller

241
 In 8085 microprocessor we get only 5 hardware
interrupt inputs.
 For application where we have multiple interrupt
sources more than 5, then we need external device
called a priority Interrupt Controller.
 By connecting such device we can increase the
interrupt handling capacity of the microprocessor.
 8259 is commonly used PIC, designed for use with
INTR & INTA.

242
Features of 8259
 It can manage 8 priority interrupts. This is equivalent to
providing 8 interrupt pins on the processor in place of INTR
pin.
 It is possible to locate vector table for these additional
interrupts anywhere in the memory map.
 By cascading nine 8259 it is possible to get 64 priority
interrupts.
 Individual interrupts could be masked by interrupt mask
register.
 8259 can be programmed as either level triggered or edge
243
triggered.
244
1. INTERRUPT REQUEST REGISTER (IRR) AND IN-SERVICE REGISTER (ISR): -

The interrupts at the IR input lines are handled by two registers in cascade, the

Interrupt Request Register (IRR) and the In-Service (ISR). The IRR is used to store

all the interrupt levels which are requesting service; and the ISR is used to store all

the interrupt levels which are being serviced.

2. PRIORITY RESOLVER: - This logic block determines the priorities of the bits set in

the IRR. The highest priority is selected and strobed into the corresponding bit of the

ISR during INTA pulse.

3. INTERRUPT MASK REGISTER (IMR): - The IMR stores the bits which mask the

interrupt lines to be masked. The IMR operates on the IRR. Masking of a higher

priority input will not affect the interrupt request lines of lower quality.

245
DATA BUS BUFFER : -This 3-state, bidirectional 8-bit buffer is used to interface the

8259A to the system Data Bus. Control words and status information are transferred

through the Data Bus Buffer.

READ/WRITE CONTROL LOGIC: - The function of this block is to accept Output

commands from the CPU. It contains the Initialization Command Word (ICW)

registers and Operation Command Word (OCW) registers which store the various

control formats for device operation. This function block also allows the status of the

8259A to be transferred onto the Data Bus.

246
THE CASCADE BUFFER/COMPARATOR : - This function block stores and

compares the IDs of all 8259A's used in the system. The associated three I/O pins

(CAS0-2) are outputs when the 8259A is used as a master and are inputs when

the 8259A is used as a slave. As a master, the 8259A sends the ID of the

interrupting slave device onto the CAS0±2 lines. The slave thus selected will send

its preprogrammed subroutine address onto the Data Bus during the next one or

two consecutive INTA pulses.

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 INTERRUPT SEQUENCE

The events occur as follows in an MCS-80/85 system:

 One or more of the INTERRUPT REQUEST lines (IR7±0) are raised high, setting

the corresponding IRR bit(s).

 The 8259A evaluates these requests, The priority resolver checks three registers:

IRR for interrupt requests, the IMR for masking bits, & the ISR for the interrupt

request being served, it resolves the priority and sends an INT to the CPU, if

appropriate.

 The CPU acknowledges the INT and responds with an INTA pulse.

248
 Upon receiving an INTA from the CPU group, the highest priority ISR bit is set,

and the corresponding IRR bit is reset. The 8259A will also release a CALL

instruction code (11001101) onto the 8-bit Data Bus through its D7±0 pins.

 This CALL instruction will initiate two more INTA pulses to be sent to the 8259A

from the CPU group.

 These two INTA pulses allow the 8259A to release its preprogrammed

subroutine address onto the Data Bus. The lower 8-bit address is released at the

first INTA pulse and the higher 8-bit address is released at the second INTA

pulse.

249
 PROGRAMMING THE 8259A

The 8259A accepts two types of command words generated by the CPU:

1. Initialization Command Words (ICWs): Before normal operation can begin, each 8259A in

the system must be brought to a starting point by a sequence of 2 to 4 bytes timed by WR

pulses.

2. Operation Command Words (OCWs): These are the command words which command the

8259A to operate in various interrupt modes. These modes are:

a. Fully nested mode

b. Rotating priority mode

c. Special mask mode

d. Polled mode
250
The OCWs can be written into the 8259A anytime after initialization.
 PRIORITY MODES OF OPERATION

1. Fully Nested Mode (FNM)

2. Rotating Priority Mode

3. Special Mask Mode

4. Poll Mode

251
Fully Nested Mode

 This mode is entered after initialization so it is called as default mode. The interrupt

requests are ordered in priority from 0 through 7 (0 highest).

 When an interrupt is acknowledged the highest priority request is determined and its

vector placed on the bus.

 Additionally, a bit of the Interrupt Service register (ISO-7) is set. This bit remains set

until the microprocessor issues an End of Interrupt (EOI) command immediately

before returning from the service routine, or if AEOI (Automatic End of Interrupt) bit is

set, until the trailing edge of the last INTA.

 While the IS bit is set, all further interrupts of the same or lower priority are inhibited,

while higher levels will generate an interrupt.

252
End of interrupt (EOI): -
 The ISR bit can be reset by an end of interrupt command issued by the MPU,
usually just before exiting from the interrupt routine.
 There are two forms of EOI command: Specific and Non-Specific. When the
8259A is operated in modes which preserve the fully nested structure, it can
determine which IS bit to reset on EOI.
 When a Non- Specific EOI command is issued the 8259A will automatically
reset the highest IS bit of those that are set, since in the fully nested mode the
highest IS level was necessarily the last level acknowledged and serviced.

Automatic End of Interrupt (AEOI) Mode : -

 In this mode the 8259A will automatically perform a non-specific EOI operation at the
trailing edge of the last interrupt acknowledge pulse.

 The AEOI mode can only be used in a master 8259A and not a slave.

253
Rotating Priority mode: -
In some applications there are a number of interrupting devices of equal priority. In
this mode a device, after being serviced, receives the lowest priority, so a device
requesting an interrupt will have to wait, in the worst case until each of 7 other
devices are serviced at most once .

254
There are two ways to accomplish Automatic Rotation

255
Special Mask Mode

Each Interrupt Request input can be masked individually by the Interrupt Mask

Register (IMR) programmed through OCW1. Each bit in the IMR masks one

interrupt channel if it is set (1). For example Bit 0 masks IR0, Bit 1 masks IR1 and

so forth.

 Some applications may require an interrupt service routine to dynamically alter the

system priority structure during its execution under software control.

 For example, the routine may wish to inhibit lower priority requests for a portion of its

execution but enable some of them for another portion.

256
Poll Mode

257
258
259
260
261
262
263
264
265
266
267
268
 It has eight bidirectional data lines supported by three handshake signals and five
general purpose interface management lines.
 The data lines are used to transfer data, addresses, commands and status bytes
among as many as 8 to 10 instruments.
 Below table shows the format for combination command address codes that a
controller can send to talker and listeners.
 Bit 8 is don’t care, bit 7 & 6 specify which command is being sent, and bit 1 to 5
gives the address of talker or listener to which command is to be sent.

269
270
271
Centronics Interface

272
 A parallel port is a type of interface found on computers (personal and otherwise) for

connecting peripherals. In computing, a parallel port is a parallel

communication physical interface. It is also known as a printer port or Centronics port.

 It was a de facto industry standard for many years, and was finally standardized

as IEEE 1284 in the late 1990s, which defined a bi-directional version of the port.

 Today, the parallel port interface is seeing decreasing use because of the rise

of Universal Serial Bus (USB) and FireWire (IEEE 1394) devices, along with network

printing using Ethernet.

 The parallel port interface was originally known as the LPT port (Line Print Terminal,

Local Print Terminal, or Line Printer) on IBM PC-compatible computers.

273
 8251
USART

274
The 8251 is a USART (Universal Synchronous Asynchronous Receiver Transmitter) for serial data
communication. As a peripheral device of a microcomputer system, the 8251 receives parallel data from
the CPU and transmits serial data after conversion. This device also receives serial data from the outside
and transmits parallel data to the CPU after conversion.

275
276
277
278
 Pin Description
D 0 to D 7 (l/O terminal) : - This is bidirectional data bus which receive control words and

transmits data from the CPU and sends status words and received data to CPU.

RESET (Input terminal): - A "High" on this input forces the 8251 into "reset status." The

device waits for the writing of "mode instruction." The min. reset width is six clock inputs

during the operating status of CLK.

CLK (Input terminal): -CLK signal is used to generate internal device timing. CLK signal is

independent of RXC or TXC. However, the frequency of CLK must be greater than 30 times

the RXC and TXC at Synchronous mode and Asynchronous "x1" mode, and must be greater

than 5 times at Asynchronous "x16" and "x64" mode.

279
WR (Input terminal): - This is the "active low" input terminal which receives a signal for

writing transmit data and control words from the CPU into the 8251.

RD (Input terminal): - This is the "active low" input terminal which receives a signal for

reading receive data and status words from the 8251.

C/D (Input terminal): - This is an input terminal which receives a signal for selecting

data or command words and status words when the 8251 is accessed by the CPU. If

C/D = low, data will be accessed. If C/D = high, command word or status word will be

accessed.

CS (Input terminal) : - This is the "active low" input terminal which selects the 8251 at

low level when the CPU accesses.

280
TXD (output terminal): - This is an output terminal for transmitting data from which serial-

converted data is sent out. The device is in "mark status" (high level) after resetting or during a

status when transmit is disabled. It is also possible to set the device in "break status" (low level)

by a command.

TXRDY (output terminal): - This is an output terminal which indicates that the 8251is ready to

accept a transmitted data character. But the terminal is always at low level if CTS = high or the

device was set in "TX disable status" by a command.

TXEMPTY (Output terminal): - This is an output terminal which indicates that the 8251 has

transmitted all the characters and had no data character. In "synchronous mode," the terminal is

at high level, if transmit data characters are no longer remaining and sync characters are

automatically transmitted.

281
TXC (Input terminal) : - This is a clock input signal which determines the transfer speed of

transmitted data. In "synchronous mode," the baud rate will be the same as the frequency of

TXC. In "asynchronous mode", it is possible to select the baud rate factor by mode

instruction. It can be 1, 1/16 or 1/64 the TXC. The falling edge of TXC sifts the serial data out

of the 8251.

RXD (input terminal) : - This is a terminal which receives serial data.

RXRDY (Output terminal): - This is a terminal which indicates that the 8251 contains a

character that is ready to READ. If the CPU reads a data character, RXRDY will be reset by the

leading edge of RD signal. Unless the CPU reads a data character before the next one is

received completely, the preceding data will be lost. In such a case, an overrun error flag

status word will be set.

282
RXC (Input terminal) : - This is a clock input signal which determines the transfer speed of
received data. In "synchronous mode," the baud rate is the same as the frequency of RXC.
In "asynchronous mode," it is possible to select the baud rate factor by mode instruction. It
can be 1, 1/16, 1/64 the RXC.

SYNDET/BD (Input or output terminal): - This is a terminal whose function changes

according to mode. In "internal synchronous mode." this terminal is at high level, if sync
characters are received and synchronized. If a status word is read, the terminal will be
reset. In "external synchronous mode, "this is an input terminal.
A "High" on this input forces the 8251 to start receiving data characters. In "asynchronous
mode," this is an output terminal which generates "high level" output upon the detection
of a "break" character if receiver data contains a "low-level" space between the stop bits of
two continuous characters. The terminal will be reset, if RXD is at high level. After Reset is
active, the terminal will be output at low level.

283
DSR (Input terminal): - This is an input port for MODEM interface. The input status of the

terminal can be recognized by the CPU reading status words.

DTR (Output terminal): - This is an output port for MODEM interface. It is possible to set

the status of DTR by a command.

CTS (Input terminal): - This is an input terminal for MODEM interface which is used for

controlling a transmit circuit. The terminal controls data transmission if the device is set in

"TX Enable" status by a command. Data is transmittable if the terminal is at low level.

RTS (Output terminal): - This is an output port for MODEM interface. It is possible to set

the status RTS by a command.

284
Control Words

There are two types of control word.

1. Mode instruction (setting of function)

2. Command (setting of operation)

1) Mode Instruction: - Mode instruction is used for setting the function of the 8251. Mode
instruction will be in "wait for write" at either internal reset or external reset. That is, the
writing of a control word after resetting will be recognized as a "mode instruction."
Items set by mode instruction are as follows:
 Synchronous/asynchronous mode
 Stop bit length (asynchronous mode)
 Character length
 Parity bit
 Baud rate factor (asynchronous mode)
 Internal/external synchronization (synchronous mode)
285
 Number of synchronous characters (Synchronous mode)
286
287
2) Command

Command is used for setting the operation of the 8251. It is possible to write a command

whenever necessary after writing a mode instruction and sync characters.

Items to be set by command are as follows:

• Transmit Enable/Disable

• Receive Enable/Disable

• DTR, RTS Output of data

• Resetting of error flag

• Sending to break characters

• Internal resetting

• Hunt mode (synchronous mode)

288
289
Status Word
It is possible to see the internal status of the 8251 by reading a status word.
The bit configuration of status word is shown

290
 8279
Keyboard & Display
Interface

291
292
Block Diagram: - It consists of four main sections:
1. CPU interface and control section
• Data buffers
• I/O Control
• Control & Timing registers
• Control & Timing logic
2. SCAN section
3. Keyboard section
• Return buffers
• Keyboard debounce & control
• FIFO / Sensor RAM
• FIFO / Sensor RAM status
4. Display section
• Display RAM
• Display address Registers
• Display registers 293
294
 Operating Modes

1. Input Modes

• Scanned Keyboard

• Scanned Sensor Matrix

• Strobed Input

2. Display Modes

• Left Entry (Type writer type)

• Right Entry (calculator type)

295