B19ECT601

Microprocessors & Microcontrollers

Dr.K.Ramasamy
Dean (Academics & Research)

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UNIT- I: 8- BIT and 16 - BIT MICROPROCESSOR

• Introduction to 8085
• 8086 Architecture
• Instruction set and programming
• Addressing modes
• Minimum and Maximum mode Configurations
• Coprocessor
• Multiprocessor.
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 Microprocessors
• A microprocessor is a controlling unit of a micro-computer, fabricated
on a small chip capable of performing Arithmetic Logical Unit (ALU)
operations and communicating with the other devices connected to it.

• Microprocessor consists of an ALU, register array, and a control unit.

ALU performs arithmetical and logical operations on the data received
from the memory or an input device. Register array consists of registers
identified by letters like B, C, D, E, H, L and accumulator. The control
unit controls the flow of data and instructions within the computer.

• How does a Microprocessor Work?

The microprocessor follows a sequence: Fetch, Decode, and then
Execute.

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Architecture of 8085 Microprocessor

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• 8085 is an 8-bit microprocessor designed by Intel in 1977
using NMOS technology.

• It has the following configuration:

• 8-bit data bus

• 16-bit address bus, which can address up to 64KB
• A 16-bit program counter
• A 16-bit stack pointer
• Six 8-bit registers arranged in pairs: BC, DE, HL
• Requires +5V supply to operate at 3.2 MHZ single phase clock
• It is used in washing machines, microwave ovens, mobile5
 8085 Microprocessor – Functional Units
Accumulator
• It is an 8-bit register used to perform arithmetic, logical, I/O & LOAD/STORE
operations. It is connected to internal data bus & ALU.

Arithmetic and logic unit

• As the name suggests, it performs arithmetic and logical operations like Addition,
Subtraction, AND, OR, etc. on 8-bit data.

General purpose register

• There are 6 general purpose registers in 8085 processor, i.e. B, C, D, E, H & L. Each
register can hold 8-bit data.

• These registers can work in pair to hold 16-bit data and their pairing combination is
like B-C, D-E & H-L.

Program counter
• It is a 16-bit register used to store the memory address location of the next
instruction to be executed. Microprocessor increments the program counter
whenever an instruction is being executed, so that the program counter points to6
Stack pointer
• It is also a 16-bit register works like stack, which is always incremented/decremented
during push & pop operations.

Temporary register
• It is an 8-bit register, which holds the temporary data of arithmetic and logical operations.

Flag register
• It is an 8-bit register having five 1-bit flip-flops, which holds either 0 or 1 depending upon
the result stored in the accumulator.

• These are the set of 5 flip-flops −

• Sign (S)
• Zero (Z)
• Auxiliary Carry (AC)
• Parity (P)
• Carry (C)
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Instruction register and decoder
• It is an 8-bit register. When an instruction is fetched from memory then it is stored
in the Instruction register. Instruction decoder decodes the information present in
the Instruction register.

Timing and control unit

• It provides timing and control signal to the microprocessor to perform operations.
Following are the timing and control signals, which control external and internal
circuits .

• Control Signals: READY, RD’, WR’, ALE

• Status Signals: S0, S1, IO/M’
• DMA Signals: HOLD, HLDA
• RESET Signals: RESET IN, RESET OUT
Interrupt control
• As the name suggests it controls the interrupts during a process. When a
microprocessor is executing a main program and whenever an interrupt occurs,
the microprocessor shifts the control from the main program to process the
incoming request. After the request is completed, the control goes back to the
main program. 8
Serial Input/output control
• It controls the serial data communication by using these two instructions:
SID (Serial input data) and SOD (Serial output data).

Address buffer and address-data buffer

• The content stored in the stack pointer and program counter is loaded into
the address buffer and address-data buffer to communicate with the CPU.
The memory and I/O chips are connected to these buses; the CPU can
exchange the desired data with the memory and I/O chips.

Address bus and data bus

• Data bus carries the data to be stored. It is bidirectional, whereas address
bus carries the location to where it should be stored and it is unidirectional.
It is used to transfer the data & Address I/O devices
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Microprocessor - 8085 Pin Configuration

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 Addressing Modes in 8085
Immediate addressing mode
• In this mode, the 8/16-bit data is specified in the instruction itself as one of its operand.
For example: MVI A, 20H: means 20H is copied into register A.

Register addressing mode

• In this mode, the data is copied from one register to another.
For example: MOV A, B: means data in register B is copied to register A.

Direct addressing mode

• In this mode, the data is directly copied from the given address to the register. For
example: LDB 5000H: means the data at address 5000H is copied to register B.

Indirect addressing mode

• In this mode, the data is transferred from one register to another by using the address
pointed by the register. For example: MOV A, M: means data is transferred from the
memory address pointed by the register pair (HL) to the register A.

Implied addressing mode

• This mode doesn’t require any operand; the data is specified by the opcode itself. For
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example: CLA.
• Interrupts in 8085
Interrupts are the signals generated by the external devices to request the microprocessor to
perform a task. There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR.
• Interrupt are classified into following groups based on their parameter −

• Vector interrupt − In this type of interrupt, the interrupt address is known to the processor.
For example: RST7.5, RST6.5, RST5.5, TRAP.

• Non-Vector interrupt − In this type of interrupt, the interrupt address is not known to the
processor so, the interrupt address needs to be sent externally by the device to perform
interrupts. For example: INTR.

• Maskable interrupt − In this type of interrupt, we can disable the interrupt by writing some
instructions into the program. For example: RST7.5, RST6.5, RST5.5.

• Non-Maskable interrupt − In this type of interrupt, we cannot disable the interrupt by writing
some instructions into the program. For example: TRAP.

• Software interrupt − In this type of interrupt, the programmer has to add the instructions
into the program to execute the interrupt. There are 8 software interrupts in 8085, i.e. RST0,
RST1, RST2, RST3, RST4, RST5, RST6, and RST7.
• Hardware interrupt − There are 5 interrupt pins in 8085 used as hardware interrupts, i.e.
TRAP, RST7.5, RST6.5, RST5.5, INTA.
• Note − INTA is not an interrupt, it is used by the microprocessor for sending
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acknowledgement. TRAP has the highest priority, then RST7.5 and so on.
 Interrupt Service Routine (ISR)
• A small program or a routine that when executed, services the corresponding
interrupting source is called an ISR.

TRAP
• It is a non-maskable interrupt, having the highest priority among all interrupts.
Bydefault, it is enabled until it gets acknowledged. In case of failure, it executes as
ISR and sends the data to backup memory. This interrupt transfers the control to
the location 0024H.
RST7.5
• It is a maskable interrupt, having the second highest priority among all interrupts.
When this interrupt is executed, the processor saves the content of the PC register
into the stack and branches to 003CH address.
RST 6.5
• It is a maskable interrupt, having the third highest priority among all interrupts.
When this interrupt is executed, the processor saves the content of the PC register
into the stack and branches to 0034H address.
RST 5.5
• It is a maskable interrupt. When this interrupt is executed, the processor saves the
content of the PC register into the stack and branches to 002CH address. 13
Instruction set of 8085

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Features of 8086 Microprocessor
• 1) The 8086 is a 16-bit microprocessor. The term “16-bit” means that its
arithmetic logic unit, internal registers and most of its instructions are
designed to work with 16-bit binary words.
• 2) The 8086 has a 16-bit data bus, so it can read data from or write data
to memory and ports either 16 bits or 8 bits at a time.
• 3) The 8086 has a 20-bit address bus, so it can directly access 220 or
10,48,576 (1Mb) memory locations. A sixteen-bit words are stored in two
consecutive memory locations.
• 4) The Features of 8086 Microprocessor can generate 16-bit I/O address,
hence it can access 216 = 65536 I/O ports.
• 5) The 8086 provides fourteen 16-bit registers.
• 6) The 8086 has multiplexed address and data bus which reduces the
number of pins needed, but does slow down the transfer of data
(drawback).
• 7) The 8086 requires one phase clock with a 33% duty cycle to provide
optimized internal timing. Range of clock rates are :- 5 MHz for 8086; 8
MHz for 8086-2; 10 MHz for 8086-1 15
• 8) The Features of 8086 Microprocessor is possible to perform bit, byte,
word and block operations in 8086. It performs the arithmetic and logical
operations on bit, byte, word and decimal numbers including multiply and
divide.
• 9) The Intel 8086 is designed to operate in two modes, namely the minimum
mode and the maximum mode. When only one 8086 CPU is to be used in a
microcomputer system, the 8086 is used in the minimum mode of operation.
In this mode the CPU issues the control signals required by memory and I/O
In multiprocessor (more than one processor in the system) system 8086
operates in maximum mode. In maximum mode, control signals are
generated with the help of external bus controller (8288).
• 10) The Intel 8086 supports multiprogramming. In multiprogramming, the
code for two or more processes is in memory at the same time and is
executed in a time-multiplexed fashion.
• 11) An interesting feature of the 8086 is that it fetches up to six instruction
bytes (4 instruction bytes for 8088) from memory and queue stores them in
order to speed up instruction execution.
• 12) The Features of 8086 Microprocessor provides powerful instruction set
with the following addressing modes: Register, immediate, direct, indirect
through an index or base, indirect through the sum of a base and an index 16
Architecture of 8086

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• The 8086 CPU is divided into two independent functional parts, the Bus interface unit (BIU)
and execution unit (EU).

• The Bus Interface Unit: contains Bus Interface Logic, Segment registers, Memory addressing
logic and a Six byte instruction object code queue. The BIU sends out address, fetches the
instructions from memory, read data from ports and memory, and writes the data to ports and
memory.

• The execution unit: contains the Data and Address registers, the Arithmetic and Logic Unit,
the Control Unit and flags. tells the BIU where to fetch instructions or data from, decodes
instructions and executes instruction. The EU contains control circuitry which directs internal
operations. A decoder in the EU translates instructions fetched from memory into a series of
actions which the EU carries out. The EU is has a 16-bit ALU which can add, subtract, AND,
OR, XOR, increment, decrement, complement or shift binary numbers. The EU is decoding an
instruction or executing an instruction which does not require use of the buses.

• In other words the BIU handles all transfers of data and addresses on the buses for the
execution unit.
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• The Queue: The BIU fetches up to 6 instruction bytes for the following
instructions. The BIU stores these prefetched bytes in first-in-first-out
register set called a queue. When the EU is ready for its next instruction it
simply reads the instruction byte(s) for the instruction from the queue in the
BIU. This is much faster than sending out an address to the system memory
and waiting for memory to send back the next instruction byte or bytes.

• Physical address formation: The 8086 addresses a segmented memory. The

complete physical address which is 20- bits long is generated using segment
and offset registers each of the size 16-bit.The content of a segment register
also called as segment address, and content of an offset register also called as
offset address. To get total physical address, put the lower nibble 0H to
segment address and add offset address. The fig shows formation of 20-bit
physical address.

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Physical address formation
41000H
0100H

PA=41100H
--------------

Register organization of 8086:

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Memory segmentation

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 Flag Register:

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Conditional Flags/Status Flags
• Carry Flag (CY): This flag indicates an overflow condition for unsigned
integer arithmetic. It is also used in multiple-precision arithmetic.
• Auxiliary Flag (AC): If an operation performed in ALU generates a
carry/barrow from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7),
the AC flag is set i.e. carry given by D3 bit to D4 is AC flag. This is not a
general-purpose flag, it is used internally by the Processor to perform Binary
to BCD conversion.
• Parity Flag (PF): This flag is used to indicate the parity of result. If lower
order 8-bits of the result contains even number of 1’s, the Parity Flag is set
and for odd number of 1’s, the Parity flag is reset.
• Zero Flag (ZF): It is set; if the result of arithmetic or logical operation is zero
else it is reset.
• Sign Flag (SF): In sign magnitude format the sign of number is indicated by
MSB bit. If the result of operation is negative, sign flag is set
• Overflow Flag: If the result exceeds 16 bit, OV is set. 23
Control Flags
• Control flags are set or reset deliberately to control the operations of the
execution unit. Control flags are as follows:
• Trap Flag (TF): It is used for single step control. It allows user to execute
one instruction of a program at a time for debugging. When trap flag is
set, program can be run in single step mode.
• Interrupt Flag (IF): It is an interrupt enable/disable flag. If it is set, the
maskable interrupt of 8086 is enabled and if it is reset, the interrupt is
disabled. It can be set by executing instruction sit and can be cleared by
executing CLI instruction.
• Direction Flag (DF): It is used in string operation. If it is set, string bytes
are accessed from higher memory address to lower memory address.
When it is reset, the string bytes are accessed from lower memory
address to higher memory address.
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Microprocessor - 8086 Pin Configuration

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26
 Addressing Modes

The 8086 has 12 addressing modes can be classified

into five groups.
• Addressing modes for accessing immediate and
register data (register and immediate modes).
• Addressing modes for accessing data in memory
(memory modes)
•Addressing modes for accessing I/O ports (I/O modes)
• Relative addressing mode
• Implied addressing mode

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1. Immediate addressing mode:
In this mode, 8 or 16 bit data can be specified as part of the instruction –
OP Code Immediate Operand
Example 1: MOV CL, 03 H:Moves the 8 bit data 03 H into CL
Example 2: MOV DX, 0525 H: Moves the 16 bit data 0525 H into DX
In the above two examples, the source operand is in immediate mode and the
destination operand is in register mode.
2. Register addressing mode:
The operand to be accessed is specified as residing in an internal register of 8086.
Example 1: MOV DX (Destination Register) , CX (Source Register) Which moves 16 bit
content of CS into DX.
Example 2: MOV CL, DL
Moves 8 bit contents of DL into CL
MOV BX, CH is an illegal instruction.
The register sizes must be the same
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3. Direct addressing mode:
• The instruction Opcode is followed by an
effective address, this effective address is directly
used as the 16 bit offset of the storage location
of the operand from the location specified by the
current value in the selected segment register.
• The default segment is always DS.
• The 20 bit physical address of the operand in
memory is normally obtained as PA = DS: EA
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 30500H
0040H
--------------
30540H=PA

•In the direct addressing mode, the 16 bit effective address (EA)
is taken directly from the displacement field of the instruction.
Example 1: MOV CX, START
•If the 16 bit value assigned to the offset START by the
programmer using an assembler pseudo instruction such as DW
is 0040 and [DS] = 3050. Then BIU generates the 20 bit physical
address 30540 H.
The content of 30540 is moved to CL The content of 30541 is
moved to CH
Example 2: MOV CH, START
If [DS] = 3050 and START = 0040
8 bit content of memory location 30540 is moved to CH. 30
4. Register indirect addressing mode:
• The EA is specified in either pointer (BX) register or an index (SI or
DI) register. The 20 bit physical address is computed using DS and
EA.
• Example: MOV [DI], BX
If [DS] = 5004, [DI] = 0020, [Bx] = 2456 PA=50060.
The content of BX (2456) is moved to memory locations 50060 H and
50061 H.

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5. Based addressing mode:

• When memory is accessed PA is computed from BX and DS

when the stack is accessed PA is computed from BP and SS.
• Example: MOV AL, START [BX] or
MOV AL, [START + BX]
In based mode
• EA: [START] + [BX]
• PA: [DS] + [EA]
• The 8 bit content of this memory location is moved to AL. 32
6. String addressing mode:
• The string instructions automatically assume SI to point to the
first byte or word of the source operand and DI to point to the
first byte or word of the destination operand. The contents of
SI and DI are automatically incremented (by clearing DF to 0
by CLD instruction) to point to the next byte or word.
• Example: MOV S BYTE
• If [DF] = 0, [DS] = 2000 H, [SI] = 0500, [ES] = 4000,
[DI] = 0300
• Source address: PA= [DS] + [SI]=20500
• Destination address: PA=[ES] + [DI] = 40300

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7.

8.

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9. I/O mode (direct):
• Port number is an 8 bit immediate operand. Example: OUT 05 H, AL
• Outputs [AL] to 8 bit port 05 H

10. I/O mode (indirect):

• The port number is taken from DX. Example 1: IN AL, DX
• If [DX] = 5040
• 8 bit content from port 5040 is moved into AL.
• Example 2: IN AX, DX
• Inputs 8 bit content of ports 5040 and 5041 into AL and AH respectively.

11. Relative addressing mode:

• Example: JNC START
• If CY=O, then PC is loaded with current PC contents plus 8 bit signed value of
START, otherwise the next instruction is executed.

12. Implied addressing mode:

• Instruction using this mode has no operands.
• 35
Example: CLC which clears carry flag to zero.
 INSTRUCTION SET OF 8086

The 8086 instructions are categorized into the following

main types.
1. Data Copy / Transfer Instructions
2. Arithmetic and Logical Instructions
3. Shift and Rotate Instructions
4. Loop Instructions
5. Branch Instructions
6. String Instructions
7. Flag Manipulation Instructions
8. Machine Control Instructions
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• Data Copy / Transfer Instructions:
• MOV:This instruction copies a word or a byte of data from some source to a
destination. The destination can be a register or a memory location. The source can
be a register, a memory location, or an immediate number.
• MOV AX, BX
• MOV AX, 5000H
• MOV AX, [SI]
• MOV AX, [2000H]
• MOV AX, 50H[BX]
• MOV [734AH], BX
• MOV DS, CX
• MOV CL, [357AH]

PUSH: Push to Stack

• This instruction pushes the contents of the specified register/memory location on to
the stack. The stack pointer is decremented by 2, after each execution of the
instruction.

E.g. PUSH AX
PUSH DS
PUSH [5000H] 37
POP: Pop from Stack
• This instruction when executed, loads the specified register/memory
location with the
• contents of the memory location of which the address is formed using
the current stack
• segment and stack pointer.
• The stack pointer is incremented by 2 Eg. POP AX
• POP DS
• POP [5000H]
XCHG: Exchange byte or word
• This instruction exchange the contents of the specified source and
destination operands
• Eg. XCHG [5000H], AX
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• XCHG BX, AX
• Input and output port transfer instructions: IN:Copy a byte or
word from specified port to accumulator.
• Eg. IN AL,03H
• IN AX,DX
• OUT:Copy a byte or word from accumulator specified port.
• Eg. OUT 03H, AL
• OUT DX, AX
• LEA:Load effective address of operand in specified register.
[reg] offset portion of address in DS
• Eg. LEA reg, offset
• LDS: Load DS register and other specified register from
memory.
• [reg] [mem]
• [DS] [mem + 2]
• Eg. LDS reg, mem 39
Flag transfer instructions: LAHF:
• Load (copy to) AH with the low byte the flag register
• Eg. LAHF

• SAHF:
• Store (copy) AH register to low byte of flag register.
• Eg. SAHF
• PUSHF:
• Copy flag register to top of stack. [SP]= [SP] – 2
• [[SP]] [Flags]
• Eg. PUSHF
• POPF:
• Copy word at top of stack to flag register. [Flags] [[SP]]
• [SP]= [SP] + 2
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Arithmetic operations:
• Addition, subtraction, negation, multiplication and comparing two
values.
ADD:
• The add instruction adds the contents of the source operand to the
destination operand.
• Eg. ADD AX, 0100H
• ADD AX, BX
• ADD AX, [SI]
• ADD AX, [5000H]
• ADD [5000H], 0100H
ADC: Add with Carry
• This instruction performs the same operation as ADD instruction, but
adds the carry flag to the result.
• Eg.
• ADC AX, BX
• ADC AX, [SI]
• ADC AX, [5000] 41
• SUB: Subtract
• The subtract instruction subtracts the source operand from
the destination operand and the result is left in the
destination operand.
• Eg. SUB AX, 0100H
• SUB AX, BX
• SUB AX, [5000H]
• SUB [5000H], 0100H
• SBB: Subtract with Borrow
• The subtract with borrow instruction subtracts the source
operand and the borrow flag (CF) which may reflect the result
of the previous calculations, from the destination operand
• Eg. SBB AX, 0100H
• SBB AX, BX
• SBB AX, [5000H]
• SBB [5000H], 0100H 42
• INC: Increment
• This instruction increases the contents of the specified Register or
memory location by
• Eg. INC AX
• INC [BX]
• INC [5000H]
• DEC: Decrement
• The decrement instruction subtracts 1 from the contents of the
specified register or memory location.
• Eg. DEC AX
• DEC [5000H]
• NEG: Negate
• The negate instruction forms 2’s complement of the specified
destination in the instruction. The destination can be a register or a
memory location. This instruction can be implemented by inverting
each bit and adding 1 to it.
• Eg. NEG AL
• AL = 0011 0101 =35H Replace number in AL with its 2’s complement AL43
= 1100 1011 = CBH
• CMP: Compare
• This instruction compares the source operand, which may
be a register or an immediate data or a memory location,
with a destination operand that may be a register or a
memory location
• Eg. CMP BX, 0100H
• CMP AX, 0100H
• CMP [5000H], 0100H
• CMP BX, [SI]
• CMP BX, CX
• MUL:Unsigned Multiplication Byte or Word
• This instruction multiplies an unsigned byte or word by
the contents of AL.
• Eg. MUL BH; (AX)= (AL) x (BH)
• MUL CX; (DX)(AX) =(AX) x (CX) 44
• IMUL: Signed Multiplication
• This instruction multiplies a signed byte in source operand by a signed byte in AL or
a signed word in source operand by a signed word in AX.
• Eg. IMUL BH
• IMUL CX
• CBW: Convert Signed Byte to Word
• This instruction copies the sign of a byte in AL to all the bits in AH. AH is then said to
be sign extension of AL.
• Eg. CBW
• AX= 0000 0000 1001 1000 Convert signed byte in AL signed word in AX. Result in AX
= 1111 1111 1001 1000
• CWD: Convert Signed Word to Double Word
• This instruction copies the sign of a byte in AL to all the bits in AH. AH is then said to
be sign extension of AL.
• Eg. CWD

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• DIV: Unsigned division
• This instruction is used to divide an unsigned word by a byte or to
divide an unsigned double word by a word.
• Eg. DIV CL; Word in AX / byte in CL; Quotient in AL, remainder in AH
• DIV CX; Double word in DX and AX / word; in CX, and Quotient in AX;
remainder in DX
• AAA: ASCII Adjust After Addition
• The AAA instruction is executed after an ADD instruction that adds
two ASCII coded operand to give a byte of result in AL. The AAA
instruction converts the resulting contents of AL to a unpacked
decimal digits.
• Example1: ADD CL, DL; [CL] = 32H = ASCII for 2; [DL] = 35H = ASCII
for 5; Result [CL]= 67H
MOV AL, CL; Move ASCII result into AL since AAA adjust only [AL] 46
• Example2:
• Addition of two one digit ASCII coded number
will not be ASCII. To convert the result to
ASCII, we use AAA after ADD instruction.

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• AAS: ASCII Adjust AL after Subtraction
• This instruction corrects the result in AL
register after subtracting two unpacked ASCII
operands. The result is in unpacked decimal
format. The procedure is similar to AAA
instruction except for the subtraction of 06
from AL.

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• AAM: ASCII Adjust after Multiplication
• This instruction, after execution, converts the product available In AL into unpacked BCD
format.
• Eg. MOV AL, 04; AL = 04
• MOV BL ,09; BL = 09
• MUL BL; AX = AL*BL; AX=24H
• AAM; AH = 03, AL=06
• AAD: ASCII Adjust before Division
• This instruction converts two unpacked BCD digits in AH and AL to the equivalent binary
number in AL. This adjustment must be made before dividing the two unpacked BCD
digits in AX by an unpacked BCD byte.
• In the instruction sequence, this instruction appears Before DIV instruction.
• Eg. AX 05 08
• AAD result in AL 00 3A 58D = 3A H in AL
• The result of AAD execution will give the hexadecimal number 3A in AL and 00 in AH
where 3A is the hexadecimal Equivalent of 58 (decimal).
• DAA: Decimal Adjust Accumulator
• This instruction is used to convert the result of the addition of two packed BCD numbers
to a valid BCD number. The result has to be only in AL.
• Eg. AL = 53; CL = 29
• ADD AL, CL; AL= (AL) + (CL); AL =53 + 29; AL =7C
• DAA; AL =7C + 06 (as C>9); AL=82 49
• DAS: Decimal Adjust after Subtraction
• This instruction converts the result of the
subtraction of two packed BCD numbers to a
valid BCD number. The subtraction has to be in
AL only.
• Eg. AL = 75, BH = 46
• SUB AL, BH; AL =2F = (AL) - (BH)
• DAS; AL =29 (as F>9, F - 6 = 9)

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•
Logical instructions
Eg. AND AX, 0008H
• AND AX, BX
• OR: Logical OR
• Eg. OR AX, 0008H
• OR AX, BX
• NOT: Logical Invert
• This instruction complements the contents of an operand register or a memory
location, bit by bit.
• Eg. NOT AX
• Eg. XOR AX, 0098H
• XOR AX, BX
• TEST: Logical Compare Instruction
• The TEST instruction performs a bit by bit logical AND operation on the two
operands.
• The result of this ANDing operation is not available for further use, but flags
are affected.
• Eg. TEST AX, BX 51
Shift and Rotate Instructions
SHL/SHR destination, count: Logical Shit
SHL:This instruction shifts each bit in the specified destination to the left and 0 is stored at
LSB position. The MSB is shifted into the carry flag. The number of shifts is indicated by
count.
Eg. SHL CL, 1
CY CL7 CL6 CL5 CL4 CL3 CL2 CL1 CL0
SHL AX, CL
SHR: SHR destination, count
This instruction shifts each bit in the specified destination to the right and 0 is stored at
MSB position. The LSB is shifted into the carry flag. The number of shifts is indicated by
count.
Eg. SHR CX, 1 CL7 CL6 CL5 CL4 CL3 CL2 CL1 CL0 CY
MOV CL, 05H
SHR AX, CL
SAR: SAR destination, count: Arithmetic Shift
This instruction shifts each bit in the specified destination some number of bit positions to
the right. As a bit is shifted out of the MSB position, a copy of the old MSB is put in the
MSB position. The LSB will be shifted into CF.
Eg. SAR BL, 1
MOV CL, 04H CL7 CL6 CL5 CL4 CL3 CL2 CL1 CL0 CY
SAR DX, CL
ROL Instruction: ROL destination, count CY CL7 CL6 CL5 CL4 CL3 CL2 CL1 CL0
This instruction rotates all bits in a specified byte or word to the left some number of bit
positions. MSB is placed as a new LSB and a new CF. 52
Eg. ROL CL, 1 MOV CL, 03H ROL BL, CL
• ROR Instruction: ROR destination, count
• This instruction rotates all bits in a specified byte or word to the right some number
of bit positions. LSB is placed as a new MSB and a new CF.
• Eg. ROR CL, 1 CL7 CL6 CL5 CL4 CL3 CL2 CL1 CL0 CY
• MOV CL, 03H
• ROR BL, CL
• RCL Instruction: RCL destination, count
• This instruction rotates all bits in a specified byte or word some number of bit
positions to the left along with the carry flag. MSB is placed as a new carry and
previous carry is place as new LSB.
• Eg. RCL CL, 1 CY CL7 CL6 CL5 CL4 CL3 CL2 CL1 CL0
• MOV CL, 04H
• RCL AL, CL

• RCR Instruction: RCR destination, count

• This instruction rotates all bits in a specified byte or word some number of bit
positions to the right along with the carry flag. LSB is placed as a new carry and
previous carry is place as new MSB.
• Eg. RCR CL, 1 CL7 CL6 CL5 CL4 CL3 CL2 CL1 CL0 CY
• MOV CL, 04H
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• RCR AL, CL
 Loop Instructions:
• Unconditional LOOP Instructions LOOP: LOOP Unconditionally
• This instruction executes the part of the program from the
Label or address specified in the instruction upto the LOOP
instruction CX number of times. At each iteration, CX is
decremented automatically and JUMP IF NOT ZERO structure.
• Example: MOV CX, 0004H
• Conditional LOOP Instructions LOOPZ / LOOPE Label
• Loop through a sequence of instructions from label while ZF=1
and CX=0.
• LOOPNZ / LOOPNE Label
• Loop through a sequence of instructions from label while ZF=1
and CX=0.

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Branch Instructions:
• Branch Instructions transfers the flow of execution of the program to a
new address specified in the instruction directly or indirectly. When this
type of instruction is executed, the CS and IP registers get loaded with
new Values of CS and IP corresponding to the location to be
transferred.
• The Branch Instructions are classified into two types
1. Unconditional Branch Instructions.
2. Conditional Branch Instructions.
Unconditional Branch Instructions:
• CALL: Unconditional Call
1. Near CALL i.e., ±32K displacement.
2. For CALL i.e., anywhere outside the segment.
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• RET: Return from the Procedure.
• INT N: Interrupt Type N.
• In the interrupt structure of 8086, 256 interrupts are defined
corresponding to the types from 00H to FFH. When INT N
instruction is executed, the type byte N is multiplied by 4 and
the contents of IP and CS of the interrupt service routine will be
taken from memory block in 0000 segment.
• INTO: Interrupt on Overflow
• This instruction is executed, when the overflow flag OF is set.
This is equivalent to a Type 4 Interrupt instruction.
• JMP: Unconditional Jump
• IRET: Return from ISR
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Conditional Branch Instructions
JZ/JE Label
Transfer execution control to address ‘Label’, if ZF=1.
JNZ/JNE Label
Transfer execution control to address ‘Label’, if ZF=0
JS Label
Transfer execution control to address ‘Label’, if SF=1.
JNS Label
Transfer execution control to address ‘Label’, if SF=0.
JO Label
Transfer execution control to address ‘Label’, if OF=1
JNO Label
Transfer execution control to address ‘Label’, if OF=0.
JNP Label
Transfer execution control to address ‘Label’, if PF=0.
JP Label
Transfer execution control to address ‘Label’, if PF=1.
JB Label
Transfer execution control to address ‘Label’, if CF=1.
JNB Label
Transfer execution control to address ‘Label’, if CF=0.
JCXZ Label
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Transfer execution control to address ‘Label’, if CX=0
 String Manipulation Instructions
• The 8086 supports a set of more powerful instructions
for string manipulations for referring to a string, two
parameters are required.
I. Starting and End Address of the String.
II. Length of the String.
• The length of the string is usually stored as count in the CX
register. The incrementing or decrementing of the pointer,
in string instructions, depends upon the Direction Flag (DF)
Status. If it is a Byte string operation, the index registers
are updated by one. On the other hand, if it is a word
string operation, the index registers are updated by two.
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• REP: Repeat Instruction Prefix
• This instruction is used as a prefix to other instructions, the instruction to
which the REP prefix is provided, is executed repeatedly until the CX register
becomes zero (at each iteration CX is automatically decremented by one).
• i. REPE / REPZ - repeat operation while equal / zero.
• ii. REPNE / REPNZ - repeat operation while not equal / not zero. These are
used for CMPS, SCAS instructions only, as instruction prefixes.
• MOVSB / MOVSW: Move String Byte or String Word
• CMPS: Compare String Byte or String Word
• SCAN: Scan String Byte or String Word
• LODS: Load String Byte or String Word
• STOS: Store String Byte or String Word
• The STOS instruction Stores the AL / AX register contents to a location in the
string pointer by ES: DI register pair. The DI is modified accordingly, No Flags
are affected by this instruction.
• The direction Flag controls the String instruction execution, The source index
SI and Destination Index DI are modified after each iteration automatically. If
DF=1, then the execution follows auto decrement mode, SI and DI are
decremented automatically after each iteration. If DF=0, then the execution
follows auto increment mode. In this mode, SI and DI are incremented 59
automatically after each iteration.
 Flag Manipulation and a Processor Control
Instructions
The Flag manipulation instructions directly modify some of the Flags of 8086.
i. CLC – Clear Carry Flag.
ii. CMC – Complement Carry Flag.
iii. STC – Set Carry Flag.
iv. CLD – Clear Direction Flag.
v. STD – Set Direction Flag.
vi. CLI – Clear Interrupt Flag.
vii. STI – Set Interrupt Flag.
Machine Control instructions
• The Machine control instructions control the bus usage and execution
i. WAIT – Wait for Test input pin to go low.
ii. HLT – Halt the process.
iii. NOP – No operation.
iv. ESC – Escape to external device like NDP
v. LOCK – Bus lock instruction prefix. 60
8086 Signals

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Minimum Mode 8086 System

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• Minimum mode: Single processor mode where 8086 generates all necessary control signals
directly
• MN/MX!=1
• 8086, Latches, Transceivers, Clock generator, memory and I/O devices
• Minimum mode signals:
• INTA!: Recognition of interrupt request
• ALE: Enables latch to separate address & data bits
• DEN!: Informs transceiver that CPU is ready to send/receive data
• DT/R!: Transmit/Receive data
• M/IO!: Data transfer is between CPU & memory or I/O
• WR!: Write operation
• HLDA!: Bus grant signal for DMA operation
• HOLD: Bus request signal for DMA operation
• Latch: 74LS373: Separates address from multiplexed address/data signals
• Controlled by ALE signal generated by 8086
• Address is latches & is available only during earlier part of cycle

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• Transceiver: 74245
• Bidirectional buffers/data amplifiers
• Separates data from multiplexed address/data signals
• Controlled by DEN!, DT/R!
• DEN! Indicates that valid data is available on data lines
• DT/R! indicates the direction of data transfer
• Clock generator: 8284
• Generates clock signal from crystal oscillator
• Synchronizes external signals with system clock
• Provides Reset signal
• Wait state logic
• It provides clock, Ready & Reset to 8086
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• Memory & I/O devices:
• M/IO!, RD! and WR!: Specify the type of data
transfer: Memory read, Memory write, IO
read & IO write

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Maximum mode configuiration

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• MN/MX!=0
• Multiprocessor mode: 8086, 8087/8089
• 8086 does not generate control signals directly.
Bus controller 8288 is used to generate control
signals
• 8288 uses S0, S1, S2 to indicate the current
machine cycle
• Maximum mode signals:
• QS1, QS0: indicates the status of instruction Queue
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S0!Si!S2!: Indicate type of current machine cycle
• 000 Interrupt acknowledge
• 001 IO read
• 010 IO write
• 011 Halt
• 100 Instruction fetch
• 101 Memory read
• 110 Memory write
• 111 Passive (Inactive)
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• LOCK!: Bus is reserved by one processor & is not available for
other processor in multiprocessor mode
• RQ!/GT1!: Bus request/Grant Low priority
• RQ!/GT0!: Bus request/Grant High priority
• Bus controller: 8288
• Derives control signals (RD!, WR!) for memory and IO devices,
DEN!, DT/R!, ALE, INTA! etc.
• Input to 8288: S0!, S1!, S2!, CLK
• AIOWC, AMWC: Advanced IO write, Memory write: Similar to
IOWC! And MWTC except that they are activated one clock cycle
earlier. This gives slow interfaces an extra clock cycle to prepare
to input data.
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 Multiprocessor Systems
• Multiprocessor Systems refer to the use of multiple processors that
execute instructions simultaneously and communicate using mailboxes.

• Maximum mode of 8086 is designed to implement 3 basic

multiprocessor configurations:
1. Coprocessor (8087)
2. Closely coupled (dedicated I/O processor: 8089)
3. Loosely coupled (Multi bus)

• Coprocessors and closely coupled configurations are similar - both the

CPU and the external processor share: Memory, I/O system, Bus & bus
control logic & Clock generator.
• In both configurations 8086 is the master or host & the supporting
processor is the slave.

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Coprocessor Configuration:
• For complex applications, 8086 is not sufficient. It should be supplemented with
coprocessors. 8086 has no instructions for performing floating point arithmetic. So by
using 8087 as a coprocessor, an application that heavily involves floating point calculations
can be readily satisfied.
• Both 8086 and 8087 execute their instructions from the same program
• 8086 performs opcode fetch cycles and identify the instructions for 8087. Once 8086
identifies the instruction of 8087, it is allotted to 8087 for further execution.
• After the completion of 8087 execution cycle, the results will be referred back to 8086
• ESC instruction:
• ESC opcode, operand
• opcode: instruction opcode: determines the action to be taken by the coprocessor
• When the CPU executes the ESC instruction, the processor accesses the memory operand
by placing the address on the address bus.
• Possible to have 2 coprocessors.
• WAIT instruction: It allows the processor to synchronize itself with external hardware, eg.,
waiting for 8087 math co-processor.
• BUSY pin of 8087 is connected to TEST! Pin of 8086. When 8087 is busy in executing some
instructions, it pulls BUSY high, so TEST! signal is also high and now 8086 is made to WAIT
until BUSY signal goes low. When 8087 completes execution of its instruction, BUSY signal
goes low & hence TEST! signal also goes low and now only 8086 goes for execution of its
program.
• WAIT instruction repeatedly checks TEST! pin until it becomes activated and then executes 71
the next instruction in sequence.
Synchronization between the 8086 and its
coprocesssor:
• If a coprocessor is configured to share the system
bus, it will recognize the ESC instruction and
therefore will get the opcode and the operand.

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Closely (Tightly) Coupled Configuration
• Coprocessor cannot take control of the bus, it does everything through
the CPU
• Closely Coupled processor may take control of the bus independently -
8089 shares CPU’s clock and bus control logic.
• Independent processor: 8089: Executes its own instruction system
• Instead of using ESC and WAIT instructions, communication with host CPU
is by way of shared memory to minimize the cost.
• Host (8086) sets up a message (command) in memory
• Independent processor interrupts host on completion or setup status bit
in the shared memory space.

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Interprocessor communication through shared memory

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 Loosely Coupled Configurations:
• Here number of modules of 8086 can be interfaced through a common system
bus to work as a multiprocessor system.
• A loosely coupled configuration provides the following advantages:
1. High system throughput can be achieved by having more than one CPU.
2. The system can be expanded in a modular form. Each bus master module is
an independent unit and normally resides on a separate PC board. Therefore, a
bus master module can be added or removed without affecting the other
modules in the system.
3. A failure in one module normally does not cause a breakdown of the entire
system and the faulty module can be easily detected and replaced.
4. Each bus master may have a local bus to access dedicated memory or I/O
devices so that a greater degree of parallel processing can be achieved. More
than one bus master module may have access to the shared system bus
Extra bus control logic must be provided to resolve the bus arbitration problem.
The extra logic is called bus access logic and it is its responsibility to make sure that
only one bus master at a time has control of the bus.
Simultaneous bus requests are resolved on a priority basis: There are three
schemes for establishing priority:
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 Bus allocation schemes
• Simultaneous bus requests are resolved on a priority basis:
Daisy chaining:
• Simplest, cheapest scheme
• No priority resolving network is needed
• Singe bus request line for requesting for the bus
• Controller sends bus grant signal if bus busy signal is inactive. It goes
through all masters in sequence till it reaches a requesting master
• The master then gains the control of bus, activates bus busy line &
starts using it
• Priority is decided by the position of the requesting master in the
sequence.
• Less HW; response time is high; failure of one module causes hole
system to fail.
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Polling method:
• Controller uses address lines to address each master in
sequence
• When the BR is received by the controller from a device, it
generates the address on the address lines. If the
generated address matches that of the requesting master,
controller activates the BUSY line.
• Once BUSY line is activated, controller stops generating
further address.
• Priority can be dynamically changed by changing the
polling sequence stored in the controller.
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Independent bus request scheme:
• It resolves priority in a parallel fashion
• Each module has a separate BR & BG lines & a priority assigned
to it
• Controller has a priority encoder, which selects the request with
highest priority & returns the corresponding BG signal.
• BUSY line is common to all the masters
• Arbitration is fast & independent of no of modules in the system
• Fast because each master communicates with controller
independently
• It requires BR & BG lines (2n lines for n modules)

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