CHAPTER 3

MEMORY MANAGEMENT
PART 2
 3.3 Paging
2

Logical Physical
In paging,
memorthe OS PAGE TABLE memory
ydivide the
physical memory
page frame Attributes
into frames which
are blocks of 0 4
small and fixed 1 3
size 2 1
3 5
 3.3 Paging
3

Logical Physical
In paging,
memorthe OS PAGE TABLE memory
ydivide the
physical memory
P0 whichpage
into frames
frame Attributes f0
P1
are blocks of 0 4 f1
smallP2
and fixed 1 3 f2
size 2 1
P3 f3
3 5 f4
f5
 3.3 Paging
4

Logical Physical
memor OS divides
PAGE TABLEalso the memory
y logical memory
(program) into
page frame Attributes
pages which are f0
0 4
blocks of size f1
1 equal
3 to frame
f2
size.
2 1 f3
3 5 f4
f5
 3.3 Paging
5

Logical Physical
memor OS divides
PAGE TABLEalso the memory
y logical memory
(program) into
P0 page frame Attributes
pages which are f0
P1 0 4
blocks of size f1
1 equal
3 to frame
P2 f2
size.
P3 2 1 f3
3 5 f4
f5
 3.3 Paging
6

Logical Physical
memor PAGE TABLE memory
y
P0 page frame Attributes f0
P1 0 4 f1
P2 1 3 f2
P3 2 1 f3
3 5 f4
f5

The OS uses a page table to map

program pages to memory frames.
 3.3 Paging
7

Logical Physical
memor PAGE TABLE memory
y
P0 page frame Attributes f0
P1 0 4 f1
P2 1 3 f2
P3 2 1 f3
3 5 P0 f4
f5

The OS uses a page table to map

program pages to memory frames.
 3.3 Paging
8

Logical Physical
memor PAGE TABLE memory
y
P0 page frame Attributes f0
P1 0 4 f1
P2 1 3 f2
P3 2 1 P1 f3
3 5 P0 f4
f5

The OS uses a page table to map

program pages to memory frames.
 3.3 Paging
9

Logical Physical
memor PAGE TABLE memory
y
P0 page frame Attributes f0
P1 0 4 P2 f1
P2 1 3 f2
P3 2 1 P1 f3
3 5 P0 f4
f5

The OS uses a page table to map

program pages to memory frames.
 3.3 Paging
10

Logical Physical
memor PAGE TABLE memory
y
P0 page frame Attributes f0
P1 0 4 P2 f1
P2 1 3 f2
P3 2 1 P1 f3
3 5 P0 f4
P3 f5

The OS uses a page table to map

program pages to memory frames.
 3.3 Paging
11

Logical Physical
memor PAGE TABLE memory
y
P0 page frame Attributes f0
P1 0 4 P2 f1
P2 1 3 f2
P3 2 1 P1 f3
3 5 P0 f4
P3 f5

Paging permits a program to allocate

noncontiguous blocks of memory
 3.3 Paging
12

 Page size (S) is defined by the hardware.

 Generally page size is chosen as a power of 2
such as 512 words/page or 4096 words/page
etc.

 With this arrangement, the words in the

program have an address called as logical
address. Every logical address is formed of
<p,d> pair
 3.3 Paging
13

 Logical address: <p,d>

p is page number
p = logical address div S
 d is displacement (offset)

d = logical address mod S

 3.3 Paging
14

 When a logical address <p, d> is

generated by the processor, first the
frame number f corresponding to
page p is determined by using the
page table and then the physical
address is calculated as (f*S+d) and
the memory is accessed.
 3.3 Paging
15

Logical Physical
address address
p d f d

pag fram attr

e e
d d
p f

p f

logical physical
memory memory
 3.3 Paging
16

Example 3.2
 Consider the following information to form a
physical memory map.
 Page Size = 8 words d : 3 bits
 Physical Memory Size = 128 words
= 128/8=16 frames f : 4 bits
 Assume maximum program size is 4 pages p :
2 bits
 A program of 3 pages where P0  f3; P1  f6;
P2  f4
 Logical memory Physical
memory
17 Word 0 … …
Word 1 Page 0 Word 0
… (P0) Word 1 Frame 3
Word 7 PAGE … (f3)
TABE
Word 8 Page Frame Word 7
Word 9 Page 1 0 3 Word 16
… (P1) 1 6 Word 17 Frame 4
Word 15 2 4 … (f4)
Word 16 Word 23
Word 17 Page 2
… (P2) … …
Word 23
Word 8
Word 9 Frame 6
… (f6)
Word 15
 3.3 Paging
18

Program
Line
Word 0
Word 1
…
Word 7
Word 8
Word 9
…
Word 15
Word 16
Word 17
…
Word 23
 3.3 Paging
19

Program Logical
Line Address
Word 0 00 000
Word 1 00 001
… …
Word 7 00 111
Word 8 01 000
Word 9 01 001
… …
Word 15 01 111
Word 16 10 000
Word 17 10 001
… …
Word 23 10 111
 3.3 Paging
20

Program Logical Offset

Line Address
Word 0 00 000 000
Word 1 00 001 001
… … …
Word 7 00 111 111
Word 8 01 000 000
Word 9 01 001 001
… … …
Word 15 01 111 111
Word 16 10 000 000
Word 17 10 001 001
… … …
Word 23 10 111 111
 3.3 Paging
21

Program Logical Offset Page

Line Address Number
Word 0 00 000 000 00
Word 1 00 001 001 00
… … … …
Word 7 00 111 111 00
Word 8 01 000 000 01
Word 9 01 001 001 01
… … … …
Word 15 01 111 111 01
Word 16 10 000 000 10
Word 17 10 001 001 10
… … … …
Word 23 10 111 111 10
 3.3 Paging
22

Program Logical Offset Page Frame

Line Address Number Number
Word 0 00 000 000 00 0011
Word 1 00 001 001 00 0011
… … … … …
Word 7 00 111 111 00 0011
Word 8 01 000 000 01 0010
Word 9 01 001 001 01 0010
… … … … …
Word 15 01 111 111 01 0010
Word 16 10 000 000 10 0000
Word 17 10 001 001 10 0000
… … … … …
Word 23 10 111 111 10 0100
 3.3 Paging
23

Program Logical Offset Page Frame Physical

Line Address Number Number Address
Word 0 00 000 000 00 0011 0011 000
Word 1 00 001 001 00 0011 0011 001
… … … … … …
Word 7 00 111 111 00 0011 0011 111
Word 8 01 000 000 01 0010 0110 000
Word 9 01 001 001 01 0010 0110 001
… … … … … …
Word 15 01 111 111 01 0010 0110 111
Word 16 10 000 000 10 0000 0100 000
Word 17 10 001 001 10 0000 0100 001
… … … … … …
Word 23 10 111 111 10 0100 0100 111
 3.3 Paging
24

 Every access to memory should go

through the page table. Therefore, it must
be implemented in an efficient way.

 How to Implement The Page Table?

 Using fast dedicated registers
 Keep the page table in main memory
 Use content-addressable associative
registers
 Using fast dedicated
25
registers
 Keep page table in fast dedicated
registers. Only the OS is able to modify
these registers.
 However, if the page table is large, this
method becomes very expensive since
requires too many registers.
 Using fast dedicated
26
registers
logical address PTLR: Page Table Length Register

p d

physical address
access
YES f d access
PT in
P<PTLR registe memor
rs y
NO rat mat

ERROR

Effective Memory Access Time

emat=rat+mat
 Keep the page table in main
memory
27

 In this second method, the OS keeps a

page table in the memory, instead of
registers.
 For every logical memory reference, two
memory accesses are required:
1. To access the page table in the memory, in
order to find the corresponding frame number.
2. To access the memory word in that frame
 This is cheap but a time consuming
method.
 Keep the page table in main memory
28

logical address PTBR: Page Table Base Register

PTLR: Page Table Length Register
p d
Access PT
entry physical address
in Memory
YES at f d access
P<PTLR address memor
PTBR + p y
NO mat mat

ERROR

Effective Memory Access Time:

emat=mat+mat=2mat
 Use content-addressable associative
registers
29

 This is a mixing of first two methods.

 Associative registers are small, high speed
registers built in a special way so that they
permit an associative search over their contents.
 That is, all registers may be searched in one
machine cycle simultaneously.
 However, associative registers are quite
expensive. So, a small number of them should
be used.
 In the overall, the method is not-expensive and
not-slow.
 Use content-addressable associative
registers
30

logical address physical address

f d
p d
Found?
Yes (HIT)
No (MISS)
Yes
P<PTLR search
PT in AR Access PT
entry physical address
in Memory
No rat at f d access
address memor
ERROR PTBR + p y

mat mat

Effective Memory Access Time: h: hit ratio

Emat=h *ematHIT + (1-h) * ematMISS =h(rat+mat)+(1-h)(rat+mat+mat)

 Use content-addressable associative
registers
31

 Assume we have a paging system which uses

associative registers. These associative registers
have an access time of 30 ns, and the memory
access time is 470 ns. The system has a hit ratio
of 90 %.

 rat=30 ns
 mat=470ns
 h=0.9
 Use content-addressable associative
registers
32

rat=30 ns, mat=470ns, h=0.9

 Now, if the page number is found in one of the

associative registers, then the effective access
time:

 ematHIT = 30 + 470 = 500 ns.

 Because one access to associative registers and

one access to the main memory is sufficient.
 Use content-addressable associative
registers
33

rat=30 ns, mat=470ns, h=0.9

 On the other hand, if the page number is not

found in associative registers, then the effective
access time:
 ematMISS = 30 + (470+470) = 970 ns.

 Since one access to associative registers and two

accesses to the main memory are required.
 Use content-addressable associative
registers
34

rat=30 ns, mat=470ns, h=0.9

ematHIT = 500 ns, ematMISS = 970 ns.

 Then, the emat is calculated as follows:

emat= h *ematHIT + (1-h) * ematMISS
= 0.9 * 500 + 0.1 * 970
= 450 + 97 = 547 ns
 Sharing Pages
35

 Sharing pages is possible in a paging system, and

is an important advantage of paging.
 It is possible to share system procedures or
programs, user procedures or programs, and
possibly data area.
 Sharing pages is especially advantageous in
time-sharing systems.
 Sharing Pages
36

 A reentrant program (non-self-modifying code =

read only) never changes during execution.
 So, more than one process can execute the same
code at the same time.
 Each process will have its own data storage and
its own copy of registers to hold the data for its
own execution of the shared program.
 Sharing Pages
37

 Example 3.4

 Consider a system having page size=30 MB.

 There are 3 users executing an editor program which is 90
MB (3 pages) in size, with a 30 MB (1 page) data space.
 To support these 3 users, the OS must allocate 3 * (90+30)
= 360 MB space.
 However, if the editor program is reentrant (non-self-
modifying code = read only), then it can be shared among
the users, and only one copy of the editor program is
sufficient. Therefore, only 90 + 30 * 3 = 180 MB of memory
space is enough for this case
 User-1 PT-1 Physical
P0 e1 Page# Frame# Memory
38
P1 e2 0 8 f0 OS
P2 e3 1 4 f1 OS
P3 data1 2 5 f2 OS
3 7 f3
f4 e2
User-2 PT-2 f5 e3
P0 e1 Page# Frame# f6
P1 e2 0 8 f7 data1
P2 e3 1 4 f8 e1
P3 data2 2 5 f9
3 12 f10
f11
User-3 PT-3 f12
P0 e1 Page# Frame# f13
P1 e2 0 8 f14
P2 e3 1 4 f15
P3 data3 2 5
3 10
 User-1 PT-1 Physical
P0 e1 Page# Frame# Memory
39
P1 e2 0 8 f0 OS
P2 e3 1 4 f1 OS
P3 data1 2 5 f2 OS
3 7 f3
f4 e2
User-2 PT-2 f5 e3
P0 e1 Page# Frame# f6
P1 e2 0 8 f7 data1
P2 e3 1 4 f8 e1
P3 data2 2 5 f9
3 12 f10
f11
User-3 PT-3 f12 data 2
P0 e1 Page# Frame# f13
P1 e2 0 8 f14
P2 e3 1 4 f15
P3 data3 2 5
3 10
 User-1 PT-1 Physical
P0 e1 Page# Frame# Memory
40
P1 e2 0 8 f0 OS
P2 e3 1 4 f1 OS
P3 data1 2 5 f2 OS
3 7 f3
f4 e2
User-2 PT-2 f5 e3
P0 e1 Page# Frame# f6
P1 e2 0 8 f7 data1
P2 e3 1 4 f8 e1
P3 data2 2 5 f9
3 12 f10 data3
f11
User-3 PT-3 f12 data 2
P0 e1 Page# Frame# f13
P1 e2 0 8 f14
P2 e3 1 4 f15
P3 data3 2 5
3 10
 User-1 PT-1 Physical
P0 e1 Page# Frame# Memory
41
P1 e2 0 8 f0 OS
P2 e3 1 4 f1 OS
P3 data1 2 5 f2 OS
3 7 f3
f4 e2
User-2 PT-2 f5 e3
User
P0 2 terminates:
e1 Page# Frame# f6
Data2 page is removed
P1 memory,
from e2 but 0 8 f7 data1
P2 pages
editör e3 remain.. 1 4 f8 e1
P3 data2 2 5 f9
3 12 f10 data3
f11
User-3 PT-3 f12
P0 e1 Page# Frame# f13
P1 e2 0 8 f14
P2 e3 1 4 f15
P3 data3 2 5
3 10
 User-1 PT-1 Physical
P0 e1 Page# Frame# Memory
42
P1 e2 0 8 f0 OS
P2 e3 1 4 f1 OS
UserP3
1 terminates:
data1 2 5 f2 OS
data1 is also
3 7 f3
removed from
memory. f4 e2
User-2 PT-2 f5 e3
P0 e1 Page# Frame# f6
P1 e2 0 8 f7
P2 e3 1 4 f8 e1
P3 data2 2 5 f9
3 12 f10 data3
f11
User-3 PT-3 f12
P0 e1 Page# Frame# f13
P1 e2 0 8 f14
P2 e3 1 4 f15
P3 data3 2 5
3 10
 User-1 PT-1 Physical
P0 e1 Page# Frame# Memory
43
P1 e2 0 8 f0 OS
P2 e3 1 4 f1 OS
P3 data1 2 5 f2 OS
3 7 f3
f4
User-2 PT-2 f5
P0 e1 Page# Frame# f6
P1 e2 0 8 f7
P2 e3 1 4 f8
P3 data2 2 5 f9
3 12 f10
f11
User-3
When PT-3
User 3 terminates: f12
P0 Data-3
e1 and also editor
Page# Frame# f13
segments are removed
P1 e2 memory.
from 0 8 f14
P2 e3 1 4 f15
P3 data3 2 5
3 10
44

 In segmentation, programs are divided into

variable size segments, instead of fixed size
pages.
 This is similar to variable partitioning, but
programs are divided to small parts.
 Every logical address is formed of a segment
name and an offset within that segment.
 In practice, segments are numbered.
 Programs are segmented automatically by the
compiler or assembler.
 3.4 Segmentation OS

45

 main
For example, a C compiler may create segments for:
 the code of each function
Func 1
 the local variables for each function

 the global variables.

Func 2
main
Data 1
Func 1 Func 2
Data 2
Data 1 Data 2
Data 3
Data 3

Logical memory Physical memory

 3.4 Segmentation
46

 For logical to physical address mapping, a

segment table is used. When a logical address
<s, d> is generated by the processor:
1. Base and limit values corresponding to segment s
are determined using the segment table
2. The OS checks whether d is in the limit. (0  d <
limit)
3. If so, then the physical address is calculated as
(base + d), and the memory is accessed.
 3.4 Segmentation OS

47

ERROR
Logical address No

s d 0≤d base
<limit
Segment Table
segment s
d
Yes

acess
seg. # the word at
limit base attr
physical
address
= base + d

Physical memory
 3.4 Segmentation
48

Example 3.5
Generate the memory map according to
the given segment table. Assume the
generated logical address is <1,1123>;
find the corresponding physical address.
Segment Limit Base
0 1500 1000
1 200 5500
2 700 6000
3 2000 3500
 0

3.4 Segmentation OS

49

Segment Limit Base

1000
0 1500 1000
s0 1500
1 200 5500
2500
2 700 6000
3 2000 3500 3500

s3 2000

5500
s1 200
5700
6000
s2 700
6700

Physical memory
 0

3.4 Segmentation OS

50

Segment Limit Base

1000
0 1500 1000
s0 1500
1 200 5500
2500
2 700 6000
3 2000 3500 3500

s3 2000

5500
Logical address: <3,1123> s1 200
s=3, d=1123 5700
Check if d<limit? 1123<2000, OK 6000
Physical address= base+d=3500+1123=4623 s2 700
6700

Physical memory
 0

3.4 Segmentation OS

51

Segment Limit Base

1000
0 1500 1000
s0 1500
1 200 5500
Base=
2500
2 700 6000 3500

3 2000 3500 3500

s3 2000

5500
Logical address: <3,1123> s1 200
s=3, d=1123 5700
Check if d<limit? 1123<2000, OK 6000
Physical address= base+d=3500+1123=4623 s2 700
6700

Physical memory
 0

3.4 Segmentation OS

52

Segment Limit Base

1000
0 1500 1000
s0 1500
1 200 5500
Base=
2500
2 700 6000 3500

3 2000 3500 3500

d=
1123 s3 2000
4623
5500
Logical address: <3,1123> s1 200
s=3, d=1123 5700
Check if d<limit? 1123<2000, OK 6000
Physical address= base+d=3500+1123=4623 s2 700
6700

Physical memory
 3.4 Segmentation
53

 Segment tables may be implemented in

the main memory or in associative
registers, in the same way it is done for
page tables.
 Also sharing of segments is applicable as
in paging. Shared segments should be
read only and should be assigned the
same segment number.
 0

Sharing Segments OS

54

user1 ST1
Editör seg lim base 1000
s0
0 1500 1000 Editör 1500
s1 Data-1 1 2000 3500
2500

3500

Data-1 2000

5500

Physical memory
 0

Sharing Segments OS

55

user1 ST1
Editör seg lim base 1000
s0
0 1500 1000 Editör 1500
s1 Data-1 1 2000 3500
2500

user2 ST2 3500

seg lim base
s0 Editör Data-1 2000
0 1500 1000
1 200 5500
s1 Data-2 5500
Data-2 200
5700

Physical memory
 0

Sharing Segments OS

56

user1 ST1
Editör seg lim base 1000
s0
0 1500 1000 Editör 1500
s1 Data-1 1 2000 3500
2500

user2 ST2 3500

seg lim base
s0 Editör Data-1 2000
0 1500 1000
1 200 5500
s1 Data-2 5500
Data-2 200
ST3 5700
user3 6000
seg lim base
Editör Data-3 700
s0 0 1500 1000
6700
1 700 6000
s1 Data-3
Physical memory
 0

Sharing Segments OS

57

user1 ST1
Editör seg lim base 1000
s0
0 1500 1000 Editör 1500
s1 Data-1 1 2000 3500
2500

3500
User 2 terminates:
Data-2 removed Data-1 2000
from memory, but
editör remains.. 5500

user3 ST3 6000

Editör seg lim base Dat-3 700
s0 6700
0 1500 100
s1 Data-3 1 700 6000
Physical memory
 0

Sharing Segments OS

58

User 1 terminates: 1000

Data-1segment is
removed from Editör 1500
memory.
2500

user3 6000
ST3 700
s0 Editör Data-3
seg lim base 6700
0 1500 100
s1 Data-3
1 700 6000 Physical memory
 0

Sharing Segments OS

59

When User 3 terminates:

Data-3and
Data-1 segment and
also editor
segments
also editor are removed
segment are
fromfrom
removed memory.
memory.

Physical memory