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ASIC Design Flow1

The document outlines the ASIC design flow, detailing each step from specification to tapeout. Key processes include RTL coding, synthesis, timing analysis, and logic verification, all aimed at creating efficient and functional application-specific integrated circuits. It emphasizes the importance of tools and methodologies used throughout the design process.

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1 views18 pages

ASIC Design Flow1

The document outlines the ASIC design flow, detailing each step from specification to tapeout. Key processes include RTL coding, synthesis, timing analysis, and logic verification, all aimed at creating efficient and functional application-specific integrated circuits. It emphasizes the importance of tools and methodologies used throughout the design process.

Uploaded by

cepita8571
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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ASIC DESIGN FLOW

Submitted To:- Submitted By:- Manju K. Chattopadhyay


Purvi Medawala
14MTES11
TABLE OF CONTENTS
 Introduction
 ASIC Design Flow
 Specification
 RTL Coding
 Test Bench & Simulation
 Synthesis
 Pre-layout Timing Analysis
 APR
 Back Annotation
 Post-layout Timing Analysis
 Logic Verification
 Tapeout
What is ASIC ?

 Application Specific
Integrated Circuit
 Build by connecting
existing circuit blocks in
new ways
 High speed, Lesser area
& power consumption,
more time to market
ASIC DESIGN FLOW
SPECIFICATION

 Features and functionalities of ASIC are defined


 Chip planning is performed
 Architecture and microarchitecture are derived
RTL CODING

 Microarchitecture converted into synthesizable RTL


code containing logic functionalities
 Graphical Tools like Summit Design’s or Mentor
Graphics are used
 Sometimes code is written manually
RTL CODING cont..
TEST BENCH AND SIMULATION

 Test bench created to


simulate RTL code using
HDL simulators
 Cadence’s Verilog XL,
Mentor Graphic’s Modelsim
are used
 Finally logically correct RTL
code obtained
SYNTHESIS

 RTL code converted into optimized logic gate level


representation
 Synthesis tools like Synopsys’s Design Compiler &
Cadence’s Ambit used
 “technology library” file & “constraints file” used
PRE-LAYOUT TIMING ANALYSIS

 synthesized database
along with timing
information from the
synthesis process used
to perform a Static
Timing Analysis
 Tweaking (making
small changes) has to
be done to correct any
timing issues
AUTOMATIC PLACE AND ROUTE
(APR)

 Layout is produced
 synthesized database together with timing
information from synthesis is used to place the logic
gates
 Designs have timing critical path
BACK ANNOTATION

 process where extraction for RC parasitics are made


from the layout.
 path delay is calculated from these RC parasitics
 Back annotation is the step that bridges synthesis
and physical layout
POST-LAYOUT TIMING ANALYSIS

 allows real timing


violations such as hold
and setup to be
detected
 net interconnect delay
information is fed into
the timing analysis and
any setup violation is
fixed
LOGIC VERIFICATION

 the final check to ensure the design is correct functionally after


additional timing information from layout
 Design is re-simulated using test benches with timing information
from layout
 If there are failures, fix it by moving back to step 2 or step 8
TAPEOUT

 When design passes


logical verification, its
ready for fabrication
 The tapeout design is
in the form of GDSII
file, which will be
accepted by the
foundry
REFRENCES

 Verilog
Coding for Logic Synthesis, edited by
Weng Fook Lee, John Wiley and Sons, Inc.
 CMOS Digital Integrated Circuits , Analysis
and Design by Sung-Mo Kang & Yusuf
Leblebici, TMH
ANY
QUESTIONS ????
THANK YOU !


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