Microprogrammed

Control Units
23I262- SHIVRAM
23I263-SHOBIKA
23I264-SHREE SUBHA
23I265-SHRI VISHNU
23I266-SNIGDHA
23I267-SREENIDHI
INTRODUCTION
SHREE SUBHA S(23I264)
 INTRODUCTION
• A microprogrammed control unit generates control signals
using a sequence of microinstructions stored in control
memory.
• Unlike a hardwired control unit, which uses fixed logic circuits,
this approach is more flexible and software-like.
• Control signals are produced by executing microinstructions,
each of which specifies low-level operations like data
movement or arithmetic.
• Acts as a midway between hardware and software.
• Facilitates easier updates, debugging, and extension of the
CPU’s capabilities.
A microinstruction typically consists of:

Control Signals: Bits specifying actions like reading from a register,

performing an ALU operation, or writing to memory.

Next Address Field: Specifies the address of the next

microinstruction to execute, enabling sequential or conditional
execution.

Flags/Status Bits: Used to handle conditions (e.g., zero flag, carry

flag) that influence branching decisions.
 ARCHITECTURE OF
MICROPROGRAMMED CONTROL UNITS
K G SNIGDHA(23I266)
 BLOCK DIAGRAM

•Control Memory interacts bidirectionally with the CMAR and CMDR.

•CMAR and Address Sequencer collaborate to determine and load the next
address.
•CMDR decodes the fetched microinstruction and generates control signals for
execution.
 KEY COMPONENTS
1. CONTROL MEMORY (CM):
Function: Stores microinstructions that dictate control signals
for the system.
Structure: Organized as a set of words, each representing a
microinstruction.
Role: Acts as the repository for the microprogram that defines
the behavior of the control unit.
Interaction: Interfaces with the CMAR and CMDR to fetch and
decode microinstructions, ensuring seamless control flow.
 KEY COMPONENTS
2. CONTROL MEMORY ADDRESS REGISTER (CMAR):
Function: Holds the address of the current microinstruction to be
fetched from the control memory.
Interaction:
• Updated by the Address Sequencer to point to the next
microinstruction.
• Outputs the address to control memory for fetching the
corresponding microinstruction.
• Supports branching by dynamically updating based on
conditional logic or return addresses.
 KEY COMPONENTS
3. CONTROL MEMORY DATA REGISTER (CMDR):
Function: Temporarily stores the fetched microinstruction from
control memory.
Interaction:
• Receives data from control memory after fetching.
• Passes the control signals and potential branching data to
other components.
• Facilitates decoding of the microinstruction to generate
control signals for executing processor operations.
 KEY COMPONENTS
4. ADDRESS SEQUENCER:
Function: Determines the next address to load into the
CMAR.
Capabilities:
• Sequential execution of microinstructions.
• Conditional or unconditional branching for control flow.
• Handling subroutine calls and returns.
Interaction: Relies on inputs from the CMDR and status flags
from the processor to calculate the next address.
 INTERACTION FLOW
1. FETCH PHASE:
• The CMAR provides the address of the current
microinstruction to the Control Memory.
• The Control Memory retrieves the microinstruction and
places it into the CMDR.
2. DECODE PHASE:
• The microinstruction in the CMDR is decoded to generate the
necessary control signals.
• Signals are distributed to the relevant components of the
processor (e.g., ALU, registers, memory).
 INTERACTION FLOW
3. EXECUTE PHASE:
• Based on the decoded control signals, the processor performs
the specified operations.
• If the microinstruction includes branching or subroutine
operations, the Address Sequencer calculates the next address.
4. NEXT INSTRUCTION DETERMINATION:
The Address Sequencer updates the CMAR with the next
microinstruction's address based on:
• Sequential progression.
• Conditional branching.
• Subroutine call or return.
ADDRESS SEQUENCER
SHOBIKA S 23I263
ADDRESS SEQUENCER:
Address Sequencing in computer architecture refers to the
method used to determine the next memory address to be accessed during
program execution. This can occur in various ways:

 Incrementing CAR by 1
 Subroutine Register
 Unconditional or Conditional branch
 Mapping Instruction
1. Incrementing CAR by 1 :
 It holds the address of the current microinstruction being executed.
 After the execution of the current microinstruction, the CAR is incremented
by 1 to point to the address of the next microinstruction in sequence.

2. Subroutine Register:
 A special register stores the return address (the address of the next
instruction after the subroutine call).
 When a subroutine is called, the current address is saved in the subroutine
register, and the CAR is set to the subroutine's start. After execution, the
return address is restored to the CAR.
3. Conditional and Unconditional Branch:
i. Conditional Branch:
The branch occurs only if a specified condition is true (e.g., result of a
comparison)
Example: IF X > 0, jump to address Y.
ii. Unconditional Branch:
The branch always occurs, regardless of any condition
Example: Jump to address Z.
4.Mapping Instruction:
 This process translates an instruction's logical address to its physical address in memory. It
ensures the CPU can locate and access instructions correctly.
 Techniques include direct mapping, associative mapping, and set-associative mapping,
often used in cache memory systems.
Microinstruction
Formats and
Addressing
-R SHRIVISHNU
 Structure of Microinstruction:
The structure of a microinstruction typically includes the following fields:
Opcode Field:
This part specifies the operation or task that needs to be performed,
like "add," "load," or "store.
Address Field:
It contains the address of the memory location or register involved in
the operation. This could be a source or destination address for data.
Control Bits:
These bits control various parts of the processor, such as the ALU
registers, and buses. They determine what actions should be taken for that
microinstruction.
 Difference between Horizontal and
Vertical Microinstructions:
Aspect Horizontal Microinstructions Vertical Microinstructions
Use many bits for controlling different
Control Signals Use fewer bits to control fewer parts.
parts.

High parallelism: Multiple operations Low parallelism: Fewer operations are

Parallelism
happen at the same time. controlled simultaneously.

Smaller in size due to fewer control

Size Larger in size due to more control bits.
bits.

Can be faster because many operations Can be slower as it executes fewer

Speed
are executed in parallel. operations at once.

More complex to design and

Complexity Simpler to design and implement.
implement.
 Addressing of Microinstruction:
• There are different ways to address or select microinstructions:
Direct Addressing:
The control unit directly knows where the next instruction is
and fetches it from that location.
Indirect Addressing:
The control unit first needs to find out where the next instruction is
(from a memory or register) before fetching it.
Immediate Addressing:
The next instruction already has the value or address it needs, so no
extra steps are required.
Design Techniques for
Microprogrammed
Control Units
SHIVRAM K | 23I262
 Control Memory
Organization
ROM -> Fixed
ROM-based Control Memory: RAM -> Flexible

• - Fixed microprograms stored in Read-Only Memory (ROM).

• - Advantages: Reliable and tamper-proof.
• - Drawback: Lack of flexibility to update instructions.

RAM-based Control Memory:

• - Reprogrammable microprograms stored in Random Access Memory (RAM).

• - Advantages: Flexible, suitable for dynamic systems.
• - Drawback: Needs extra security to protect data.
Optimization Techniques
Optimization Flow:
Reuse -> Memory Saved
Reducing Redundancy:

• - Identify common microinstruction sequences and reuse them.

• - Saves memory space and simplifies control logic.

Minimizing Control Memory Size:

• - Use encoding strategies to reduce the size of microinstructions.

• - Ensure no compromise on functionality.
Pipelined Microinstruction
Execution
Pipeline:
Fetch -> Decode -> Execute

• Introduce pipelining to process multiple

microinstructions simultaneously.
• - Example: Fetch one instruction while decoding
another.
• Result: Improves throughput and system
performance.
Subroutine Usage
• Modularize frequently used operations into subroutines:
• - Example: Arithmetic operations or data movement tasks.
Advantages:
• - Saves memory by reusing subroutines.
• - Simplifies design and maintenance.
Conclusion
• ROM vs. RAM: Fixed vs. flexible trade-offs.
• Optimizations: Focus on memory efficiency and speed.
• Subroutines and pipelining:
• - Key techniques to enhance modularity and performance.
• Practical relevance: Suitable for CISC architectures and embedded
systems.
 ADVANTAGES
AND
DISADVANTAGES
SREENIDHI(23I267)
ADVANTAGES:
• Flexibility:
Easily modifiable to support new instructions.
• Simpler Design:
Reduces Hardware Complexity.
• Debugging:
Logical errors in the control flow are easier to fix.
• Cost effective:
Reduces development costs for control units,especially for
CISC
DISADVANTAGES:
• Slower Execution:
Extra Cycles for micro instruction fetch and decode.
• Increased Memory Requirements:
Control memory occupies additional space.
• Unsuitable for High performance:
Modern CPU’s favor faster ,hardwired control units.
• Less Optimal for Simple Designs:
Overhead may be unnecessary for simple processors.
APPLICATIONS:
• CISC Architectures

• Embedded Systems

• Storage Controllers

• High Level Architecture support

• Multimedia Processors
THANK YOU