Module-4

Introduction to the ARM Instruction set: Introduction, Data

processing instructions, Load - Store instruction, Software
interrupt instructions, Program status register instructions,
Loading constants, ARMv5E extensions, Conditional Execution.
Text book 2: Chapter 3
Introduction
• Different ARM architecture revisions support different instructions.
• However, new revisions usually add instructions and remain
backwardly compatible.
• Code you write for architecture ARMv4T should execute on an
ARMv5TE processor
• We illustrate the processor operations using examples with pre- and
post-conditions, describing registers and memory before and after the
instruction or instructions are executed
• Notations : hexadecimal numbers with the prefix 0x and binary
numbers with the prefix 0b
• PRE <pre-conditions>
• <instruction/s>
• POST <post-conditions>
• In the pre- and post-conditions, memory is denoted as
• mem<data_size>[address]
• This refers to data_size bits of memory starting at the given byte
address. For example, mem32[1024] is the 32-bit value starting at
address 1 KB.
• ARM instructions process data held in registers and only access
memory with load and store instructions
• ARM instructions commonly take two or three operands. For instance
the ADD instruction below adds the two values stored in registers r1
and r2 (the source registers). It writes the result to register r3 (the
destination register).
Data Processing Instructions
• The data processing instructions manipulate data within registers. They
are move instructions, arithmetic instructions, logical instructions,
comparison instructions, and multiply instructions.
• Most data processing instructions can process one of their operands
using the barrel shifter.
• If you use the S suffix on a data processing instruction, then it updates
the flags in the cpsr. Move and logical operations update the carry flag C,
negative flag N, and zero flag Z.
• The carry flag is set from the result of the barrel shift as the last bit
shifted out.
• The N flag is set to bit 31 of the result. The Z flag is set if the result is zero.
Move Instructions
• Move is the simplest ARM instruction.
• It copies N into a destination register Rd, where N is a register or
immediate value.
• This instruction is useful for setting initial values and transferring data
between registers.
• Example 3.1 This example shows a simple move instruction.
• The MOV instruction takes the contents of register r5 and copies
them into register r7, in this case, taking the value 5, and overwriting
the value 8 in register r7.
• PRE r5 = 5 r7 = 8
• MOV r7, r5 ; let r7 = r5
• POST r5 = 5 r7 = 5
Barrel Shifter
• We showed a MOV instruction where N is a simple
register.
• But N can be more than just a register or immediate
value; it can also be a register Rm that has been
preprocessed by the barrel shifter prior to being used
by a data processing instruction.
• Data processing instructions are processed within
the arithmetic logic unit (ALU).
• A unique and powerful feature of the ARM processor
is the ability to shift the 32-bit binary pattern in one
of the source registers left or right by a specific
number of positions before it enters the ALU.
• This shift increases the power and flexibility of many
data processing operations
• PRE r5 = 5 r7 = 8
• MOV r7, r5, LSL #2 ; let r7 = r5*4 = (r5 << 2)
• POST r5 = 5 r7 = 20
Arithmetic Instructions
• Syntax: <instruction>{<cond>}{S} Rd, Rn, N
Data processing instructions
add r1,r1,r2 ;E0811002
add r0,r1,r1,lsl #1; E0810081
Logical Instructions
• Logical instructions perform bitwise logical operations on the two
source registers.
Comparison Instructions
• The comparison instructions are used to compare or test a register with a
32-bit value. They update the cpsr flag bits according to the result, but do
not affect other registers.
Multiply Instructions
• The multiply instructions multiply the contents of a pair of registers
and, depending upon the instruction, accumulate the results in with
another register.
• The long multiplies accumulate onto a pair of registers representing a
64-bit value. The final result is placed in a destination register or a
pair of registers
Branch Instructions
• A branch instruction changes the flow of execution or is used to call a routine.
• This type of instruction allows programs to have subroutines, if-then-else
structures, and loops
• The change of execution flow forces the program counter pc to point to a new
address
Load-Store Instructions
• Load-store instructions transfer data between memory and processor
registers. There are three types of load-store instructions: single-
register transfer, multiple-register transfer, and swap
Single-Register Transfer
Single-Register Load-Store
Addressing Modes
Multiple-Register Transfer
• Load-store multiple instructions can transfer multiple registers
between memory and the processor in a single instruction.
• The transfer occurs from a base address register Rn pointing into
memory.
• Multiple-register transfer instructions are more efficient from single-
register transfers for moving blocks of data around memory and
saving and restoring context and stacks.
PRE mem32[0x80018] = 0x03
mem32[0x80014] = 0x02
mem32[0x80010] = 0x01
r0 = 0x00080010
r1 = 0x00000000
r2 = 0x00000000
r3 = 0x00000000
LDMIA r0!, {r1-r3}
POST r0 = 0x0008001c
r1 = 0x00000001
r2 = 0x00000002
r3 = 0x00000003
We illustrate the use of the load-store multiple instructions with a block memory copy example. This example is a
simple routine that copies blocks of 32 bytes from a source address location to a destination address location

; r9 points to start of source data

; r10 points to start of destination data
; r11 points to end of the source
loop
; load 32 bytes from source and update r9 pointer
LDMIA r9!, {r0-r7}
; store 32 bytes to destination and update r10 pointer
STMIA r10!, {r0-r7} ; and store them
; have we reached the end
CMP r9, r11
BNE loop
Stack Operations
• The ARM architecture uses the load-store multiple instructions to carry out stack
operations.
• The pop operation (removing data from a stack) uses a load multiple instruction;
similarly, the push operation (placing data onto the stack) uses a store multiple
instruction.
• When using a stack you have to decide whether the stack will grow up or down in
memory.
• A stack is either ascending (A) or descending (D). Ascending stacks grow towards
higher memory addresses; in contrast, descending stacks grow towards lower
memory addresses.
• When you use a full stack (F), the stack pointer sp points to an address that is the
last used or full location (i.e., sp points to the last item on the stack).
• In contrast, if you use an empty stack (E) the sp points to an address that is the
first unused or empty location (i.e., it points after the last item on the stack).
Swap Instruction
• The swap instruction is a special case of a load-store instruction. It
swaps the contents of memory with the contents of a register.
• This instruction is an atomic operation—it reads and writes a location in
the same bus operation, preventing any other instruction from reading
or writing to that location until it completes.
Software Interrupt Instruction
• A software interrupt instruction (SWI) causes a software interrupt exception, which
provides a mechanism for applications to call operating system routines.
• When the processor executes an SWI instruction, it sets the program counter pc to the
offset 0x8 in the vector table.
• The instruction also forces the processor mode to SVC, which allows an operating system
routine to be called in a privileged mode
movs pc,r14_SVC
Program Status Register Instructions
• The ARM instruction set provides two instructions to directly control a program
status register (psr).
• The MRS instruction transfers the contents of either the cpsr or spsr into a
register; in the reverse direction, the MSR instruction transfers the contents of a
register into the cpsr or spsr.
Coprocessor Instructions
• Coprocessor instructions are used to extend the instruction set.
• A coprocessor can either provide additional computation capability
or be used to control the memory subsystem including caches and
memory management.
• The coprocessor instructions include data processing, register
transfer, and memory transfer instructions.
• In the syntax of the coprocessor instructions, the cp field represents the
coprocessor number between p0 and p15.
• The opcode fields describe the operation to take place on the coprocessor.
• The Cn, Cm, and Cd fields describe registers within the coprocessor. The
coprocessor operations and registers depend on the specific coprocessor
you are using.
• Coprocessor 15 (CP15) is reserved for system control purposes, such as
memory management, write buffer control, cache control, and
identification registers.
Loading Constants
• There is no ARM instruction to move a 32-bit constant into a register.
Since ARM instructions are 32 bits in size, they obviously cannot
specify a general 32-bit constant
• To aid programming there are two pseudoinstructions to move a 32-
bit value into a register
ARMv5E Extensions
Count Leading Zeros Instruction
• The count leading zeros instruction counts the number of zeros
between the most significant bit and the first bit set to 1. Example
3.30 shows an example of a CLZ
Saturated Arithmetic
• Normal ARM arithmetic instructions wrap around when you overflow an integer
value. For example, 0x7fffffff+1= -0x80000000.
• Thus, when you design an algorithm, you have to be careful not to exceed the
maximum representable value in a 32-bit integer.

PRE
cpsr = nzcvqiFt_SVC
r0 = 0x00000000
r1 = 0x70000000 (positive)
r2 = 0x7fffffff (positive)
ADDS r0, r1, r2
POST
cpsr = NzcVqiFt_SVC
r0 = 0xefffffff (negative)
Conditional Execution
• Most ARM instructions are conditionally executed—you can specify that the
instruction only executes if the condition code flags pass a given condition or test.
• The condition field is a two-letter mnemonic appended to the instruction
mnemonic. The default mnemonic is AL, or always execute.
GCD without conditional execution
GCD using conditional execution

gcd CMP r1, r2

SUBGT r1, r1, r2
SUBLT r2, r2, r1
BNE gcd