Timing Diagram
Timing Diagram
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100 ns
ns
Wait
Wait state
state
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inserted here
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General Bus Operation
The 8086 has a combined address and data bus commonly referred as
a time multiplexed address and data bus.
• The main reason behind multiplexing address and data over the
same pins is the maximum utilization of processor pins and it
facilitates the use of 40 pin standard DIP package.
Basically, all the processor bus cycles consist of at least four clock
cycles. These are referred to as T1, T2, T3, T4. The address is
transmitted by the processor during T1. It is present on the bus only
for one cycle.
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The negative edge of this ALE pulse is used to separate the
address and the data or status information. In maximum mode, the
status lines S0, S1 and S2 are used to indicate the type of
operation.
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General Bus Cycle For 8086
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Minimum Mode 8086 System
The microprocessor 8086 is operated in minimum mode by strapping
its MN/MX pin to logic 1.
In this mode, all the control signals are given out by the
microprocessor chip itself. There is a single microprocessor in the
minimum mode system.
The remaining components in the system are latches,
transreceivers, clock generator, memory and I/O devices.
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Minimum Mode Configuration For 8086
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Transreceivers are the bidirectional buffers and some times they are called as
data amplifiers. They are required to separate the valid data from the time
multiplexed address/data signals. They are controlled by two signals namely, DEN
and DT/R.
The DEN signal indicates the direction of data, i.e. from or to the processor.
The system contains memory for the monitor and users program storage.
Usually, EPROM are used for monitor storage, while RAM for users program
storage. A system may contain I/O devices.
The opcode fetch and read cycles are similar. Hence the timing diagram can be
categorized in two parts, the first is the timing diagram for read cycle and the
second is the timing diagram for write cycle.
The read cycle begins in T1 with the assertion of address latch enable (ALE)
signal and also M / IO signal. During the negative going edge of this signal, the
valid address is latched on the local bus.
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The BHE and A0 signals address low, high or both bytes. From T1
to T4, the M/IO signal indicates a memory or I/O operation.
At T2, the address is removed from the local bus and is sent to the
output. The bus is then tristated. The read (RD) control signal is also
activated in T2.
The read (RD) signal causes the address device to enable its data bus
drivers. After RD goes low, the valid data is available on the data bus.
The addressed device will drive the READY line high. When the
processor returns the read signal to high level, the addressed device will
again tristate its bus drivers.
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A write cycle also begins with the assertion of ALE and the
emission of the address.
The data remains on the bus until middle of T4 state. The WR becomes
active at the beginning of T2 (unlike RD is somewhat delayed in T2 to
provide time for floating).
The BHE and A0 signals are used to select the proper byte or bytes of
memory or I/O word to be read or write.
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Hold Response sequence:
The HOLD pin is checked at leading edge of each clock pulse. If it is
received active by the processor before T4 of the previous
cycle or during T1 state of the current cycle, the CPU activates HLDA in
the next clock cycle and for succeeding bus cycles, the bus will be given
to another requesting master.
The control of the bus is not regained by the processor until the
requesting master does not drop the HOLD pin low.
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Hold Response Timing Cycle
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Maximum Mode 8086 System
In the maximum mode, the 8086 is operated by strapping the MN/MX
pin to ground.
In this mode, the processor derives the status signal S2, S1, S0.
Another chip called bus controller derives the control signal using this
status information .
In the maximum mode, there may be more than one microprocessor in the
system configuration. The components in the system are same as in the
minimum mode system.
The basic function of the bus controller chip IC8288, is to derive control
signals like RD and WR ( for memory and I/O devices), DEN, DT/R, ALE etc.
using the information by the processor on the status lines.
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The bus controller chip has input lines S2, S1, S0 and CLK. These
inputs to 8288 are driven by CPU.
It derives the outputs ALE, DEN, DT/R, MRDC, MWTC, AMWC, IORC,
IOWC and AIOWC. The AEN, IOB and CEN
pins are specially useful for multiprocessor systems.
AEN and IOB are generally grounded. CEN pin is usually tied to
+5V. The significance of the MCE/PDEN output depends upon the status
of the IOB pin.
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IORC, IOWC are I/O read command and I/O write command signals
respectively . These signals enable an IO interface to read or write the
data from or to the address port.
The MRDC, MWTC are memory read command and memory write
command signals respectively and may be used as memory read or
write signals.
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Maximum Mode Configuration For 8086
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R0, S1, S2 are set at the beginning of bus cycle.8288 bus controller will output a
pulse as on the ALE and apply a required signal to its DT / R pin during T1.
In T2, 8288 will set DEN=1 thus enabling transceivers, and for an input it will
activate MRDC or IORC. These signals are activated until T4.
The status bit S0 to S2 remains active until T3 and become passive during T3
and T4.
If reader input is not activated before T3, wait state will be inserted between
T3 and T4.
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