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SystemVerilog oops

The document discusses Object-Oriented Programming (OOP) concepts and their application in SystemVerilog, highlighting features such as classes, encapsulation, inheritance, and polymorphism. It emphasizes the advantages of OOP in creating modular and maintainable testbenches compared to traditional procedural programming. Additionally, it contrasts SystemVerilog with C++, noting its type safety and automatic garbage collection capabilities.
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0% found this document useful (0 votes)
19 views

SystemVerilog oops

The document discusses Object-Oriented Programming (OOP) concepts and their application in SystemVerilog, highlighting features such as classes, encapsulation, inheritance, and polymorphism. It emphasizes the advantages of OOP in creating modular and maintainable testbenches compared to traditional procedural programming. Additionally, it contrasts SystemVerilog with C++, noting its type safety and automatic garbage collection capabilities.
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPT, PDF, TXT or read online on Scribd
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OOP Concepts

Why SystemVerilog?

Constrained Randomization Easy c model integration

OOP support New data types ie,logic


System Verilog
Assertions Coverage support

Narrow gap b/w design & verification engineer


What is OOP?

classes encapsulation

OOP

polymorphism inheritance
What is OOP?

 OOP is object oriented programming


 Classes form the base of OOP programming
 Encapsulation - OOP binds data & function together
 Inheritance –extend the functionality of existing objects
 Polymorphism – wait until runtime to bind data with
functions
What is OOP?

 OOP breaks a testbench into blocks that work together to


accomplish the verification goal
 Why OOP

• Highly abstract system level modelling


• Classes are intended for verification
• Classes are easily reused and extended
• Data security
• Classes are dynamic in nature
• Easy debugging, one class at a time
Why not C++

Why system
Verilog?

Why Not C++?


Why not C++

C++
C++ SystemVerilog
System Verilog

 No relation to  Superset of Verilog


verilog  RTL/Verification language
 Interface is required
 Assertion language
to interact with Verilog
 Constraint language
 Code coverage language
INTRODUCTION

• With procedural programming languages such as Verilog


and C, there is a strong division between data structures
and the code that uses them.
• OOPs create complex data types and tie them together
with the routines that work with them.
• create testbenches and system-level models at a more
abstract level by calling routines to perform an action
rather than toggling bits.
• When you work with transactions instead of signal
transitions, you are more productive.
• Grouping data and code together helps you in creating and
maintaining large testbenches.
• Traditional testbenches:create a transaction,transmit it,
receive it, check it, and make a report.
• You should divide your testbench into blocks, and then
define how they communicate.
CLASS

• A class encapsulates the data together


with the routines that manipulate it.
• There are two routines in the BusTran
class: a function to display the contents
of the packet, and another that computes
the CRC (cyclic redundancy check) of
the data.
• Class names start with a capital letter
and do not use underscores.
• Constants are all upper case, as while
variables are lower case.
• You are free to use whatever style you
want.
WHERE TO DEFINE A CLASS?

• You can define a class in SystemVerilog in a program,


module, package,or outside of any these.
• Many verification teams put either a standalone class or a
group of closely related classes in a file.
• Bundle the group of classes with a SystemVerilog
package.
OOP TERMINOLOGY
• Class – a basic building block containing routines and variables. The
analogue in Verilog is a module.
• Object – an instance of a class. In Verilog, you need to instantiate a
module to use it.
• Handle – a pointer to an object. In Verilog, you use the name of an
instance when you refer to signals and methods from outside the
module. An OOP handle is like the address of the object, but is stored
in a pointer that can only refer to one type.
• Property – a variable that holds data. In Verilog, this is a signal such
as a register or wire.
• Method – the procedural code that manipulates variables, contained
in tasks and functions. Verilog modules have tasks and functions plus
initial and always blocks.
• Prototype – the header of a routine that shows the name, type, and
argument list. The body of the routine contains the executable code.
OBJECTS
• Stimulus objects are constantly being created and used to drive the
DUT and check the results.
• Later, the objects may be freed so their memory can be used by new
ones.

• b is a handle that points to an object of type BusTran.


• When you declare the handle b, it is initialized to the special value
null.
• Next, you call the new function to construct the BusTran object. new
allocates space for the BusTran, initializes the variables to their default
value (0)for 2-state variables and X for 4-state ones), and returns the
address where the object is stored.
• For every class, SystemVerilog creates a default new to allocate and
initialize an object.
Custom Constructor
• When you call new to instantiate an object,you are
allocating a new block of memory to store the variables for
that object.
• You can define your own new function so that you can set
the values as you prefer. That is why the new function is
also called the “constructor,” as it builds the object.

• The above code sets addr and data to fixed values but
leaves crc at its default value of X.
The difference between new() and new[]
• new() function is called to construct a single object, while
the new[] operator is building an array with multiple
elements.
• new() can take arguments for setting object values, while
new[] only takes a single value for the array size.
Getting a handle on objects
• A handle can point to many objects. This is the dynamic
nature of OOP and SystemVerilog.
OBJECT DEALLOCATION

• Garbage collection is the process of automatically freeing


objects that are no longer referenced.
• One way SystemVerilog can tell if an object is no longer
being used is by keeping track of the number of handles
that point to it.When the last handle no longer references
an object, SystemVerilog releases the memory for it.
SV vs C++
• A SystemVerilog handle can only point to objects of one
type, so they are called “type-safe.”
• SystemVerilog performs automatic garbage collection
when no more handles refer to an object, you can be sure
your code always uses valid handles.
• In C / C++, a pointer can refer to an object that no longer
exists .code can suffer from “memory leaks” when you
forget to deallocate objects.
• SystemVerilog can not garbage collect an object that is
referenced by a handle. You need to manually clear all
handles by setting them to null.
Static Variables vs. Global Variables
• Every object has its own local variables that are not shared
with any other object. If you have two BusTran objects,
each has its own addr, crc, and data variables.
• create a global variable. Then you would have a global
variable that is used by one small piece of code, but is
visible to the entire testbench.
• a static variable inside a class. This variable is shared
between all instances of the class, but its scope is limited
to the class.
THANK YOU…..

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