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Unit 2_DLD

The document covers the design and functionality of various combinational circuits including half and full adders, subtractors, multiplexers, demultiplexers, encoders, decoders, comparators, and parity generators. It provides definitions, circuit diagrams, truth tables, and equations for each type of circuit. Additionally, it includes practice questions for designing and explaining the working of these circuits.
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0% found this document useful (0 votes)
6 views35 pages

Unit 2_DLD

The document covers the design and functionality of various combinational circuits including half and full adders, subtractors, multiplexers, demultiplexers, encoders, decoders, comparators, and parity generators. It provides definitions, circuit diagrams, truth tables, and equations for each type of circuit. Additionally, it includes practice questions for designing and explaining the working of these circuits.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Unit 2

Combinational Circuit
CONTENTS
• Design of Half and Full Adders, Half and Full Subtractors, BCD Adder,
Multiplexer, Demultiplexer, Decoder, Encoder, Comparators (2 bit),
Parity generators and Checker

• PAWAR5057
Half adder
• Definition
The Half Adder is a type of combinational logic circuit that adds
two of the 1-bit binary digits. It generates carry and sum of both
the inputs.
Block Diagram Truth table Equations
Sum= A XOR B
• Carry
= A AND B

Circuit diagram
Full adder
• Definition
The Full Adder is a type of combinational logic circuit that adds three of the
1-bit binary digits. It generates carry and sum of both the inputs.
Block Diagram Truth table Equations
Sum= A XOR B XOR C

Carry = AB + BCin + ACin

Circuit diagram
Half Subtractor
• Definition
The Half substractor is a type of combinational logic circuit that subtract
two of the 1-bit binary digits. It generates difference and borrow of
both the inputs.
Block Diagram Truth table Equations
Diff= A XOR B

Borrow = A B

Circuit diagram
Full Subtractor
• Definition
The full subtractor is a type of combinational logic circuit that subtract
three of the 1-bit binary digits. It generates difference and borrow of
both the inputs.
Block Diagram Truth table


• Circuit diagram
Full Subtractor
• Definition
The full subtractor is a type of combinational logic circuit that subtract
three of the 1-bit binary digits. It generates difference and borrow of
both the inputs.
Block Diagram Truth table


• Circuit diagram
Identify the conversion
BCD addition
Multiplexer
• A multiplexer is a combinational circuit that has 2n input
lines and a single output line.

The logical expression of the


term Y is as follows:
Y=S0'.A0+S0.A1
8:1 Multiplexer

Y=S0'.S1'.S2'.A0+S0.S1'.S2'.A1+S0'.S1.S2'.A2+
S0.S1.S2'.A3+S0'.S1'.S2 A4+S0.S1'.S2 A5+S0'.S
1.S2 .A6+S0.S1.S3.A7
8 ×1 multiplexer using 4×1 and 2×1 multiplexer
De multiplexers
• A De-multiplexer is a combinational circuit that has only
1 input line and 2N output lines
• 1×2 De-multiplexer:

Y0=S0'.A
Y1=S0.A
Design 1:4 Demux

Y0=S1' S0' A
y1=S1' S0 A
y2=S1 S0' A
y3=S1 S0 A
1×8 De-multiplexer using 1×4 and 1×2 de-multiplexer
Encoders
• An encoder is a combinational logic circuit that is used
to convert a normal or familiar information into a coded
format.
• Encoders are crucial components in various digital
electronics applications such as data transmission,
controlling and automation, communication, signal
processing, etc.
Encoders
The combinational circuits that change the binary information into N output lines are known
as Encoders.

A1=Y0+Y1
A0=Y2+Y0
8 to 3 line Encoder: Octal to Binary Encoder.

A2=Y4+Y5+Y6+
Y7
A1=Y2+Y3+Y6+
Y7
A0=Y7+Y5+Y3+
Y1
Decimal to BCD Encoder

A3 = Y9 + Y8
A2 = Y7 + Y6 + Y5 +Y4
A1 = Y7 + Y6 + Y3 +Y2
A0 = Y9 + Y7 +Y5 +Y3
+ Y1
Decoders
• Decoders are used for code conversions.
• Decoders are extensively used in memory systems of
computers.
• Decoders are also used for de-multiplexing or data
distribution.
• Decoder may also be used for timing or sequencing
purposes.
• Types: 2:4, 3:8, 4:16 etc.
Decoder:2 to 4 line decoder:

Y3=E.A1.A0
Y2=E.A1.A0'
Y1=E.A1'.A0
Y0=E.A1'.A0'
3 to 8 line decoder: Binary to Octal Decoder

Y0=A0'.A1'.A2'
Y1=A0.A1'.A2'
Y2=A0'.A1.A2'
Y3=A0.A1.A2'
Y4=A0'.A1'.A2
Y5=A0.A1'.A2
Y6=A0'.A1.A2
4 to 16 line Decoder

• Design on you own


Magnitude Comparator

• A magnitude digital Comparator is a combinational circuit


that compares two digital or binary numbers in order
to find out whether one binary number is equal, less than,
or greater than the other binary number.

A>B: AB’
A<B: A’B
A=B: A'B' +
AB
2 bit comparator

A>B:A1B1’ + A0B1’B0’ + A1A0B0’


: : :

A=B:-> A1’A0’B1’B0’ + A1’A0B1’B0 + A1A0B1B0 +


A<B:A1’B1 + A0’B1B0 +
A1A0’B1B0’
A1’A0’B0
-> A1’B1’ (A0’B0’ + A0B0) + A1B1 (A0B0 +
A0’B0’)
-> (A0B0 + A0’B0’) (A1B1 + A1’B1’)
-> (A0 Ex-Nor B0) (A1 Ex-Nor B1)
Parity bit checker and generator
• There are two types of parity bit generators based on
the type of parity bit being generated. Even parity
generator generates an even parity bit. Similarly, odd
parity generator generates an odd parity bit.
ODD Parity Generator

P = A XNOR B XNOR C
Parity checker – Even Parity checker
Parity checker – Odd Parity checker

PEC = (A Ex-NOR B) Ex-NOR (C Ex-


NOR P)
Practise Questions

• Design a half adder and full adder


• Design a half and full substractor
• Numerical on BCD adder
• Draw the circuit of 4 bit BCD adder
• Design 2:1/ 4:1/ 8:1/16:1 Multiplexer
• Design 16:1 Multiplexer using two 8:1 Multiplexer (similar questions on 4:1, 8:1 and 32:1)
• Design 1:2/ 1:4/ 1:8/1:16 De-Multiplexer
• Design 1:8 De-Multiplexer using two 1:4 De-Multiplexer (similar questions on 1:4, 1:8 and 1:32)
• Explain the working of 4:2/ 8:3/16:4 Encoder
• Explain the working of 2:4/ 3:8/4:16 decoder
• Explain the working of 2 bit and 4 bit comparator
• Explain the design of even parity generator and checker
• Explain the design of odd parity generator and checker
• Give application of adder, substractor, Mux, DeMux, encoder, decoder, comparator and Parity
generator

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