Finite State Machines

General Sequential System

Models of synchronous sequential systems Two common models of synchronous sequential systems
Moore machines Mealy machines

Moore Machine

Mealy Machine

Design of a three-bit counter

K-maps for 3-bit counter

3-bit counter circuit

Synchronous Sequential Circuit Analysis

10

Synchronous Sequential Circuit

State Memory A set of n edge-triggered flip-flops that store the current state of the machine All flip-flops are triggered from the same master clock signal All flip-flops change state together Combinational circuit Next state logic Output logic Mealy and Moore

Inputs

Combinational circuit

Outputs Next State

Current State

State Memory

Clock

11

Mealy Model
inputs Next-state Logic F clock input excitation State Memory current state Output Logic G

outputs

clock signal

Copyright 2000 by Prentice Hall, Inc. Digital Design Principles and Practices, 3/e

next state = F (current state, inputs) outputs = G (current state, inputs)

12

Moore Model
inputs Next-state Logic F clock input excitation State Memory current state Output Logic G outputs

clock signal
Copyright 2000 by Prentice Hall, Inc. Digital Design Principles and Practices, 3/e

next state = F (current state, inputs) outputs = G (current state)

13

Analysis - Goals
Characterize as Mealy or Moore machine Determine next state equations, i.e., find the function F next state = F (current state, inputs) Determine output equations Meally: outputs = G (current state, inputs), or Moore: outputs = G (current state) Express as machine behavior State table, or State diagram Formulate English description of machine behavior

14

An example sequential circuit

A sequential circuit with two JK flip-flops State or memory: Q1Q0 One input: X; One output: Z
15

State table of example circuit

Present State Q1 Q0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1

Inputs X 0 1 0 1 0 1 0 1

Next State Q1 Q0

Outputs Z

16

Output Equations
From the diagram, you can see that Z = Q1Q0X Mealy model circuit !!!

Present State Q1 Q0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1

Inputs X 0 1 0 1 0 1 0 1

Next State Q1 Q0

Outputs Z 0 0 0 0 0 0 0 1
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Next State Equations Q(t+1)

Find the flip-flop input equations/excitation equations Substitute excitation equations in the flip-flops characteristic equation

J1 = X Q0 K1 = X + Q0 J0 = X + Q1 K0 = X

18

 Excitation equations:

Next State Equations Q(t+1)

J1 = X Q0 and K1 = X + Q0 J0 = X + Q1 and K0 = X

Characteristic equation of the JK flip-flop:

Q(t+1) = KQ(t) + JQ(t) Next state equations: Q1(t+1) = K1Q1(t) + J1Q1(t) = (X + Q0(t)) Q1(t) + X Q0 (t) Q1(t) = X (Q0(t) Q1(t) + Q0(t) Q1(t)) = X (Q0(t) Q1(t)) Q0(t+1) = K0Q0(t) + J0Q0(t) = X Q0(t) + (X + Q1(t)) Q0(t) = X + Q0(t) Q1(t)
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 Excitation equations:

Next State Equations Q(t+1)

J1 = X Q0 and K1 = X + Q0 J0 = X + Q1 and K0 = X

Characteristic equation of the JK flip-flop:

Q(t+1) = KQ(t) + JQ(t) Next state equations: Q1(t+1) = K1Q1(t) + J1Q1(t) = (X + Q0(t)) Q1(t) + X Q0 (t) Q1(t) = X (Q0(t) Q1(t) + Q0(t) Q1(t)) = X (Q0(t) Q1(t)) Q0(t+1) = K0Q0(t) + J0Q0(t) = X Q0(t) + (X + Q1(t)) Q0(t) = X + Q0(t) Q1(t)
20

 Excitation equations:

Next State Equations Q(t+1)

J1 = X Q0 and K1 = X + Q0 J0 = X + Q1 and K0 = X

Characteristic equation of the JK flip-flop:

Q(t+1) = KQ(t) + JQ(t) Next state equations: Q1(t+1) = K1Q1(t) + J1Q1(t) = (X + Q0(t)) Q1(t) + X Q0 (t) Q1(t) = X (Q0(t) Q1(t) + Q0(t) Q1(t)) = X (Q0(t) Q1(t)) Q0(t+1) = K0Q0(t) + J0Q0(t) = X Q0(t) + (X + Q1(t)) Q0(t) = X + Q0(t) Q1(t)
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State Table & Next State Equations

Q1(t+1) = X (Q0(t) Q1(t)) Q1=0, Q0=0, X= 0 => Q1(t+1)= 0 Q0(t+1) = X + Q0(t) Q1(t) Q1=0, Q0=0, X= 0 => Q0(t+1)= 0

Present State Q1 Q0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1

Inputs X 0 1 0 1 0 1 0 1

Next State Q1 Q0 0 0

Outputs Z 0 0 0 0 0 0 0 1
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State Table & Next State Equations

Q1(t+1) = X (Q0(t) Q1(t)) Q1=0, Q0=1, X= 1 => Q1(t+1)= 0 Q0(t+1) = X + Q0(t) Q1(t) Q1=0, Q0=1, X= 1 => Q0(t+1)= 1

Present State Q1 Q0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1

Inputs X 0 1 0 1 0 1 0 1

Next State Q1 Q0 0 0

Outputs Z 0 0 0 0 0 0 0 1
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State Table & Next State Equations

Q1(t+1) = X (Q0(t) Q1(t)) Q0(t+1) = X + Q0(t) Q1(t)
Present State Inputs Next State Outputs Q1 Q0 X Q1 Q0 Z 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1 0 0 0 0 0 0 0 1

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State Table & Characteristic Table

The general JK flip-flop characteristic equation is: Q(t+1) = KQ(t) + JQ(t) We can also determine the next state for each input/current state combination directly from the characteristic table
J 0 0 1 1 K 0 1 0 1 Q(t+1) Q(t) 0 1 Q(t) Operation No change Reset Set Complement

25

State Table & Characteristic Table

With these equations, we can make a table showing J1, K1, J0 and K0 for the different combinations of present state Q1Q0 and input X J1 = X Q0 K1 = X + Q0 J0 = X + Q1 K0 = X

Present State Q1 Q0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1

Inputs X 0 1 0 1 0 1 0 1

J1 0 0 1 0 0 0 1 0

Flip-flop Inputs K1 J0 0 1 1 1 0 1 1 1 0 1 0 1 1 1 1 1

K0 1 0 1 0 1 0 1 0
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State Table & Characteristic Table

J 0 0 1 1 Present State Q1 Q0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Inputs X 0 1 0 1 0 1 0 1 K 0 1 0 1 Q(t+1) Q(t) 0 1 Q(t) FF Inputs K1 J0 0 1 1 1 0 1 1 1 0 1 0 1 1 1 1 1 Next State Q1 Q0

J1 0 0 1 0 0 0 1 0

K0 1 0 1 0 1 0 1 0

27

State Table & Characteristic Table

J 0 0 1 1 Present State Q1 Q0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Inputs X 0 1 0 1 0 1 0 1 K 0 1 0 1 Q(t+1) Q(t) 0 1 Q(t) FF Inputs K1 J0 0 1 1 1 0 1 1 1 0 1 0 1 1 1 1 1 Next State Q1 Q0

J1 0 0 1 0 0 0 1 0

K0 1 0 1 0 1 0 1 0

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A different look
Present State Inputs Next State Outputs Q1 Q0 X Q1 Q0 Z 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1 0 0 0 0 0 0 0 1

Next State Present State Q1 Q0 0 0 1 1 0 1 0 1 0 1 1 0 Input X= 0 0 0 1 0 0 0 0 0 Input X= 1 1 1 1 1

Output Z X= 0 0 0 0 0 X= 1 0 0 0 1
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State diagrams (Mealy model)

We can also represent the state table graphically with a state diagram A diagram corresponding to our example state table is shown below

Present State Inputs Next State Outputs Q1 Q0 X Q1 Q0 Z 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1 0 0 0 0 0 0 0 1

input output 0/0 00 0/0 11 state 1/0 1/1 0/0

1/0 01 1/0 0/0 10

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Sizes of state diagrams

Always check the size of your state diagrams If there are n flip-flops, there should be 2n nodes in the diagram If there are m inputs, then each node will have 2m outgoing arrows In our example, We have two flip-flops, and thus four states or nodes. There is one input, so each node has two outgoing arrows.

0/0 00 0/0 11 1/0 1/1 0/0

1/0 01 1/0 0/0 10

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Another Mealy Circuit

Next-state Logic F State Memory Output Logic G output input EN EN EN D0
D CLK Q Q

excitation Q0

MAX

Q0 Q0 D1
D CLK Q Q

Q1

Q1 Q1

clock signal CLK

current state

Copyright 2000 by Prentice Hall, Inc. Digital Design Principles and Practices, 3/e

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Excitation Equations
Next-state Logic F State Memory Output Logic G output input EN EN EN D0
D CLK Q Q

excitation Q0

MAX

Q0 Q0 D1
D CLK Q Q

Q1

Q1 Q1

clock signal CLK

current state

Copyright 2000 by Prentice Hall, Inc. Digital Design Principles and Practices, 3/e

D0 = EN Q0 + EN Q0 D1 = EN Q1 + EN Q1Q0 + EN Q1 Q0
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Next State/Output Equations

Next-state Logic F State Memory Output Logic G output input EN EN EN D0
D CLK Q Q

excitation Q0

MAX

Q0 Q0 D1
D CLK Q Q

Q1

Q1 Q1

clock signal CLK

current state

Copyright 2000 by Prentice Hall, Inc. Digital Design Principles and Practices, 3/e

Q0(t+1) = D0 = EN Q0 + EN Q0 Q1(t+1) = D1 = EN Q1 + EN Q1 Q0 + EN Q1 Q0 MAX= EN Q1 Q0

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Mealy State Table

Q0(t+1) = D0 = EN Q0 + EN Q0 Q1(t+1) = D1 = EN Q1 + EN Q1 Q0 + EN Q1 Q0 MAX= EN Q1 Q0
Output MAX EN= 0 1 0 1 0 0 0 0 0 EN= 1 0 0 0 1

Next State Present State Q1 Q0 0 0 1 1 0 1 0 1 0 0 1 1 Input EN= 0 0 1 0 1 0 1 1 0 Input EN= 1

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Mealy State Table

Next State Present State Q1 Q0 0 0 1 1 0 1 0 1 0 0 1 1 Input EN= 0 0 1 0 1 0 1 1 0 Input EN= 1 1 0 1 0 Output MAX EN= 0 0 0 0 0 EN= 1 0 0 0 1 State Q1 Q0 0 0 Next State Present State Q1 Q0 A B C D Input EN= 0 A B C D Input EN= 1 B C D A Output MAX EN= 0 0 0 0 0 EN= 1 0 0 0 1
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State Name A B C D

0 1 0 1

1 1

Mealy State Diagram

EN = 0
(MAX = 0)

EN = 0 A EN = 1
(MAX = 0) (MAX = 0)

EN = 1
(MAX = 1)

EN = 1
(MAX = 0)

D EN = 0
(MAX = 0)
Copyright 2000 by Prentice Hall, Inc. Digital Design Principles and Practices, 3/e

EN = 1
(MAX = 0)

C EN = 0
(MAX = 0)

Next State Input EN= 1 B C D A

Present State Q1 Q0 A B C D

Output MAX EN= 0 0 0 0 0 EN= 1 0 0 0 1

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Input EN= 0 A B C D

Moore Circuit
Next-state Logic F State Memory Output Logic G output MAXS input EN EN EN D0
D CLK Q Q

excitation

X
Q0

Q0 Q0 D1
D CLK Q Q

Q1

Remove input connection to output logic => Moore machine

Q1 Q1

clock signal CLK

current state

Copyright 2000 by Prentice Hall, Inc. Digital Design Principles and Practices, 3/e

38

Next State/Output Equations

Next-state Logic F State Memory Output Logic G output MAXS input EN EN EN D0
D CLK Q Q

excitation

X
Q0

Q0 Q0 D1
D CLK Q Q

Q1

Q1 Q1

clock signal CLK

current state

Copyright 2000 by Prentice Hall, Inc. Digital Design Principles and Practices, 3/e

Q0(t+1) = D0 = EN Q0 + EN Q0 Q1(t+1) = D1 = EN Q1 + EN Q1 Q0 + EN Q1 Q0 MAXS= Q1 Q0 MAXS

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Moore State Table

Q0(t+1) = D0 = EN Q0 + EN Q0 Q1(t+1) = D1 = EN Q1 + EN Q1 Q0 + EN Q1 Q0 MAXS= Q1 Q0 MAXS
Next State Present State Q1 Q0 0 0 1 1 0 1 0 1 0 0 1 1 Input EN= 0 0 1 0 1 0 1 1 0 Input EN= 1 1 0 1 0 Output MAXS 0 0 0 1

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Moore State Diagram

EN = 0 A
MAXS=0

EN = 0 EN = 1 B
MAXS=0

EN = 1

EN = 1

D
MAXS=1

EN = 1

C
MAXS=0

EN = 0

EN = 0

Copyright 2000 by Prentice Hall, Inc. Digital Design Principles and Practices, 3/e

Next State Input EN= 0 Input EN= 1 0 1 0 1 0 1 1 0 1 0 1 0

Present State Q1 Q0 0 0 1 1 0 1 0 1 0 0 1 1

Output MAXS 0 0 0 1
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State Transitions
CLOCK EN Q1 Q0 MAX MAXS STATE A A B C C C D D D A A

Copyright 2000 by Prentice Hall, Inc. Digital Design Principles and Practices, 3/e

MAX : Output of the Mealy circuit MAXS : Output of the Moore circuit
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Sequential circuit analysis summary

To analyze sequential circuits, you have to: Find Boolean expressions for the outputs of the circuit and the flip-flop inputs Use these expressions to fill in the output and flip-flop input columns in the state table Finally, use the characteristic equation or characteristic table of the flip-flop to fill in the next state columns. The result of sequential circuit analysis is a state table or a state diagram describing the circuit

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Design of Sequence Detector

44

Sequence Detector
A circuit that detects the occurrence of a particular pattern on its input is referred to as a sequence detector.
Design a circuit that examine a string of 0s and 1s applied to the input X and for any input sequence ending in 101 will produce an output Z=1 coincident with the last 1. The circuit does not reset when a 1 output occur. We assume that the input X can only change between clock pulses
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101 Sequence Detector

X = Z = (time:

0 0 0

0 0 1

1 0 2

1 0 3

0 0 4

1 1 5

1 0 6

0 0 7

0 0 8

1 0 9

0 0 10

1 1 11

0 0 12

1 1 13

0 0 14
46

0 0 15)

Design of 101 Sequence Detector

State Diagram:

47

Design of 101 Sequence Detector

State Diagram:
1/0

48

Design of 101 Sequence Detector

State Diagram (final):

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Design of 101 Sequence Detector

State Table:
Present state S0 S1 S2 Next State X=0 S0 S2 S0 X=1 S1 S1 S1 0 0 0 Present Output X=0 X =1 0 0 1
Assign a unique binary code to each state name (State Assignment)

State Table with State Assignment:

DA DB

A+ B+ AB 00 01 10 X=0 00 10 00 X=1 01 01 01 X=0 0 0 0

Z X =1 0 0 1
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Design of Sequence Detector

Derive Boolean Equations:
AB X 0 1 00 0 0 01 1 0 11 X X A 10 0 0 X 0 1 AB 00 0 1 01 0 1 11 X X A 10 0 1

DA = X.B

DB = X

AB 00 0 0 0 01 0 0 11 X X

A 10 0 1

Z = X.A

Design of Sequence Detector

C1

s(t+1)

Compare with Typical Mealy Machine

x(t) present inputs

next state

State Register

s(t)
present state

C2

z(t)

clock

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Design of Sequence Detector

A Moore Sequence Detector:

101 sequence Detector

X = Z = (time:

0 0 0

0 0 1

1 0 2

1 0 3

0 0 4

1 1 5

1 0 6

0 0 7

0 0 8

1 0 9

0 0 10

1 1 11

0 0 12

1 1 13

0 0 14

0 0 15)
53

Design of a Sequence Detector

54

Design of a Sequence Detector

S0: start S1: got 1 S2: got 10 S3: got 101

55

Design of a Sequence Detector

S0: start S1: got 1 S2: got 10 S3: got 101

56

Design of a Sequence Detector

State Table

Transition Table with State assignment

Prese nt state S0 S1 S2 S3

Next State X=0 S0 S2 S0 S2 X=1 S1 S1 S3 S1

Present Output (Z) 0 0 0 1

A+ B + AB 00 01 11 10 X=0 00 11 00 11 X=1 01 01 10 01 Z 0 0 0 1

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State Diagram Development

To develop a sequence detector state diagram:
1. Construct some sample input and output sequences to make sure that you understand the problem statement. 2. Begin in an initial state in which NONE of the initial portion of the sequence has occurred (typically reset state). 3. Add a state that recognizes that the first symbol has occurred. 4. Add states that recognize each successive symbol occurring. 5. Each time you add an arrow to the state graph, determine it can go to one of the previously defined states or whether a new state must be added 6. The final state represents the input sequence occurrence. 7. Add state transition arcs which specify what happens when a symbol not in the proper sequence has occurred. 8. Check your state graph for completeness and non-redundant arcs. 9. When your state graph is complete, test it by applying the input sequences formulated in part1 and making sure the output sequences are correct
58

Sequential circuit design procedure

Step 1: Make a state table based on the problem statement. The table should show the present states, inputs, next states and outputs. (It may be easier to find a state diagram first, and then convert that to a table) Step 2: Assign binary codes to the states in the state table, if you havent already. If you have n states, your binary codes will have at least log2 n digits, and your circuit will have at least log2 n flip-flops Step 3: For each flip-flop and each row of your state table, find the flip-flop input values that are needed to generate the next state from the present state. You can use flip-flop excitation tables here. Step 4: Find simplified equations for the flip-flop inputs and the outputs. Step 5: Build the circuit!

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Another Example

60

Sequence detector (Mealy)

A sequence detector is a special kind of sequential circuit that looks for a special bit pattern in some input The detector circuit has only one input, X
One bit of input is supplied on every clock cycle This is an easy way to permit arbitrarily long input sequences

There is one output, Z, which is 1 when the desired pattern is found Our example will detect the bit pattern 1001: Inputs: Outputs: 11100110100 100110 00000100000 100100

A sequential circuit is required because the circuit has to remember the inputs from previous clock cycles, in order to determine whether or not a match was found
61

Step 1: Making a state table

The first thing you have to figure out is precisely how the use of state will help you solve the given problem
Make a state table based on the problem statement. The table should show the present states, inputs, next states and outputs Sometimes it is easier to first find a state diagram and then convert that to a table

This is usually the most difficult step. Once you have the state table, the rest of the design procedure is the same for all sequential circuits

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A basic Mealy state diagram

What state do we need for the sequence detector?
We have to remember inputs from previous clock cycles For example, if the previous three inputs were 100 and the current input is 1, then the output should be 1 In general, we will have to remember occurrences of parts of the desired patternin this case, 1, 10, and 100

Well start with a basic state diagram:

A
State A B C D

1/0

0/0

C
Meaning

0/0

None of the desired pattern (1001) has been input yet. Weve already seen the first bit (1) of the desired pattern. Weve already seen the first two bits (10) of the desired pattern. Weve already seen the first three bits (100) of the desired pattern.
63

Overlapping occurrences of the pattern

What happens if were in state D (the last three inputs were 100), and the current input is 1?
The output should be a 1, because weve found the desired pattern But this last 1 could also be the start of another occurrence of the pattern! For example, 1001001 contains two occurrences of 1001 To detect overlapping occurrences of the pattern, the next state should be B.

1/0

0/0

C 1/1

0/0

State A B C D

Meaning None of the desired pattern (1001) has been input yet. Weve already seen the first bit (1) of the desired pattern. Weve already seen the first two bits (10) of the desired pattern. Weve already seen the first three bits (100) of the desired pattern.
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Filling in the other arrows

Two outgoing arrows for each node, to account for the possibilities of X=0 and X=1 The remaining arrows we need are shown in blue. They also allow for the correct detection of overlapping occurrences of 1001.

1/0 A 0/0
State A B C D

0/0 0/0 1/0 1/1

Meaning

1/0

0/0

None of the desired pattern (1001) has been input yet. Weve already seen the first bit (1) of the desired pattern. Weve already seen the first two bits (10) of the desired pattern. Weve already seen the first three bits (100) of the desired pattern.
65

Mealy state diagram & table

1/0 A 0/0
Present State A A B B C C D D Input 0 1 0 1 0 1 0 1 Next State A B C B D B A B

0/0

1/0

0/0 1/0

C 1/1

0/0

Output 0 0 0 0 0 0 0 1

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Step 2: Assigning binary codes to states

We have four states ABCD, so we need at least two flip-flops Q1Q0 The easiest thing to do is represent state A with Q1Q0 = 00, B with 01, C with 10, and D with 11 The state assignment can have a big impact on circuit complexity, but we wont worry about that too much in this class
Present State Q1 Q0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Next State Q1 Q0 0 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1

Present State A A B B C C D D

Input 0 1 0 1 0 1 0 1

Next State A B C B D B A B

Output 0 0 0 0 0 0 0 1

Input X 0 1 0 1 0 1 0 1

Output Z 0 0 0 0 0 0 0 1
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Step 3: Finding flip-flop input values

Next we have to figure out how to actually make the flip-flops change from their present state into the desired next state This depends on what kind of flip-flops you use! Well use two JKs. For each flip-flip Qi, look at its present and next states, and determine what the inputs Ji and Ki should be in order to make that state change.

Present State Q1 Q0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1

Input X 0 1 0 1 0 1 0 1

Next State Q1 Q0 0 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1

Flip flop inputs J1 K1 J0 K0

Output Z 0 0 0 0 0 0 0 1

68

JK excitation table
An excitation table shows what flip-flop inputs are required in order to make a desired state change
Q(t) 0 0 1 1 Q(t+1) 0 1 0 1 J 0 1 x x K x x 1 0 Operation No change/reset Set/complement Reset/complement No change/set

This is the same information thats given in the characteristic table, but presented backwards
J 0 0 1 1 K 0 1 0 1 Q(t+1) Q(t) 0 1 Q(t) Operation No change Reset Set Complement
69

 Use the JK excitation table on the right to find the correct values for each flip-flops inputs, based on its present and next states

Q(t) 0 0 1 1

Q(t+1) 0 1 0 1

J 0 1 x x

K x x 1 0

Present State Q1 Q0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1

Input X 0 1 0 1 0 1 0 1

Next State Q1 Q0 0 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1

Flip flop inputs J1 K1 J0 K0 0 0 1 0 x x x x x x x x 0 1 1 1 0 1 x x 1 1 x x x x 1 0 x x 1 0

Output Z 0 0 0 0 0 0 0 1
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Step 4: Find equations for the FF inputs and output

Now you can make K-maps and find equations for each of the four flip-flop inputs, as well as for the output Z These equations are in terms of the present state and the inputs The advantage of using JK flip-flops is that there are many dont care conditions, which can result in simpler MSP equations
Present State Q1 Q0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Next State Q1 Q0 0 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1

Input X 0 1 0 1 0 1 0 1

Flip flop inputs J1 K1 J0 K0 0 0 1 0 x x x x x x x x 0 1 1 1 0 1 x x 1 1 x x x x 1 0 x x 1 0

Output Z 0 0 0 0 0 0 0 1

71

FF input equations
Present State Q1 Q0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Input X 0 1 0 1 0 1 0 1 Next State Q1 Q0 0 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1 Flip flop inputs J1 K1 J0 K0 0 0 1 0 x x x x x x x x 0 1 1 1 0 1 x x 1 1 x x x x 1 0 x x 1 0 Output Z 0 0 0 0 0 0 0 1

J1 00 X 0 1 0 0

Q1 Q0 01 1 0 11 x x 10 x x X

K1 00 0 1 x x

Q1 Q0 01 x x 11 1 1 10 0 1

J1 = X Q0

K1 = X + Q0

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FF input equations
Present State Q1 Q0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Input X 0 1 0 1 0 1 0 1 Next State Q1 Q0 0 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1 Flip flop inputs J1 K1 J0 K0 0 0 1 0 x x x x x x x x 0 1 1 1 0 1 x x 1 1 x x x x 1 0 x x 1 0 Output Z 0 0 0 0 0 0 0 1

J0 00 X 0 1 0 1

Q1 Q0 01 x x 11 x x 10 1 1 X

K0 00 0 1 x x

Q1 Q0 01 1 0 K0 = X 11 1 0 10 x x

J 0 = X + Q1

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Output equation
Present State Q1 Q0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Input X 0 1 0 1 0 1 0 1 Next State Q1 Q0 0 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1 Flip flop inputs J1 K1 J0 K0 0 0 1 0 x x x x x x x x 0 1 1 1 0 1 x x 1 1 x x x x 1 0 x x 1 0 Output Z 0 0 0 0 0 0 0 1

Z 00 X 0 1

Q1 Q0 01 11 1 Z = X Q1 Q0
74

10

Step 5: Build the circuit

Lastly, we use these simplified equations to build the completed circuit

J1 = X Q0 K1 = X + Q0 J0 = X + Q1 K0 = X Z = Q1Q0X

75

Sequence detector (Moore)

A sequence detector is a special kind of sequential circuit that looks for a special bit pattern in some input The detector circuit has only one input, X
One bit of input is supplied on every clock cycle This is an easy way to permit arbitrarily long input sequences

There is one output, Z, which is 1 when the desired pattern is found Our example will detect the bit pattern 1001: Inputs: Outputs: 11100110100 100110 00000100000 100100

A sequential circuit is required because the circuit has to remember the inputs from previous clock cycles, in order to determine whether or not a match was found
76

Moore state diagram & table

1
A/0

B/0

0 1

C/0

0 0

D/0

E/1

0
Present State A A B B C C D D E E Input 0 1 0 1 0 1 0 1 0 1 Next State A B C B D B A E C B Output 0 0 0 0 0 0 0 0 1 1

Circuit design is left as an exercise !

77

Comparison of Mealy and Moore FSM

Mealy machines have less states outputs are on transitions (n2) rather than states (n) Moore machines are safer to use outputs change at clock edge (always one cycle later) in Mealy machines, input change can cause output change as soon as logic is done a big problem when two machines are interconnected asynchronous feedback may occur if one isnt careful Mealy machines react faster to inputs react in same cycle don't need to wait for clock outputs may be considerably shorter than the clock cycle in Moore machines, more logic may be necessary to decode state into outputs there may be more gate delays after clock edge
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Comparison of Mealy and Moore Mealy machines have less states FSM states (n) outputs are on transitions (n ) rather than
2

Moore machines are safer to use outputs change at clock edge (always one cycle later) in Mealy machines, input change can cause output change as soon as logic is done a big problem when two machines are interconnected asynchronous feedback may occur if one isnt careful Mealy machines react faster to inputs react in same cycle don't need to wait for clock outputs may be considerably shorter than the clock cycle in Moore machines, more logic may be necessary to decode state into outputs there may be more gate delays after clock edge
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Example: Sequence Detector

A sequential circuit has one input (X) and one output (Z). The circuit examines groups of four consecutive inputs and produces an output Z = 1 if the input sequence 0101 or 1001 occurs. The circuit resets after every four inputs. Find a Mealy state graph. A typical input and output sequence is:

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81

State Reduction

82

State Optimization
Equivalent States:
Two states are equivalent if, for each member of the set of inputs,
they give exactly the same output and send the circuit either to the same state or to an equivalent state.

If two states are equivalent, one can be eliminated without effecting the behavior of the FSM.

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State Optimization Algorithm: Row Matching

Two states are equivalent if any of the conditions are true:
1. If two states have the same output AND both transition are to the same next state, 2. If two states have the same output AND both transition are to each other 3. If two states have the same output AND both self-loop,

Combine the equivalent states into a new renamed state. Repeat until no more states are combined.

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Example: Sequence Detector

State Table

85

Example: Sequence Detector

Since states H and I have the same next states and the same outputs, states H and I are equivalent. We can replace I with H.

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Example: Sequence Detector

Reduced State Table

87

Example: Sequence Detector

Reduced State Graph

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Row Matching Example

State Transition Table NS PS x=0 x=1 a a b b c d c a d d e f e a f f g f g a f output x=0 x=1 0 0 0 0 0 0 0 1 0 1 0 1 0 1

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Row Matching Example (cont)

NS PS x=0 x=1 a a b b c d c a d d e f e a f f e f NS PS x=0 x=1 a a b b c d c a d d e d e a d output x=0 x=1 0 0 0 0 0 0 0 1 0 1 0 1 output x=0 x=1 0 0 0 0 0 0 0 1 0 1
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Reduced State Transition Diagram

State Optimization Algorithm

Implication Chart Method

State Table
Prese nt State a b c d e f g h Next State X=0 d f e a c f b c 1 c h d e a b h g Present Output X=0 0 0 1 0 1 1 0 1 91

State Optimization Algorithm

Implication Chart

92

State Optimization Algorithm

Implication Chart
Prese nt State a b c d e f g h Next State X=0 d f e a c f b c 1 c h d e a b h g Present Output X=0 0 0 1 0 1 1 0 1

a|b

iff

d| f

and

c|h

b{c

because the outputs differ

a|d

iff

a|d iff

and

c|e and c|h

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a|g

b|d

State Optimization Algorithm

Implication Chart After First Pass
 Processing order is important

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State Optimization Algorithm

Implication Chart After Second Pass
Present State a b c f g h Next State X=0 a f c f b c 1 c h a b h g Output 0 0 1 1 0 1

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Implication Table Method

The implication table method of determining state equivalence can be summarized as follows:
1. Construct a chart which contains a square for each pair of states. 2. Compare each pair of rows in the state table. If the outputs associated with states i and j are different, place an X in square ij to indicate that i j. If the outputs are the same, place the implied pairs in square i-j. (If the next states of i and j are m and n for some input x, then m-n is an implied pair.) If the outputs and next states are the same (or if i-j only implies itself), place a check () in square i-j to indicate that i j.
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Implication Table Method

3. Go through the table square-by-square. If square i-j contains the implied pair m-n, and square m-n contains an X, then i j, and an X should be placed in square i-j. 4. If any Xs were added in step 3, repeat step 3 until no more Xs are added. 5. For each square i-j which does not contain an X, i j.

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VHDL Modeling of FSM

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A simple Moore machine

F1 is B <= not (A and B) F2 is D <= not C

Output is a function of the state registers. The simplest Moore machine can use only one process

nand

D type FF

not

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A simple Moore machine

architecture moore1_arch of sm is

entity sm is port ( clock: in std_logic; A: in STD_LOGIC; D : out STD_LOGIC); end sm;

signal C: std_logic; -- global, can be seen by -- different processes begin D <= not C; -- F2 = combination logic process(CLK) begin if (CLKvent and CLK =1) then C <= A nand C; --F1 = combination end if; end process; end moore1_arch;
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-- sequential logic

Moore machine using 2 processes

It is more flexible and easier to design F1 is one process and F2 is another process

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Moore machine using 2 processes

architecture moore2_arch of sm is signal B,C: std_logic; begin entity sm is port ( clock: in std_logic; A : in std_logic; D: out std_logic ); end sm; process (C) begin D <= not C; -- F2 = combination logic end process; process(clock) begin if clockvent and clock = 1then C <= A nand C; --F1 = combination logic end if; end process; end moore2_arch;
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-- combinational logic

-- sequential logic

State Representation
General State machine Design steps
Step 1. Identify the states Step 2. Connect the states with certain conditions.

Declare your state types using a new type declaration:

architecture type state-type is (s0, s1, s2, s3); signal ps, ns: state-type; -- holds state information begin process (..) --------------103

Comparison of Mealy and Moore Mealy machines have less states FSM states (n) outputs are on transitions (n ) rather than
2

Moore machines are safer to use outputs change at clock edge (always one cycle later) in Mealy machines, input change can cause output change as soon as logic is done a big problem when two machines are interconnected asynchronous feedback may occur if one isnt careful Mealy machines react faster to inputs react in same cycle don't need to wait for clock outputs may be considerably shorter than the clock cycle in Moore machines, more logic may be necessary to decode state into outputs there may be more gate delays after clock edge
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Moore machine for 11 sequence detection (Non-overlapping)

LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.ALL; USE ieee.numeric_std.ALL; ENTITY SM_11 IS PORT ( clock, reset, X: IN Y : OUT std_logic); END SM_11;

std_logic;

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Moore machine for 11 sequence detection

ARCHITECTURE moore_sm11 OF sm_11 IS TYPE state_type IS (S0, S1, S2) -- enumerated type SIGNAL state: state_type := S0; BEGIN fsm: PROCESS (clock, reset) -- the process describes the BEGIN -- state machine only IF reset = '1' THEN Y <= 0; state <= S0; ELSIF rising_edge(clock) THEN CASE state IS WHEN S0 => Y <= 0 IF X = 1 THEN state <= S1; END IF; WHEN S1 => Y <= 0 IF X = 1 ELSE state END IF; Y <= 1 IF X = 1 ELSE state END IF;

THEN state <= S2; <= S0; THEN state <= S1; <= S0;

WHEN S2

=>

END CASE; END IF; END PROCESS fsm; END moore_sm11;

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Mealy machine for 11 sequence detection (Non-overlapping)

LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.ALL; USE ieee.numeric_std.ALL; ENTITY SM_11 IS PORT ( clock, reset, X: IN Y : OUT std_logic); END SM_11;

std_logic;

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Solution1. Mealy for 11 sequence detection

ARCHITECTURE mealy1_sm11 OF sm_11 IS TYPE state_type IS (S0, S1) -- enumerated type SIGNAL state : state_type := S0; BEGIN fsm: PROCESS (X, clock, reset) BEGIN IF reset = '1' THEN Y <= 0; state <= S0; ELSIF rising_edge(clock) THEN CASE state IS WHEN S0 => IF X = 1 THEN Y <= 0; state <= S1; Else Y <= 0; END IF; WHEN S1 => IF X = 1 THEN Y<= 1; ELSE Y <= 0; END IF; state <= S0;

END CASE; END IF; END PROCESS fsm; END mealy1_sm11;

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Solution2. Mealy for 11 sequence detection

ARCHITECTURE mealy2_sm11 OF sm_11 IS TYPE state_type IS (S0, S1) -- enumerated type SIGNAL pstate, nstate: state_type := S0; BEGIN P1: PROCESS (clock, reset) BEGIN IF reset = '1' THEN Y <= 0; pstate <= S0; ELSIF rising_edge(clock) THEN pstate <= nstate; END IF;

END PROCESS P1;

P2: PROCESS (pstate, X) BEGIN CASE pstate IS WHEN S0 =>

IF X = 1 THEN nstate<= S1; Y <= 1; ELSE Y <= 0 END IF; IF X = 1 THEN nstate<= S0; Y <= 1; ELSE nstate <= S0; Y <= 0; END IF;

WHEN S1

=>

END CASE; END PROCESS P2; END mealy1_sm11;

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Example Design a state machine to implement the function shown below:

RESET (sync) POS

hold
POS clear=1' track=0'

sample

extend

clear='0' track='1'

clear=1' track=1'
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Example: Solution 1 Using an Enumerated Type

LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY ex1 IS PORT ( clock, pos, reset: IN std_logic; clear, track: OUT std_logic); END ex1; ARCHITECTURE archex1 OF ex1 IS TYPE states IS (hold, sample, extend); SIGNAL fsm: states; BEGIN clear <= '0' WHEN fsm = sample ELSE '1'; track <= '1' WHEN (fsm = extend or fsm = sample) ELSE '0';

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Example : Solution 1 (contd.)

sync: PROCESS (clock) BEGIN IF rising_edge(clock) THEN IF reset = '1' THEN -- synchronous reset fsm <= hold; ELSE CASE fsm IS WHEN hold => IF pos = '0' THEN fsm <= sample; ELSE fsm <= hold; END IF; WHEN sample => fsm <= extend; WHEN extend => fsm <= hold; WHEN OTHERS => fsm <= hold; END CASE; END IF; END IF; END PROCESS sync; END archex1;
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Example: Solution 2 Using Constants

LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY ex2 IS PORT ( clock, pos, reset: IN std_logic; clear, track: OUT std_logic); END ex2; ARCHITECTURE archex2 SIGNAL fsm : CONSTANT hold : CONSTANT sample : CONSTANT extend : BEGIN clear <= fsm(1); track <= fsm(0); OF ex2 IS std_logic_vector(1 std_logic_vector(1 std_logic_vector(1 std_logic_vector(1

downto downto downto downto

0); 0) := 10; 0) := 01; 0) := 11;

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Example: Solution 2 (contd.)

sync: PROCESS (clock) BEGIN IF rising_edge(clock) THEN IF reset = '1' THEN -- synchronous reset fsm <= hold; ELSE CASE fsm IS WHEN hold => IF pos = '0' THEN fsm <= sample; ELSE fsm <= hold; END IF; WHEN sample => fsm <= extend; WHEN extend => fsm <= hold; WHEN OTHERS => fsm <= hold; END CASE; END IF; END IF; END PROCESS sync; END archex2;
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FSM

115

FSM Design Style #1

Lower section of the state machine is completely separated from that of the upper section

116

FSM Design Style #1

Design of the lower (sequential) section
process (reset, clock) begin if (reset = 1) then pr_state <= state0; elsif (clockevent and clock = 1) then pr_state <= nx_state; end if; end process;

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FSM Design Style #1

Design of the upper (combinational) section
process (input, pr_state) begin case pr_state is when state0 => if (input = ) then output <= ; nx_state <= state1; else end if; when state1 => if (input = ) then output <= ; nx_state <= state2; else end if; end case; end process;

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FSM Design Style #1 complete template

library ieee; ------------ upper section -------------------use ieee.std_logic_1164.all; process (input, pr_state) ---------------------------------------begin eitity case pr_state is ----------------------------------------when state0 => architecture architecture_abc of def is if (input = ) then type state is (state0, state1, state2, state3,); output <= ; signal pr_state, nx_state : state; nx_state <= state1; begin else ----------lower section -----------end if; when state1 => process (reset, clock) if (input = ) then begin output <= ; if (reset = 1) then nx_state <= state2; pr_state <= state0; else elsif (clockevent and clock = 1) then end if; pr_state <= nx_state; end if; end case; end process; end process; 119 end architecture_abc

FSM Design Style #1

Example:

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FSM Design Style #1

eitity simple_fsm is port (a, b, d, clk, rst : IN bit; x: OUT bit); end simple_fsm; ----------------------------------------architecture arc_fsm of simple_fsm is type state is (stateA, stateB); signal pr_state, nx_state : state; begin ----------lower section -----------process (reset, clock) begin if (rst = 1) then pr_state <= stateA; elsif (clkevent and clk = 1) then pr_state <= nx_state; end if; end process;

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FSM Design Style #1

------------ upper section -------------------process (a, b, d, pr_state) begin case pr_state is when stateA => x <= a; if (d = 1) then nx_state <= stateB; else nx_state <= stateA; end if; when stateB => x <= b; if (d = 1) then nx_state <= stateA; else nx_state <= stateB; end if; end case; end process; end arc_fsm;

122

FSM Design Style #2:

Stored output

123

FSM Design Style #2 complete template

library ieee; ------------ upper section -------------------use ieee.std_logic_1164.all; process (input, pr_state) ---------------------------------------begin eitity case pr_state is ----------------------------------------when state0 => architecture architecture_abc of def is temp <= ; type state is (state0, state1, state2, state3,); if (condition) then signal pr_state, nx_state : state; nx_state <= state1; signal temp: (data_type); . begin end if; ----------lower section -----------when state1 => process (reset, clock) temp <= ; begin if (condition) then if (reset = 1) then nx_state <= state2; pr_state <= state0; elsif (clockevent and clock = 1) then end if; output <= temp; end case; pr_state <= nx_state; end process; end if; end architecture_abc end process; 124

FSM Design Style #2 - Example

eitity simple_fsm is port (a, b, d, clk, rst : IN bit; x: OUT bit); end simple_fsm; ----------------------------------------architecture arc_fsm of simple_fsm is type state is (stateA, stateB); signal pr_state, nx_state : state; signal temp : BIT; begin ----------lower section -----------process (reset, clock) begin if (rst = 1) then pr_state <= stateA; elsif (clkevent and clk = 1) then x <= temp; pr_state <= nx_state; end if; end process;

125

FSM Design Style #2

------------ upper section -------------------process (a, b, d, pr_state) begin case pr_state is when stateA => temp <= a; --- x <= a; if (d = 1) then nx_state <= stateB; else nx_state <= stateA; end if; when stateB => temp <= b; ----x <= b; if (d = 1) then nx_state <= stateA; else nx_state <= stateB; end if; end case; end process; end arc_fsm;

126

State Assignment

127

State Assignments
After the number of states in a state table has been reduced, the next step in realizing the transition table is to assign flipflop states (i.e. binary values) to correspond to the states in the state table. The cost of the logic required to realize a sequential circuit is strongly dependent on the way this state assignment is made.

128

State Assignments
Given a sequential circuit with three states and two flipflops (A and B), there are 4 3 2 = 24 possible state assignments for the three states.

129

Equivalent Circuits

130

131

132

State Assignments
When realizing a three-state sequential circuit with symmetrical flip-flops (i.e. JK or SR), it is only necessary to try three different states to be assured of a minimum cost realization. Similarly, only three different assignments must be tried for four states.

133

State Assignments

134

Guidelines for State Assignment

Trying all nonequivalent state assignments is not practical in most cases. The following guidelines are useful in making assignments which will place 1s (or 0's) together in the nextstate maps: 1. States which have the same next state for a given input should be given adjacent assignments. 2. States which are the next states of the same state should be given adjacent assignments. 3. States which have the same output for a given input should be given adjacent assignments.
135

Example: Selecting an Assignment

1. 2. 3.

States which have the same next state for a given input should be given adjacent assignments. States which are the next states of the same state should be given adjacent assignments. States which have the same output for a given input should be given adjacent assignments.
136

Example: Selecting an Assignment

Based on the State Assignment Guidelines:

137

Next State Maps

138

Next State Maps

139

One-Hot State Assignment

Sometimes reducing the number of flip-flops used is not as important as reducing the logic feeding into the flip-flops. Using a one-hot state assignment may help accomplish this. The one-hot assignment uses one flip-flop for each state, so a state machine with N states requires N flip-flops. Exactly one of the flip-flops is set to one in each state.

140

141

Partial State Graph

142

143

Example: State Assignments

For a four-state FSM, three possible state assignments are:
State S0 S1 S2 S3 # of FF Binary 00 01 10 11 2 Gray-code 00 01 11 10 2 One-hot 0001 0010 0100 1000 4
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Reference
"Fundamentals of Logic Design", 5th Edition, Charles H. Roth, Jr Chapters 13,14,15,17,18,19,20

145