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Verilog Chapter 5

Chapter 5 discusses gate level modeling in Verilog, detailing the four levels of abstraction for hardware description: behavioral, dataflow, gate, and switch levels. It covers the types of gates supported in Verilog, including basic logic gates and their instantiation, as well as the concept of gate delays and their specifications. The chapter also provides examples of a multiplexer and a full adder, illustrating how to implement these components in Verilog.
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0% found this document useful (0 votes)
7 views38 pages

Verilog Chapter 5

Chapter 5 discusses gate level modeling in Verilog, detailing the four levels of abstraction for hardware description: behavioral, dataflow, gate, and switch levels. It covers the types of gates supported in Verilog, including basic logic gates and their instantiation, as well as the concept of gate delays and their specifications. The chapter also provides examples of a multiplexer and a full adder, illustrating how to implement these components in Verilog.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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Chapter -5

Gate Level Modelling


Till now we have discussed about the

• Design methodologies
• Basic conventions and constructs
• Modules and Port interfaces

Now we will get into modeling actual hardware


circuits in verilog.
There are four levels of abstraction to describe the hardware :-

• Behavioral or Algorithmic level


• Dataflow level
• Gate level
• Switch level

• Behavioral level is the highest level of abstraction and switch


level is the lowest level of abstraction.

• Mostly the digital design is done at gate level or the higher levels
of abstraction.

• At gate level, the circuit is described in terms of gates. For eg:


nand , and, or, xnor & bufif1 etc.
Gate Types
• Verilog supports basic logic gates as predefined primitives.
• Two classes of Basic Gates: and/or gates and buf/not gates
• And/Or gates have one scalar output and multiple inputs.
• The o/p of a gate is evaluated as soon as one of the i/p changes.
• And/Or gates that are available in verilog are shown below.
and or xor nand nor xnor
Gate instantiation of And/Or gates
wire OUT, IN1, IN2;
and a1(OUT, IN1, IN2);
nand na1(OUT, IN1, IN2);
or or1(OUT, IN1, IN2);
nor nor1(OUT, IN1, IN2);
xor x1(OUT, IN1, IN2);
xnor nx1(OUT, IN1, IN2);

nand na1_3inp(OUT, IN1, IN2, IN3);


// gate instantiation without instance name
and (OUT, IN1, IN2); // legal gate instantiation
Truth tables
Buf/Not Gates
• These have one scalar input and one or more scalar outputs
• Two basic Buf/Not gate primitives that are provided in Verilog
are
buf not
// basic gate instantiations
buf b1(OUT1, IN);
not n1(OUT1, IN);
// More than two outputs
buf b1_2out(OUT1, OUT2, IN);
// gate instantiation without instance name
not (OUT1, IN); // legal gate instantiation
Bufif/ Notif
• Gates with an extra control signal on buf and not gates are also
available.
bufif1 notif1 bufif0 notif0
• These gate propagate only if their control signal is asserted.
• They propagate (z) if their control signal is deasserted.
Truth Table of bufif and notif
• Such gates are used when a signal is to be driven only when
the control signal is asserted.
• Such a situation is applicable when the multiple drivers drive
the signal.
• //Instantiation of bufif gates
bufif1 b1 (out, in, ctrl);
bufif0 b0 (out, in, ctrl);
//Instantiation of notif gates
notif1 n1 (out, in, ctrl);
notif0 n0 (out, in, ctrl);
Example 5-4 Simple Array of Primitive Instances
wire [7:0] OUT, IN1, IN2;
// basic gate instantiations
nand n_gate[7:0](OUT, IN1, IN2);

// This is equivalent to the following 8 instantiations


nand n_gate0(OUT[0], IN1[0], IN2[0]);
nand n_gate1(OUT[1], IN1[1], IN2[1]);
nand n_gate2(OUT[2], IN1[2], IN2[2]);
nand n_gate3(OUT[3], IN1[3], IN2[3]);
nand n_gate4(OUT[4], IN1[4], IN2[4]);
nand n_gate5(OUT[5], IN1[5], IN2[5]);
nand n_gate6(OUT[6], IN1[6], IN2[6]);
nand n_gate7(OUT[7], IN1[7], IN2[7]);
Example of 4x1 multiplexer using gate level
Verilog description of multiplexer
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);
// Port declarations
output out; input i0, i1, i2, i3; input s1, s0;
// Internal wire declarations
wire s1n, s0n; wire y0, y1, y2, y3;
// Gate instantiations and Create s1n and s0n signals
not (s1n, s1); not (s0n, s0);
// 3-input and gates instantiated
and (y0, i0, s1n, s0n);
and (y1, i1, s1n, s0);
and (y2, i2, s1, s0n);
and (y3, i3, s1, s0);
// 4-input or gate instantiated
or (out, y0, y1, y2, y3);
endmodule
Stimulus for multiplexer
module stimulus;
reg IN0, IN1, IN2, IN3; reg S1, S0; wire OUTPUT;
mux4_to_1 mymux(OUTPUT, IN0, IN1, IN2, IN3, S1, S0);
initial
begin
IN0 = 1; IN1 = 0; IN2 = 1; IN3 = 0;
#1 $display("IN0= %b, IN1= %b, IN2= %b, IN3= %b\n",IN0,IN1,IN2,IN3);
S1 = 0; S0 = 0;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);
S1 = 0; S0 = 1;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);
S1 = 1; S0 = 0;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);
S1 = 1; S0 = 1;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);
end
endmodule
Output of simulation

IN0= 1, IN1= 0, IN2= 1, IN3= 0

S1 = 0, S0 = 0, OUTPUT = 1

S1 = 0, S0 = 1, OUTPUT = 0

S1 = 1, S0 = 0, OUTPUT = 1

S1 = 1, S0 = 1, OUTPUT = 0
1-bit Full Adder
1-bit Full Adder
• module fulladd(sum, c_out, a, b, c_in);
• output sum, c_out;
• input a, b, c_in;
• wire s1, c1, s2;
• xor (s1, a, b);
• and (c1, a, b);
• xor (sum, s1, c_in);
• and (s2, s1, c_in);
• xor (c_out, s2, c1);
• endmodule
4-bit Full adder
• module fulladd4(sum, c_out, a, b, c_in);
• output [3:0] sum; output c_out; input[3:0] a, b;
input c_in;
• wire c1, c2, c3;
• fulladd fa0(sum[0], c1, a[0], b[0], c_in);
• fulladd fa1(sum[1], c2, a[1], b[1], c1);
• fulladd fa2(sum[2], c3, a[2], b[2], c2);
• fulladd fa3(sum[3], c_out, a[3], b[3], c3);
• endmodule
module stimulus;
reg [3:0] A, B; reg C_IN; wire [3:0] SUM; wire C_OUT;
fulladd4 FA1_4(SUM, C_OUT, A, B, C_IN);
initial
begin
$monitor($time," A= %b, B=%b, C_IN= %b, --- C_OUT= %b, SUM=
%b\n", A, B, C_IN, C_OUT, SUM);
end
initial begin
A = 4'd0; B = 4'd0; C_IN = 1'b0;
#5 A = 4'd3; B = 4'd4;
#5 A = 4'd2; B = 4'd5;
#5 A = 4'd9; B = 4'd9;
#5 A = 4'd10; B = 4'd15;
#5 A = 4'd10; B = 4'd5; C_IN = 1'b1;
end
endmodule
• The output of the simulation is shown below

• 0 A= 0000, B=0000, C_IN= 0, --- C_OUT= 0, SUM= 0000


• 5 A= 0011, B=0100, C_IN= 0, --- C_OUT= 0, SUM= 0111
• 10 A= 0010, B=0101, C_IN= 0, --- C_OUT= 0, SUM= 0111
• 15 A= 1001, B=1001, C_IN= 0, --- C_OUT= 1, SUM= 0010
• 20 A= 1010, B=1111, C_IN= 0, --- C_OUT= 1, SUM= 1001
• 25 A= 1010, B=0101, C_IN= 1,, C_OUT= 1, SUM= 0000
Gate Delays
• In real circuits , logic gates have delays associated with them.
• Gate delays allows the Verilog user to specify delays through
the logic circuits.
• There are 3 types of delays from the input to the output of a
primitive gate.
a. Rise delay
b. Fall delay
c. Turn-off delay
Rise delay

The rise delay is assciated with a gate output transition to a 1 from any other value .
Fall delay

Fall delay is associated with a gate output transition to a 0 from


other level
Turn off delay
Turn off delay is associated with a gate output transition to the high
impedance value(z) from another level.

If the value changes to (x) then the minimum of three delays is


considered.

If no delay value is specified then by default the value of delay is


zero.
• Three types of delay specifications are allowed.
• If only one delay is specified, this value is used for all
transitions.
• If two delays are specified, they refer to the rise and fall delay
values.
• The turn-off delay is the minimum of the two delays. If all
three delays are specified, they refer to rise, fall, and turn-off
delay values.
• If no delays are specified, the default value is zero.
Types of delay specification
Examples of delay specification are shown below.

and #(5) a1(out, i1, i2); //Delay of 5 for all transitions


and #(4,6) a2(out, i1, i2); // Rise = 4, Fall = 6
bufif0 #(3,4,5) b1 (out, in, control); // Rise = 3, Fall = 4,
Turn-off = 5
Min, Typ and Max values
• Verilog provides an additional level of control for
each type of delay mentioned before.
• Min, Typ and Max values are specified for each
delay value which we discussed before.
• Any one value can be chosen at the start of the
simulation.
• Min, Typ and Max values are used to model devices
whose delays vary within a minimum and maximum
range because of the fabrication process variations.
• Min value: The min value is the minimum
delay value that the designer expects the gate
to have.

• Typ value: The typ value is the typical delay


value that the designer expects the gate to
have.

• Max value: The max value is the maximum


delay value that the designer expects the gate
to have.
• These values can be chosen at verilog run time.
• Method of choosing these value may vary for
different simulators.
• For Verilog-XL , the values are chosen by
specifying options +maxdelays, +typdelays
and +mindelays at run time.
• If no value is specified then typical delay value
is the default .
• The designer can experiment with delay values
without modifying the design.
Delay example
out = (a.b) + c
Verilog description
Waveforms for Delay simulation
• The outputs (E) and (OUT) are initially unknown.
• At time 10, after (A),(B) and (C) all transition to 1,
(OUT) transitions to 1 after a delay of 4 time units
and (E) changes value to 1 after 5 time units.
• At time 20, (B) and (c) transition to 0. (E) changes
value to 0 after 5 time units and (OUT) transitions
to 0, 4 time units after (E) changes.
• The timing for each transition in the above
waveform corresponds to the gate delays shown in
module D.
Thank You

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