RedHawk™ VCD Based

Dynamic Analysis

Version V5.2-AL-RH131-07FEB2016

1 ©2016 ANSYS Inc.

 Agenda

• VCD Introduction

• RedHawk VCD Based Static Flow

• Cycle Selection Basics

• RedHawk VCD Based Dynamic Flow

2 ©2016 ANSYS Inc.

 What is VCD ?
• VCD or “Value change dump file”
― Contains the waveforms for different signal nets in the design
― Created from 3rd party verification tools
― Format is ASCII
― Waveform can be viewed in 3rd party tools

• Alternative format is FSDB (Fast signal Database)

― Format is binary
― Much lesser file size compared to VCD

• RedHawk supports both VCD and FSDB formats

3 ©2016 ANSYS Inc.

 Types of VCD
Gate Level VCD
• Contains toggle information of all the gates in the design
• True time VCD
– SDF (Standard Delay Format) is used in verification
– VCD generated from timing annotated functional/scan simulation
– RedHawk will use switching scenario from VCD
– RedHawk will use instance switching time from VCD
• Non-true time VCD
– SDF not used in verification
– VCD generated assuming unit-delay gate level functional/scan simulation
– RedHawk will use switching scenario from VCD
– RedHawk will use switching time from STA file

• Do I need STA file for true-time based analysis ?

– Yes, you will still require this for slew information

4 ©2016 ANSYS Inc.

 Types of VCD (Cont’d)
RTL VCD
• Contains only activity at state points
• Registers/latches/memory/primary input
• RedHawk does logic propagation to derive the activity information
for internal logic
• Mapping RTL VCD to gate netlist name
– RedHawk can use auto-name mapping and generate the mapping on its
own
– Mapping file can be generated from formal verification tools
• User control available for logic propagation through constraint file

• RTL VCD is useful during early stages of the design cycle

• Gate level simulation happens later in the design cycle
• RTL VCD file size will be much smaller compared to Gate level VCD
• RTL VCD is always non true time
• RedHawk will use switching scenario from VCD
• RedHawk will use switching time from STA file

5 ©2016 ANSYS Inc.

 VCD Based Power Calculation

6 ©2016 ANSYS Inc.

 RedHawk VCD Based Dynamic
Voltage Drop Analysis
No Statistical Vectorless
VCD? Vectorless Scan
Yes

RTL VCD Gate-level VCD

True-Time Non True-Time

Note : Fast Signal Database (FSDB ) can also be used in place of VCD

7 ©2016 ANSYS Inc.

 VCD_FILE Specification in GSR
• VCD_FILE Specification
VCD_FILE
{
<top_level name> <absolute or relative path to VCD or FSDB file>
FILE_TYPE <VCD | FSDB | RTL_VCD | RTL_FSDB>
FRONT_PATH <redundant path string that does not match the DEF
path> SUBSTITUTE_PATH <the substitute path string from above>
START_TIME <analysis start_time in ps; optional; default=0>
TRUE_TIME [0|1]
MAPPING <mapping_file_name>
}

DYNAMIC_SIMULATION_TIME <frame_width_sec>

• Power Calculation will be done between:

• START_TIME and (START_TIME + DYNAMIC_SIMULATION_TIME)

8 ©2016 ANSYS Inc.

 Hierarchical VCD_FILE Specification in GSR
• BLOCK_VCD_FILE Specification
BLOCK_VCD_FILE
{
VCD_FILE {
<hier_name/inst_name> <absolute or relative path to VCD or FSDB
file> FILE_TYPE <VCD | FSDB | RTL_VCD | RTL_FSDB>
FRONT_PATH <redundant path string that does not match the DEF
path> SUBSTITUTE_PATH <the substitute path string from above>
START_TIME <analysis start_time in ps; optional; default=0>
TRUE_TIME [0|1]
MAPPING <mapping_file_name>
}
VCD_FILE {
<hier_name2/inst_name2> <absolute or relative path to VCD/FSDB
file> FILE_TYPE <VCD | FSDB | RTL_VCD | RTL_FSDB>
……
}
}

9 ©2016 ANSYS Inc.

 Power Calculation Options
POWER_ANALYSIS_MODE [averaged | averaged_fast]
• This allows user to set the accuracy level of VCD based power
calculation. Setting the above keyword to “averaged” improves the
accuracy of power calculation by taking into account state
dependent leakage and internal power values from the .lib.
• Default: averaged_fast.

10 ©2016 ANSYS Inc.

 Cycle Select in VCD Based
Dynamic Analysis

11 ©2016 ANSYS Inc.

 Cycle Select In VCD Based Dynamic Analysis
• Challenges in VCD dynamic simulation
– Dynamic analysis is true transient simulation, not average analysis
like static Setup
– VCDs can contain thousands of cycle. We cannot perform dynamic
analysis for the complete VCD;
– Need to intelligently filter out critical cycles in the VCD
Cycle selection
• Using Cycle selection to identify the critical cycles in the VCD
• Two methods to filter the critical cycles
– WORST_POWER_ CYCLE
– WORST_DPDT_CYCLE PwrCalc
• Once the critical cycle is selected, RedHawk does dynamic
simulation for this cycle
– Pre-simulation cycles (from VCD) will be attached to the Extraction
selected cycle
• Both True-time and Non-true time VCDs can be used in
cycle selection Dynamic
• Both RTL and Gate level VCDs can be used for cycle Simulation
selection
• The keyword SELECT_RANGE activates cycle selection.
– The VCD time between the values provided in SELECT_RANGE will be
12 considered for cycle selection.
©2016 ANSYS Inc.
 Cycle Select In VCD Based Analysis Flow
Input data

Design Synopsys
STA SPEF TECH
(DEF/LEF) LIB

VCD Cycle selection

Cycles of interest

WORST_POWER_CYCLE WORST_DPDT_CYCLE

VCD_FILE { VCD_FILE {
SELECT_RANGE <start_time> <end_time> SELECT_RANGE <start_time> <end_time>
SELECT_TYPE WORST_POWER_CYCLE SELECT_TYPE WORST_DPDT_CYCLE
} }

13 ©2016 ANSYS Inc.

 WORST_POWER_CYCLE

GSR and Command file examples

GSR:
VCD_FILE {
TCL:
GENERIC GENERIC.vcd
FILE_TYPE VCD import gsr GENERIC.gsr
FRONT_PATH "GENERIC/" setup design
SUBSTITUTE_PATH "" setup analysis_mode dynamic
SELECT_RANGE <start_time> <end_time> perform pwrcalc
SELECT_TYPE WORST_POWER_CYCLE perform extraction –power –
TRUE_TIME 1 ground -c
} perform analysis -vcd

• DYNAMIC_SIMULATION_TIME decides the window width of each

cycle
• User can set "SELECT_RANGE -1 -1" to allow RedHawk to
do a cycle selection for the entire VCD range

14 ©2016 ANSYS Inc.

 WORST_POWER_CYCLE (Cont’d)

• RedHawk does cycle by cycle power calculation

adsRpt/worst_power_cycle.rpt

• Selects cycle having highest power for dynamic simulation

15 ©2016 ANSYS Inc.

 WORST_DPDT_CYCLE
GSR and Command file examples

GSR:
TCL:
VCD_FILE {
GENERIC GENERIC.vcd import gsr GENERIC.gsr
FILE_TYPE VCD setup design
FRONT_PATH "GENERIC/" setup analysis_mode dynamic
SUBSTITUTE_PATH "" perform pwrcalc
SELECT_RANGE <start_time> <end_time> perform extraction –power –ground -c
SELECT_TYPE WORST_DPDT_CYCLE setup package
TRUE_TIME 1 perform analysis -vcd
}

• DYNAMIC_SIMULATION_TIME decides the window width of each cycle.

• User can set “SELECT_RANGE -1 -1” to allow RedHawk to do a

cycle selection for the entire VCD range.

16 ©2016 ANSYS Inc.

 Accuracy In Cycle Selection Based Power
Calculation
• Accuracy can be selected using the below keyword:
– POWER_CYCLE_SELECT_MODE [0| 1| 2]
• 0: default value, time usage: low, memory usage: low, accuracy: low
• 1: time usage: low, memory usage: high, accuracy: middle
• 2: time usage: high, memory usage: high, accuracy: high

17 ©2016 ANSYS Inc.

 Result Exploration and
Debugging
adsRpt/redhawk.log

18 ©2016 ANSYS Inc.

 Debug Tips in VCD Analysis
• Check whether the VCD is imported correctly in RedHawk
– adsRpt/vcd_missing_signal_nets
– adsRpt/vcd_missing_clock_nets

• If close to 100% of nets are reported as missing in the VCD check the
“FRONT_PATH” keyword in GSR
– Make sure that there is a trailing slash in the string specification
• FRONT_PATH "test_bench1/GENERIC/”
– Open the VCD in text editor and verify the scope statements
• Scope statements define the hierarchy in VCD
• If the input is FSDB, you can convert it into VCD using 3rd party conversion utilities and check
– Load the VCD/FSDB in a 3rd party waveform viewer to browse the hierarchy

• Use switching histograms to verify the VCD switching

– For scan shift VCDs, make sure that ~100% flops and clocks are switching
– For MBIST VCDs, make sure that ~100% memories are switching

• For true-time VCD analysis, make sure that VCD is timing back annotated

19 ©2016 ANSYS Inc.

 Lab Exercise : VCD Analysis
• Steps to be followed # Import data
– cd GENERIC_tutorial/vcd_run import gsr GENERIC.gsr
setup design
– cd worst_power setup analysis_mode
dynamic
– Review GSR and command file # Calculate power
– redHawk –f run_dynamic.tcl perform pwrcalc

# Power grid extraction

perform extraction -power -ground -c

# Lumped resistance (in Ohms)

User control file (GSR): # for package, wirebond and pads
# Default values are all 0, i.e no off-chip impact
setup package -power -r 0.005 -l 2.5 -c 5
VCD_FILE { setup package -ground -r 0.005 -l 2.5 -c 5
GENERIC ../../design_data/vcd setup wirebond -power -r 0.01 -l 2.2 -c 1.42
/GENERIC.vcd setup wirebond -ground -r 0.05 -l 1.7 -c 0.2
FILE_TYPE VCD setup pad -power -r 0.001
FRONT_PATH setup pad -ground -r 0.001
"test_bench1/GENERIC/" TRUE_TIME
1 # Dynamic IR analysis
SELECT_RANGE -1 -1
perform analysis –vcd
SELECT_TYPE WORST_POWER_CYCLE
}
explore design

20 ©2016 ANSYS Inc.

 Result Analysis

• Result analysis procedure is same as normal dynamic

analysis
– Refer to Lecture : “Moving to RedHawk Dynamic”

21 ©2016 ANSYS Inc.

 Advanced Usage Options

22 ©2016 ANSYS Inc.

 RTL-VCD Auto Name Mapping

• To perform RTL-to-gate mapping of net names . Default ON in RedHawk

• GSR and Command file examples

GSR: TCL:
VCD_FILE {
import gsr GENERIC.gsr
GENERIC GENERIC.vcd
setup design
FILE_TYPE RTL_VCD
setup analysis_mode
FRONT_PATH "GENERIC/"
dynamic
SUBSTITUTE_PATH "“
perform pwrcalc
START_TIME <start_time_in_ps>
perform extraction –power –ground -c
TRUE_TIME 0
setup package
}
perform analysis -vcd

• To turn off RTL-VCD Auto Name Mapping enable ‘RTL_NAME_MAPPING 0’

in GSR

23 ©2016 ANSYS Inc.

 RTL-VCD Propagation Modes
• Event Propagation Based Power Calculation (default):

VCD_FILE {
GENERIC GENERIC.vcd No special settings
FILE_TYPE RTL_VCD needed – Event
GSR file START_TIME Propagation is the
<start_time_in_ps> default mode when
…….. RTL VCD is specified.
}

• State Propagation Based Power Calculation :

• Keyword
VCD_FILE { ‘VCD_DRIVEN 1‘
GENERIC GENERIC.vcd enables State
FILE_TYPE RTL_VCD Propagation.
GSR file START_TIME
<start_time_in_ps> • Note: END_TIME
. is honored here.
. VCD is analyzed
VCD_DRIVEN 1 from START_TIME
} to END_TIME.

24 ©2016 ANSYS Inc.

 How to Get Help!
• Apache Online Customer Support Center
– http://support.apache-da.com
– Email: [email protected]

25 ©2016 ANSYS Inc.

 Thank You!

26 ©2016 ANSYS Inc.