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Microprocessor Systems-Part 1

The document outlines the syllabus for a course on Microprocessor Systems, covering topics such as the 8085 microprocessor architecture, assembly language programming, memory and peripheral interfacing, and the Intel 8086 and Freescale ColdFire processors. It details course outcomes for students, emphasizing skills in program design, hardware interfacing, and performance optimization. The pedagogy includes flipped classes, live discussions, quizzes, assignments, lab work, and simulation-based projects.

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0% found this document useful (0 votes)
6 views147 pages

Microprocessor Systems-Part 1

The document outlines the syllabus for a course on Microprocessor Systems, covering topics such as the 8085 microprocessor architecture, assembly language programming, memory and peripheral interfacing, and the Intel 8086 and Freescale ColdFire processors. It details course outcomes for students, emphasizing skills in program design, hardware interfacing, and performance optimization. The pedagogy includes flipped classes, live discussions, quizzes, assignments, lab work, and simulation-based projects.

Uploaded by

studyexam015
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Microprocessor Systems

ECL 3060 (3-0-0) = 3 Credits

Microprocessor Systems Lab


ECP 3060 (0-0-2) = 1 Credit
D R. S U ME E T G U PTA
A S S O C I AT E PR O F E S S O R
S CH O O L O F E L E C T R O NI C S & CO MMU NI C AT I O N E NG I NE E R I NG
S H R I MATA VA I S H NO DE V I U NI V E R S I T Y , KAT RA
Syllabus
Introduction to 8085 Microprocessor: Functional block diagram – Registers, ALU, Bus
systems, Memory & Instruction cycles Timing diagrams, Address Decoding techniques,
Addressing modes, Instruction Set, Assembly Language Programming, Interrupts-Types &
handling, ISR, Stack architecture

Memory and Peripheral interfacing: Basic interfacing concepts - Memory space partitioning
- Buffering of buses – Timing constraints - Memory control signals - Read and write cycles,
Interfacing RAM, ROM, 8255PPI, Interfacing applications using 8255. Need for direct memory
access - DMA transfer types

Intel 16 bit Microprocessor: Register organization of 8086 – Architecture - Physical Memory


organization - I/O addressing capability, Addressing modes of 8086 - Instruction set of 8086 -
Assembler directives and operators, Assembly language programming, Interrupt Architecture

Freescale 32 bit ColdFire Processor:-Introduction to ColdFire Core, Comparison with 8085 &
8086 Architecture, Introduction to MCF5223X Microprocessor Architecture & Functional Blocks
Course Outcome
CO No. Course Outcome

CO1 The student will be able to analyze, specify, design, write and test assembly language
programs for 8085 microprocessor and basic programs to run on 8086 microprocessor
based systems.

CO2 The student will be able to understand the various aspects of the internal architecture of
the 8085 microprocessor and will be able to design hardware circuits to interface the 8085
microprocessor to various ICs like RAM, ROM, 8255 etc.

CO3 The student will be able to calculate the worst-case execution time of programs or parts of
programs, and to design and build, or to modify, software to maximize its run time memory
or execution-time behavior.

CO4 The student will be able to compare the architecture design for 8085, 8086 & Coldfiree 32
bit microprocessor
Pedagogy
1. Flipped Class – Pre-loaded Video Lectures which you will view before coming
to the live class
2. Live Classes - For discussions and doubt clearing
3. Quizzes – Multiple Choice Types
4. Assignments - Zero plagiarism policy – Copying will get you a zero
5. Lab Work – To the extent possible
6. Project – Simulation Based
Microprocessors System

74LS374
8085 Microprocessor

Consists of:
1. CPU + ALU + Registers
2. 8 bit Data Bus (Multiplexed)
3. 16 bit Address Bus (8 bit Multiplexed with Data Bus)
4. 5 Sources of hardware Interrupt
5. 02 Serial Data Lines
6. DMA Interface
7. Control lines for interfacing
8085 Microprocessor

Fetch-Decode-Execute Cycle

A microprocessor, till the time it is ON and is not in HALT mode, will continuously follow the
Fetch Decode Execute Cycle
1. Fetch the Instruction from the ROM into the Instruction Register (IR)
2. Decode the Instruction i.e. understand what the instruction is
3. Execute the Instruction i.e. perform all micro-steps needed to complete the task
mentioned by the instruction
Then go back to Step No. 1 and repeat the process infinite number of times
8085 Microprocessor – Pin Description
Pins Direction Description
X1, X2 IN This is where the Crystal is connected to the Oscillator circuit inside 8085 where Clock is
generated. Typically 6MHz crystal is connected and internal clock is 3MHz (Crystal frequency/2)
CLK OUT OUT The Clock signal generated inside the 8085 is also available as an output at this pin and can be
connected to external device, if needed
Vcc, GND IN Voltage Supply and Ground. As IC is TTL, Supply is Typically 5V
AD7-AD0 IN & OUT Multiplexed Address and Data Bus (LSB of Address Bus A7-A0 is time multiplexed with Data Bus
D7-D0
A8-A15 OUT MSB of Address Bus
ALE OUT Used to demultiplex the time multiplexed Address and Data Bus AD7-AD0 to A7-A0 & D7-D0
RD, WR, IO/M OUT Signal used for Reading a byte or Writing a byte from/to external Input/Output Device or
Memory
RESETIN, IN, OUT Applying a 0 on RESETIN RESETS the 8085 and simultaneously generates a 1 on RESET OUT which
RESET OUT could be used to REST other external devices if needed.
HOLD, HLDA IN, OUT Hold & Hold Acknowledge (Active Low) are used for Direct Memory access (DMA)
8085 Microprocessor – Pin Description
Pins Direction Description
S0,S1 OUT These Status signals indicate the status of thee internal circuit of the 8085
READY IN Slow external devices use this signal to convey to 8085 that they are ready for the next operation
TRAP, RST 7.5, IN, OUT First 05 are the Interrupt Signals while INTA is the Interrupt Acknowledgement Signal generated
RST 6.5, RST by 8085 in response to receipt of INTR interrupt
5.5, INTR,
INTA
SID, SOD IN, OUT These are used to Serially receive or transmit 01 byte of data, bit by bit
8085 Microprocessor – Memory Read Cycle
8085 Microprocessor – Memory Write Cycle
e.g. STA 2022H
In T1:
Address available on A8-A15 & A7-A0
ALE Pulse
Io/M =0
WR=1

In T2:
A7-A0 becomes tri-state
ALE=0
Put Data on Data Bus D7-D0
Io/M=0
WR=0

In T3:
After some time WR=1
Remove Data from D7-D0, Bus is tri-state
Complete the Cycle
8085 Microprocessor – De-multiplexing of AD7-AD0
8085 Microprocessor – De-multiplexing of AD7-AD0
8085 Microprocessor – RAM Interface
A14
A12 /WR /WR

A1 A13
A9 A5
A8 A3
A7 A11
A6 /RD
/RD
A4 A10
A2 /CS
A0 D4
D0 D3
D1 D7
D5 D2
D6

/RD /WR
8085 Microprocessor – Address Space
Address Space means the total unique addresses that can be generated by the 8085 microprocessors on its 16 address
lines. Since 8085 has 16 address lines thus a total of 2^16 = 65536 addresses

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0


0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000H (Starting Address)

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFFH (Last Address)

2^4 = 16
2^7 =128
2^8 = 256
2^9 =512
2^10 =1024 (1KB)
2^11 =2048 (2KB)
2^12 =4096 (4KB)
2^13 =8192 (8KB)
2^14 =16384 (16KB)
2^15 =32768 (32KB)
2^16 =65536 (64KB)
8085 Microprocessor – Address Space

Q1. 01 ROM IC of 32KB and 01 RAM IC of 32KB are to be interfaced with the 8085. Assuming the starting address of
ROM IC is 0000H what will be address map for the ROM and RAM?

Q2. 02 ROM ICs of 8KB each and 01 RAM IC of 16KB is interfaced to 8085. Assuming the starting address of first ROM
IC is 0000H what will be address map for the ROMs and RAM?

Q3. 01 ROM IC of 2KB and on ROM IC of 8KB and 02 RAM IC of 8KB each is interfaced to 8085. Assuming the starting
address of first ROM IC is 0000H what will be address map for the ROMs and RAM?

Q4. IO/M is used by microprocessor to indicate if its doing a Rad or write operation with Input/Output Device or
Memory. This signal along with /RD and /WR signal is used to perform the Memory Rad/Write or IO Read/write
operations. Design a circuit which accepts these three signals as input and generates four outputs namely /IOR,
/IOW, /MEMR,/MEMW8085.
8085 Microprocessor – Memory Interface
0000H
A0-A14
/CS1 A15
D0-D7

/RD

7FFFH

A15
8000H

A0-A14
/CS2
D0-D7
/RD
/WR
FFFFH
8085 Microprocessor – Memory Interface
8KB ROM
A0-A12 0000H
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D0-D7
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 /RD 1FFFH
0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
/CS1
0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
8KB ROM
0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A0-A12 2000H
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 D0-D7
/RD 3FFFH
A15 /CS1 /CS2
A14
A13 16KB RAM
4000H
A15 /CS2 A0-A13
A14 /CS3
A13 D0-D7
/RD
A15 /WR
/CS3
A14
A13 7FFFH
8085 Microprocessor – Memory Interface 2KB ROM
0000H
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A0-A10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D0-D7
0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
/RD 07FFH
0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 /CS1
0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8KB ROM
A0-A12 2000H
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 D0-D7
/RD 3FFFH
0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
/CS2
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A15 /CS1 8KB RAM
A14 4000H
A15 /CS2 A0-A12
A13
A14 /CS3
A13 D0-D7
/RD
A15 /CS3 /WR
A14 5FFFH
A13 8KB RAM
6000H
A15 /CS4 A0-A12
A14 /CS4
D0-D7
A13 /RD
/WR
7FFFH
74138 3 to 8 Decoder
8085 Microprocessor – Memory Interface
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
8KB ROM
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 A0-A12 0000H

0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 D0-D7
0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 /RD 1FFFH
/CS1
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8KB ROM
A0-A12 2000H
A13 D0-D7
A14
/CS1 /RD 3FFFH
/CS2 /CS2
A15
GND 16KB RAM
/CS3 4000H
A0-A13
/CS3
D0-D7
Vcc /RD
/WR

7FFFH
Instruction Set of 8085
Microprocessor

Instruction Format: Instruction consists of 01 Opcode (Operation Code) and either 0, 1 or 2 operands

E.g. LDA 2000H LDA (3AH) 20H 00H


OpCode means the code of the operation to be done e.g. Add, Subtract, Increment, decrement, move etc.
Operands means the values over which the operations are to be done
The opcodes are fixed and were designed when the 8085 microprocessor was designed. We can’t change it.
The operands can be either given directly in the instruction, in registers, in memory locations
E.g. LDA 2000H LDA (3AH) 20H 00H

We already know that reading one byte of memory takes 3 T States. This combination of 3 T states is
called a Machine Cycle represented by M
The Instructions are stored in the ROM and need to be fetched from the ROM to the Microprocessor
Fetching the Opcode (1 Byte) takes 3 T states and 01 additional T state is taken to decode the Opcode
Therefore, the Machine cycle for Opcode Fetch is of 4 T-States and not 3 T states
This is called M1 Machine cycle – Machine cycle for fetching the OpCode
So with this logic how many machine cycles will be required to fetch the complete instruction LDA
2000H? The answer is 3 Machine cycles M1, M2 & M3
How many total t states to fetch this instructions?
4 T states in M1, 3 T States in M2 & 3 T states in M3 – Total of 10 T States to fetch this instruction
Instruction Fetch Cycle of 8085 – Part –A – Op-code
Fetch
M1 Machine Cycle – Opcode Fetch & Decode

T1 – 8085 puts the address of ROM


memory location from where the Op
code is to be fetched on higher and
lower address bus

T2 – 8085 enables the /RD signal so that


the opcode can be read from ROM
memory location

T3 – The opcode is fetched and stored in


Instruction Register (IR) in the 8085

T4 – Decoding of the Opcode takes


place so that 8085 knows what is to be
done next
Instruction Fetch Cycle of 8085 – Part –B – Operand
Fetch
M2 Machine Cycle – Operand Fetch M3 Machine Cycle – Operand Fetch

Operand Fetch is Memory Read Cycle

All Instructions may not require


operand fetch

In case of instructions where there is


no operand fetch required, only M1
cycle will occur for fetch.

Operand Operand In some cases, there will b 01 operand


or 02 operands

Accordingly either M2 will run or M2


and M3 both will run
Example of Program written in Assembly
Language of 8085
Question: Write a program in Assembly language of 8085 microprocessor to add the two bytes
stored at memory location 2000H & 2001H and store the sum in 2002H.

LDA 2000H //Read number from memory location 2000H and copy into Accumulator (A)
MOV B,A //Copy the contents of Register A (Source) into Register B (Destination)
LDA 2001H //Read number from memory location 2001H and copy into Accumulator (A)
ADD B //Perform the addition of the two bytes stored in A and B and store sum in A
STA 2002H //Store the value in A into memory location 2002H
HLT //Stop
Registers in 8085
Flag register in 8085

1. CY Flag – Carry Flag - This flag becomes 1 when addition or subtraction of two bytes results in
generation of carry or borrow else it is 0. This carry or borrow is reflected in the Carry flag.
2. P Flag - Parity Flag - If after any arithmetic or logical operation the result has even
parity, an even number of 1 bits, the parity flag becomes set i.e. 1, otherwise it
becomes reset i.e. 0.
3. Z Flag – Zero Flag - If after any arithmetic or logical operation the result is zero,
the Zero flag is set i.e. 1, otherwise it is reset i.e. 0.
4. S Flag – Sign Flag – The S flag corresponds to the Most Significant Bit of the
Accumulator after arithmetic or logical operation is carried out. If signed number
representation is being used then a 1 would indicate that the number is negative and
0 would indicate that number is positive
5. AC Flag – Auxiliary Carry Flag - If after any arithmetic operation there is a carry
from the lower nibble to the upper nibble then AC Flag is set i.e. becomes 1 else AC
flag is reset i.e. 0
Instruction Set of 8085
Microprocessor

There are a total of 246 instructions in the instructions set of 8085 microprocessor and these can be
categorized as:
1. Data Transfer Instructions – These instructions can be used to transfer data between Register to
register, Register to memory, memory to register . e.g. LDA, STA, MOV, MVI. Execution of these
instructions have not effect on the flags.
2. Arithmetic & Logical Instructions - These instructions can be used to perform arithmetic and logical
operations. Result of the operation, in most cases is stored in Accumulator. e.g. ADD, SUB, INR, DCR,
AND, XOR, ORA etc. Execution of most of these instructions have effect on the flags.
3. Branching Instructions – These instructions can be used to change the sequence of flow of the
program. This change in flow can be conditional or unconditional. e.g. JMP, JZ, JNZ, CALL, RET
4. Control Instructions - These instruction control the basic functioning of the microprocessor. e.g.
HLT, NOP, SIM, RIM, DI, EI
Data Transfer Instructions

MOV destination, source


MVI destination, 8 bit number
LDA 16 bit address
STA 16 bit address
LHLD 16 bit address
SHLD 16 bit address
LXI 16 bit number
LDAX Register pair which contains address
STAX Register pair which contains address
XCHG Exchange
Data Transfer Instructions (MOV)
MOV destination, source
Both destination or source can be registers
One can be Register and another can be Memory represented by M
E.g. MOV A,B Copy contents of B in A A B
MOV C,D Copy contents of D in C C D
MOV B,E Copy contents of E in B B E
MOV A,M Copy contents of memory location whose address is in HL into A
A [HL]
Register H Register L
2000H 5AH
20H 03H
2001H 2FH
If Register H has the value 20H & L has the value 03H then the Register pair HL has
the value 2003H 2002H 39H
2003H 1FH
Now on execution of MOV A,M the data stored in 2003H will be copied to A i.e.
2004H 22H
after execution of instruction value in A will be 1FH which was stored at 2003H
Data Transfer Instructions (MOV)
MOV destination, source

Size of Instruction : 01 Byte


T-States Required for fetching & execution:
◦ For Register to Register transfer only 01 Machine cycle with 04 T states
◦ For Register to Memory transfer and vice versa: 02 Machine Cycles
M1- 04 T- states,
M2 -03 T-States
Instruction Fetch & Execute Cycle for MOV rd,rs
M1 Machine Cycle – Opcode Fetch, Decode & Execute

T1 – 8085 puts the address of ROM memory


location from where the Op code is to be fetched
on higher and lower address bus

T2 – 8085 enables the /RD signal so that the


opcode can be read from ROM memory location

T3 – The opcode is fetched and stored in


Instruction Register (IR) in the 8085

T4 – Decoding of the Opcode takes place so that


8085 knows what is to be done next. As both
source and destination register are inside the
8085 so execution of instruction also is
completed in T4
Instruction Fetch Cycle for MOV rd,M
M1 Machine Cycle – Opcode Fetch

T1 – 8085 puts the address of ROM memory


location from where the Op code is to be fetched
on higher and lower address bus

T2 – 8085 enables the /RD signal so that the


opcode can be read from ROM memory location

T3 – The opcode is fetched and stored in


Instruction Register (IR) in the 8085

T4 – Decoding of the Opcode takes place so that


8085 knows what is to be done next.
Instruction Execute Cycle for MOV rd,M
M2 Machine Cycle –

This is memory Read cycle

The content of memory location, whose


H address is in HL, is copied into the Register
mentioned in the instruction.

L Data
Data Transfer Instructions (MVI reg/M, 8 bit value)
MVI destination, source
Destination can be a register of M (Memory)
E.g. MVI A,2FH Move immediately into A the value 2FH A 2FH
MVI C, 77H Move immediately into C the value 77H C C 77H
MVI M, 8CH Move immediately into the Memory location the number 8CH. location
is Memory the one whose address is in [HL] 8CH

Register H Register L
2000H 5AH
20H 03H
2001H 2FH
If Register H has the value 20H & L has the value 03H then the Register pair HL has
the value 2003H 2002H 39H
2003H 1FH / 8CH
Now on execution of MVI, 8CH, the data at memory location 2003H will be
2004H 22H
replaced with 8CH
Data Transfer Instructions (MVI)
MVI reg/M, 8 bit number

Size of Instruction : 02 Byte


T-States Required for fetching & execution:
◦ For storing data into Register: 02 Machine cycle
M1- 04 T- states – Fetch op code
M2 -03 T-States – Fetch operand and store in register

◦ For storing data in Memory: 03 Machine Cycles


M1- 04 T- states – Fetch op code
M2 -03 T-States – Fetch operand
M3 – 03 T States – Memory write cycle
Instruction Fetch & Execute Cycle for MVI rd, 8 bit number
M1 Machine Cycle – Opcode Fetch, Decode

T1 – 8085 puts the address of ROM memory


location from where the Op code is to be fetched
on higher and lower address bus

T2 – 8085 enables the /RD signal so that the


opcode can be read from ROM memory location

T3 – The opcode is fetched and stored in


Instruction Register (IR) in the 8085

T4 – Decoding of the Opcode takes place so that


8085 knows what is to be done next. Looking at
opcode, 8085 knows this instruction’s size is 02
bytes and thus initiates operand fetch cycle M2
Instruction Fetch & Execute Cycle for MVI rd, 8 bit number
M2 Machine Cycle – Operand Fetch

Operand Fetch is Memory Read Cycle

Since the operand i.. 8 bit value is to be


stored in Register only, execution
happens in T3 of M2

Operand
Instruction Fetch & Execute Cycle for MVI M, 8 bit number
M1 Machine Cycle – Opcode Fetch, Decode

T1 – 8085 puts the address of ROM memory


location from where the Op code is to be fetched
on higher and lower address bus

T2 – 8085 enables the /RD signal so that the


opcode can be read from ROM memory location

T3 – The opcode is fetched and stored in


Instruction Register (IR) in the 8085

T4 – Decoding of the Opcode takes place so that


8085 knows what is to be done next. Looking at
opcode, 8085 knows this instruction’s size is 02
bytes and thus initiates operand fetch cycle M2
Instruction Fetch & Execute Cycle for MVI rd, 8 bit number
M2 Machine Cycle – Operand Fetch M3 Machine Cycle – Memory Write

Operand L 8 bit no.


Comparison between MOV & MVI
MOV Rd, Rs – M1 – 04 T MVI Rd, 8 BIT VALUE – M1,M2 – 07 T
MOV Rd, M – M1, M2 – 07 T MVI M, 8 BIT VALUE – M1,M2, M3 – 10 T
MOV M, Rs – M1, M2 – 07 T
Size: 01 Byte – Opcode Size: 02 Bytes - Opcode, 8 bit number
Instruction Meaning Size T States
MVI H, 21H H <- 21H 2 7
MVI L, 20H L <- 20H 2 7
MVI M, 67H [HL] <- 67H 2 10
MOV B,M B <- 67H 1 7
MVI L, 24H L <- 24H 2 7
MOV M,B [HL] <- 67H 1 7
INX H HL < - HL + 1 1 6
MOV M, B [HL] <- 67H 1 7
Data Transfer Instructions (LDA 16 bit address)
LDA 16 bit address
Load into Accumulator (A), the data from memory location whose 16 bit address is given in instruction
E.g. LDA 2100H Move into A the data from memory location 2100H A [2100H]
LDA 374FH Move into A the data from memory location 374FH A [374FH]
Data Transfer Instructions (LDA)
LDA 16 BIT ADDRESS e.g. LDA 2100H

Size of Instruction : 3 Byte


T-States Required for fetching & execution:
M1- 04 T- states – Fetch op code
M2 -03 T-States – Fetch operand 1
M3 – 03 T States – Fetch operand 2
M4 - 03 T States – Read number
from memory location and store in A
Instruction Fetch & Execute Cycle for LDA 16 bit address
M1 Machine Cycle – Opcode Fetch, Decode

T1 – 8085 puts the address of ROM memory


location from where the Op code is to be fetched
on higher and lower address bus

T2 – 8085 enables the /RD signal so that the


opcode can be read from ROM memory location

T3 – The opcode is fetched and stored in


Instruction Register (IR) in the 8085

T4 – Decoding of the Opcode takes place so that


8085 knows what is to be done next. Looking at
opcode, 8085 knows this instruction’s size is 03
bytes and thus initiates operand fetch cycle M2
& M3
Instruction Fetch & Execute Cycle for LDA 16 bit address
M2 Machine Cycle – Operand Fetch M3 Machine Cycle – Operand Fetch M4 Machine Cycle – Memory Read

Operand Operand 8 bit no.


Data Transfer Instructions (STA 16 bit address)
STA 16 bit address
Store the contents of the Accumulator (A), into memory location whose 16 bit address is given in
instruction
E.g. STA 2100H Move into A the data from memory location 2100H A [2100H]
STA 374FH Move into A the data from memory location 374FH A [374FH]
Data Transfer Instructions (STA 16 bit address)
STA 16 BIT ADDRESS e.g. STA 2100H

Size of Instruction : 3 Byte


T-States Required for fetching & execution:
M1- 04 T- states – Fetch op code
M2 -03 T-States – Fetch operand 1
M3 – 03 T States – Fetch operand 2
M4 - 03 T States – Store number in
A
into memory location
Instruction Fetch & Execute Cycle for STA 16 bit address
M1 Machine Cycle – Opcode Fetch, Decode

T1 – 8085 puts the address of ROM memory


location from where the Op code is to be fetched
on higher and lower address bus

T2 – 8085 enables the /RD signal so that the


opcode can be read from ROM memory location

T3 – The opcode is fetched and stored in


Instruction Register (IR) in the 8085

T4 – Decoding of the Opcode takes place so that


8085 knows what is to be done next. Looking at
opcode, 8085 knows this instruction’s size is 03
bytes and thus initiates operand fetch cycle M2
& M3
Instruction Fetch & Execute Cycle for STA 16 bit address
M2 Machine Cycle – Operand Fetch M3 Machine Cycle – Operand Fetch M4 Machine Cycle – Memory Write

Operand Operand A
Data Transfer Instructions (LXI Rp, 16 bit number)
LXI Rp, 16 bit number
Load into Register Pair (BC, DE, HL,SP) the 16 bit number given in the instruction itself
E.g. LXI H, 2100H Copy 21H into H, 00H into L H 21H L 00H
LXI B, 2420H Copy 24H into B, 20H into C B 21H C 00H
LXI D, 4142H Copy 41H into D, 42H into E D 21H E 00H
LXI SP, 3042H Copy 3042h in 16 bit Register SP SP 3042H
Data Transfer Instructions (LXI Rp, 16 bit number)
LXI Rp, 16 bit number e.g. LXI H, 2100H

Size of Instruction : 3 Byte


T-States Required for fetching & execution:
M1- 04 T- states – Fetch op code
M2 -03 T-States – Fetch operand 1
M3 – 03 T States – Fetch operand 2
The two operands fetched are stored in the Register pair directly without any
additional T-state
Instruction Fetch & Execute Cycle for LXI Rp, 16 bit number
M1 Machine Cycle – Opcode Fetch, Decode

T1 – 8085 puts the address of ROM memory


location from where the Op code is to be fetched
on higher and lower address bus

T2 – 8085 enables the /RD signal so that the


opcode can be read from ROM memory location

T3 – The opcode is fetched and stored in


Instruction Register (IR) in the 8085

T4 – Decoding of the Opcode takes place so that


8085 knows what is to be done next. Looking at
opcode, 8085 knows this instruction’s size is 03
bytes and thus initiates operand fetch cycle M2
& M3
Instruction Fetch & Execute Cycle for LXI Rp, 16 bit number
M2 Machine Cycle – Operand Fetch M3 Machine Cycle – Operand Fetch

The operands are stored in the Register


pair as they are fetched, thus no
additional T state is required for
execution of instruction

Operand Operand
Write a program in 8085 Assembly language to read
two bytes of data from 2000H & 2001H and
exchange the two bytes
LDA 2000H A < - [2000H] 3 13 LXI H, 2000H HL < - 2000H 3 10
MOV B,A B <- A 1 4 MOV B,M B <- [2000H] 1 7

LDA 2001H A <- [2001H] 3 13 LDA 2001H A <- [2001H] 3 13

STA 2000H [2000H] <- A 3 13 STA 2000H [2000H] <- A 3 13

MOV A,B A <- B 1 4 MOV A,B A <- B 1 4


STA 2001H [2001H] <- A 3 13
STA 2001H [2001H] <- A 3 13 ◦ 14 60
◦ 14 60
A
5AH 2000H 77H

B
2001H 5AH
5AH
Arithmetic Instructions
ADD R/M A <- A + R/M
ADC R/M + Carry A <- A + R/M + Carry
ADI 8 bit number A <- A + 8 bit number
ACI 8 bit number + Carry A <- A + 8 bit number + Carry
SUB R/M A <- A - R/M
SBB R/M – Carry A <- A - R/M - Carry
SUI 8 bit number A <- A - 8 bit number
SBI 8 bit number – Carry A <- A - 8 bit number – Carry
INR R/M R <-R+1 M<- M+1
DCR R/M R <-R-1 M<- M-1
INX Rp Rp <- Rp + 1
DCX Rp Rp <- Rp - 1
Arithmetic Instructions (ADD R/M)
ADD R/M (ALL FLAGS ARE AFFECTED)
Add the 8 bit number in A with the 8 bit number in other register R or memory

E.g. ADD B Add number in A with number in B and store answer in A A+B
ADD E Add number in A with number in B and store answer in A A+E
ADD M Add number in A with number in M and store answer in A A + [HL]

Register H Register L Register A


2000H 5AH
20H 03H 0FH
2001H 2FH
If Register H has the value 20H & L has the value 03H and A has the value 0FH then 2002H 39H
execution of ADD M will result in 0FH + 1FH and the answer 2EH will be stored in A
2003H 1FH
2004H 22H
Arithmetic Instructions (ADD R/M)
ADD R/M

Size of Instruction : 01 Byte


T-States Required for fetching & execution:
◦ If other number is in Register then only 01 Machine cycle with 04 T states
◦ For other number is in Memory then : 02 Machine Cycles
M1- 04 T- states – Fetch op code
M2 -03 T-States - Fetch operand and perform
addition in same Machine cycle
Instruction Fetch & Execute Cycle for ADD R
M1 Machine Cycle – Opcode Fetch, Decode & Execute

T1 – 8085 puts the address of ROM memory


location from where the Op code is to be fetched
on higher and lower address bus

T2 – 8085 enables the /RD signal so that the


opcode can be read from ROM memory location

T3 – The opcode is fetched and stored in


Instruction Register (IR) in the 8085

T4 – Decoding of the Opcode takes place so that


8085 knows what is to be done next. As both
source and destination register are inside the
8085 so execution of instruction also is
completed in T4
Instruction Fetch Cycle for ADD M
M1 Machine Cycle – Opcode Fetch

T1 – 8085 puts the address of ROM memory


location from where the Op code is to be fetched
on higher and lower address bus

T2 – 8085 enables the /RD signal so that the


opcode can be read from ROM memory location

T3 – The opcode is fetched and stored in


Instruction Register (IR) in the 8085

T4 – Decoding of the Opcode takes place so that


8085 knows what is to be done next. Looking at
opcode 8085 understands that the operand is to
be fetched and that requires an additional
memory read cycle.
Instruction Execute Cycle for ADD M
M2 Machine Cycle –

This is memory Read cycle

The content of memory location, whose


H address is in HL, are brough into a temporary
register and then addition is performed and
answer stored in A.
L Data
Flag register in 8085

1. CY Flag – Carry Flag - This flag becomes 1 when addition or subtraction of two bytes results in
generation of carry or borrow else it is 0. This carry or borrow is reflected in the Carry flag.
2. P Flag - Parity Flag - If after any arithmetic or logical operation the result has even
parity, an even number of 1 bits, the parity flag becomes set i.e. 1, otherwise it
becomes reset i.e. 0.
3. Z Flag – Zero Flag - If after any arithmetic or logical operation the result is zero,
the Zero flag is set i.e. 1, otherwise it is reset i.e. 0.
4. S Flag – Sign Flag – The S flag corresponds to the Most Significant Bit of the
Accumulator after arithmetic or logical operation is carried out. If signed number
representation is being used then a 1 would indicate that the number is negative and
0 would indicate that number is positive
5. AC Flag – Auxiliary Carry Flag - If after any arithmetic operation there is a carry
from the lower nibble to the upper nibble then AC Flag is set i.e. becomes 1 else AC
flag is reset i.e. 0
Let’s see how Flags are affected by ADD instruction
MVI A,09H A= 5DH CY= 0 AC= 0 S= 0 Z= 0 P= 0
MVI B, 54H
ADD B 5D = 0101 1101

MVI A, 9FH A= 11H CY= 1 AC= 1 S= 0 Z= 0 P= 1


MVI E, 72H 11H = 0001 0001
ADD E 9FH
72H
1

MVI A, 9FH A= 2DH CY= 0 AC= 0 S= 0 Z= 0 P= 1


MVI B, 72H 2D = 0010 1101
SUB B
LXIH 2020H H=20H L= 20H A= F8H CY= 1 AC= 0 S= 1 Z= 0 P= 1
MVI A, 7FH F8 = 1111 1000
MVI M, 87H
SUB M
Arithmetic Instructions (ADC R/M)
ADC R/M (ALL FLAGS ARE AFFECTED)
Add the 8 bit number in A with the 8 bit number in other register R or memory + Carry Flag

E.g. ADC B Add number in A with number in B and store answer in A A + B + Carry Flag
ADC E Add number in A with number in B and store answer in A A + E + Carry Flag
ADC M Add number in A with number in M and store answer in A A + [HL] + Carry Flag

Register H Register L Register A


2000H 5AH
20H 03H 0FH
2001H 2FH
If Register H has the value 20H & L has the value 03H and A has the value 0FH and 2002H 39H
value of Carry Flag is 1 then execution of ADD M will result in 0FH + 1FH and the
2003H 1FH
answer 2FH will be stored in A
2004H 22H
Arithmetic Instructions (ADC R/M)
ADC R/M

Size of Instruction : 01 Byte


T-States Required for fetching & execution:
◦ If other number is in Register then only 01 Machine cycle with 04 T states
◦ For other number is in Memory then : 02 Machine Cycles
M1- 04 T- states – Fetch op code
M2 -03 T-States - Fetch operand and perform
addition in same Machine cycle
Instruction Fetch & Execute Cycle for ADC R
M1 Machine Cycle – Opcode Fetch, Decode & Execute

T1 – 8085 puts the address of ROM memory


location from where the Op code is to be fetched
on higher and lower address bus

T2 – 8085 enables the /RD signal so that the


opcode can be read from ROM memory location

T3 – The opcode is fetched and stored in


Instruction Register (IR) in the 8085

T4 – Decoding of the Opcode takes place so that


8085 knows what is to be done next. As both
source and destination register are inside the
8085 so execution of instruction also is
completed in T4
Instruction Fetch Cycle for ADC M
M1 Machine Cycle – Opcode Fetch

T1 – 8085 puts the address of ROM memory


location from where the Op code is to be fetched
on higher and lower address bus

T2 – 8085 enables the /RD signal so that the


opcode can be read from ROM memory location

T3 – The opcode is fetched and stored in


Instruction Register (IR) in the 8085

T4 – Decoding of the Opcode takes place so that


8085 knows what is to be done next. Looking at
opcode 8085 understands that the operand is to
be fetched and that requires an additional
memory read cycle.
Instruction Execute Cycle for ADD M
M2 Machine Cycle –

This is memory Read cycle

The content of memory location, whose


H address is in HL, are brough into a temporary
register and then addition is performed and
answer stored in A.
L Data
Arithmetic Instructions (ADI 8 bit number)
ADI 8 bit number (ALL FLAGS ARE AFFECTED)
Add the 8 bit number in A with the 8 bit number given in the instructions

E.g. ADI 20H Add number in A with the number 20H A A + 20H

Register A Register A
0FH 2FH

If Register A has the value 0FH, then after execution of the instruction ADI 20H, the new value in A shall be 2FH.
Arithmetic Instructions (ADI 8 bit number)
ADI 8 bit number

Size of Instruction : 02 Byte


T-States Required for fetching & execution:
◦ 02 Machine Cycles
◦ M1- 04 T- states – Fetch op code
M2 -03 T-States - Fetch operand (8 bit number) and perform addition in same Machine
cycle
Instruction Fetch & Execute Cycle for ADI 8 bit number
M1 Machine Cycle – Opcode Fetch

T1 – 8085 puts the address of ROM memory


location from where the Op code is to be fetched
on higher and lower address bus

T2 – 8085 enables the /RD signal so that the


opcode can be read from ROM memory location

T3 – The opcode is fetched and stored in


Instruction Register (IR) in the 8085

T4 – Decoding of the Opcode takes place so that


8085 knows what is to be done next. Looking at
opcode 8085 understands that the operand is to
be fetched and that requires an additional
memory read cycle.
Instruction Execute Cycle for ADI 8 bit number
M2 Machine Cycle – Operand Fetch &
Execution

This is memory Read cycle

Operand (8 bit number is fetched and


addition is performed in this Machine Cycle
itself

Data
Arithmetic Instructions (ACI 8 bit number)
ACI 8 bit number (ALL FLAGS ARE AFFECTED)
Add the 8 bit number in A with the 8 bit number given in the instruction + Carry Flag

E.g. ACI 20H Add number in A with the number 20H A A + 20H + Carry Flag

Register A CY Register A CY
0FH 1 After execution of ACI 20H 30H 0

If Register A has the value 0FH and if carry flag is 1, then after execution of the instruction ACI 20H, the new value
in A shall be 30H and new value in Carry Flag shall be 0.
Arithmetic Instructions (ACI 8 bit number)
ACI 8 bit number

Size of Instruction : 02 Byte


T-States Required for fetching & execution:
◦ 02 Machine Cycles
◦ M1- 04 T- states – Fetch op code
M2 -03 T-States - Fetch operand (8 bit number) and perform addition in same Machine
cycle
Instruction Fetch & Execute Cycle for ACI 8 bit number
M1 Machine Cycle – Opcode Fetch

T1 – 8085 puts the address of ROM memory


location from where the Op code is to be fetched
on higher and lower address bus

T2 – 8085 enables the /RD signal so that the


opcode can be read from ROM memory location

T3 – The opcode is fetched and stored in


Instruction Register (IR) in the 8085

T4 – Decoding of the Opcode takes place so that


8085 knows what is to be done next. Looking at
opcode 8085 understands that the operand is to
be fetched and that requires an additional
memory read cycle.
Instruction Execute Cycle for ACI 8 bit number
M2 Machine Cycle – Operand Fetch &
Execution

This is memory Read cycle

Operand (8 bit number is fetched and


addition is performed in this Machine Cycle
itself

Data
Arithmetic Instructions (SUB R/M)
SUB R/M (ALL FLAGS ARE AFFECTED)
Subtract from the 8 bit number in A, the 8 bit number in other register R or memory

E.g. SUB B Subtract from the number in A, number in B and store answer in A A-B
SUB E Subtract from the number in A, number in E and store answer in A A-E
SUB M subtract from the number in A, number in M and store answer in A A - [HL]

Register H Register L Register A


2000H 5AH
20H 03H 0FH
2001H 2FH
If Register H has the value 20H & L has the value 03H and A has the value 0FH then 2002H 39H
execution of SUB M will result in 0FH - 07H and the answer 08H will be stored in A
2003H 07H
2004H 22H
Arithmetic Instructions (SUB R/M)
SUB R/M

Size of Instruction : 01 Byte


T-States Required for fetching & execution:
◦ If other number is in Register then only 01 Machine cycle with 04 T states
◦ For other number is in Memory then : 02 Machine Cycles
M1- 04 T- states – Fetch op code
M2 -03 T-States - Fetch operand and perform
addition in same Machine cycle
Instruction Fetch & Execute Cycle for SUB R
M1 Machine Cycle – Opcode Fetch, Decode & Execute

T1 – 8085 puts the address of ROM memory


location from where the Op code is to be fetched
on higher and lower address bus

T2 – 8085 enables the /RD signal so that the


opcode can be read from ROM memory location

T3 – The opcode is fetched and stored in


Instruction Register (IR) in the 8085

T4 – Decoding of the Opcode takes place so that


8085 knows what is to be done next. As both
source and destination register are inside the
8085 so execution of instruction also is
completed in T4
Instruction Fetch Cycle for SUB M
M1 Machine Cycle – Opcode Fetch

T1 – 8085 puts the address of ROM memory


location from where the Op code is to be fetched
on higher and lower address bus

T2 – 8085 enables the /RD signal so that the


opcode can be read from ROM memory location

T3 – The opcode is fetched and stored in


Instruction Register (IR) in the 8085

T4 – Decoding of the Opcode takes place so that


8085 knows what is to be done next. Looking at
opcode 8085 understands that the operand is to
be fetched and that requires an additional
memory read cycle.
Instruction Execute Cycle for SUB M
M2 Machine Cycle –

This is memory Read cycle

The content of memory location, whose


H address is in HL, are brough into a temporary
register and then subtraction is performed
and answer stored in A.
L Data
Arithmetic Instructions (SBB R/M)
SBB R/M (ALL FLAGS ARE AFFECTED)
Subtract from the 8 bit number in A, the 8 bit number in other register R or memory - Carry Flag

E.g. SBB B Subtract from number in A, number in B and store answer in A A - B - Carry Flag
SBB E Subtract from number in A, number in E and store answer in A A - E - Carry Flag
SBB M Subtract from number in A, number in M and store answer in A A - [HL] - Carry Flag

Register H Register L Register A


2000H 5AH
20H 03H 0FH
2001H 2FH
If Register H has the value 20H & L has the value 03H and A has the value 0FH and 2002H 39H
value of Carry Flag is 1 then execution of SBB M will result in 0FH - 03H -1 and the
2003H 03H
answer 0BH will be stored in A
2004H 22H
Arithmetic Instructions (SBB R/M)
ADC R/M

Size of Instruction : 01 Byte


T-States Required for fetching & execution:
◦ If other number is in Register then only 01 Machine cycle with 04 T states
◦ For other number is in Memory then : 02 Machine Cycles
M1- 04 T- states – Fetch op code
M2 -03 T-States - Fetch operand and perform
addition in same Machine cycle
Instruction Fetch & Execute Cycle for SBB R
M1 Machine Cycle – Opcode Fetch, Decode & Execute

T1 – 8085 puts the address of ROM memory


location from where the Op code is to be fetched
on higher and lower address bus

T2 – 8085 enables the /RD signal so that the


opcode can be read from ROM memory location

T3 – The opcode is fetched and stored in


Instruction Register (IR) in the 8085

T4 – Decoding of the Opcode takes place so that


8085 knows what is to be done next. As both
source and destination register are inside the
8085 so execution of instruction also is
completed in T4
Instruction Fetch Cycle for SBB M
M1 Machine Cycle – Opcode Fetch

T1 – 8085 puts the address of ROM memory


location from where the Op code is to be fetched
on higher and lower address bus

T2 – 8085 enables the /RD signal so that the


opcode can be read from ROM memory location

T3 – The opcode is fetched and stored in


Instruction Register (IR) in the 8085

T4 – Decoding of the Opcode takes place so that


8085 knows what is to be done next. Looking at
opcode 8085 understands that the operand is to
be fetched and that requires an additional
memory read cycle.
Instruction Execute Cycle for SBB M
M2 Machine Cycle –

This is memory Read cycle

The content of memory location, whose


H address is in HL, are brough into a temporary
register and then subtraction is performed
and answer stored in A.
L Data
Arithmetic Instructions (SUI 8 bit number)
SUI 8 bit number (ALL FLAGS ARE AFFECTED)
Subtract from the 8 bit number in A, the 8 bit number given in the instructions

E.g. SUI 20H Subtract from number in A, the number 20H A A - 20H

Register A Register A
7FH 5FH

If Register A has the value 7FH, then after execution of the instruction SUI 20H, the new value in A shall be 5FH.
Arithmetic Instructions (SUI 8 bit number)
SUI 8 bit number

Size of Instruction : 02 Byte


T-States Required for fetching & execution:
◦ 02 Machine Cycles
◦ M1- 04 T- states – Fetch op code
M2 -03 T-States - Fetch operand (8 bit number) and perform addition in same Machine
cycle
Instruction Fetch & Execute Cycle for SUI 8 bit number
M1 Machine Cycle – Opcode Fetch

T1 – 8085 puts the address of ROM memory


location from where the Op code is to be fetched
on higher and lower address bus

T2 – 8085 enables the /RD signal so that the


opcode can be read from ROM memory location

T3 – The opcode is fetched and stored in


Instruction Register (IR) in the 8085

T4 – Decoding of the Opcode takes place so that


8085 knows what is to be done next. Looking at
opcode 8085 understands that the operand is to
be fetched and that requires an additional
memory read cycle.
Instruction Execute Cycle for SUI 8 bit number
M2 Machine Cycle – Operand Fetch &
Execution

This is memory Read cycle

Operand (8 bit number is fetched and


subtraction is performed in this Machine
Cycle itself

Data
Arithmetic Instructions (SCI 8 bit number)
SCI 8 bit number (ALL FLAGS ARE AFFECTED)
Subtract from the 8 bit number in A, 8 bit number given in the instruction - Carry Flag

E.g. SCI 20H Subtract from number in A, number 20H A A -20H - Carry Flag

Register A CY Register A CY
7FH 1 After execution of ACI 20H 5EH 0

If Register A has the value 7FH and if carry flag is 1, then after execution of the instruction SCI 20H, the new value
in A shall be 5EH and new value in Carry Flag shall be 0.
Arithmetic Instructions (SCI 8 bit number)
SCI 8 bit number

Size of Instruction : 02 Byte


T-States Required for fetching & execution:
◦ 02 Machine Cycles
◦ M1- 04 T- states – Fetch op code
M2 -03 T-States - Fetch operand (8 bit number) and perform addition in same Machine
cycle
Instruction Fetch & Execute Cycle for SCI 8 bit number
M1 Machine Cycle – Opcode Fetch

T1 – 8085 puts the address of ROM memory


location from where the Op code is to be fetched
on higher and lower address bus

T2 – 8085 enables the /RD signal so that the


opcode can be read from ROM memory location

T3 – The opcode is fetched and stored in


Instruction Register (IR) in the 8085

T4 – Decoding of the Opcode takes place so that


8085 knows what is to be done next. Looking at
opcode 8085 understands that the operand is to
be fetched and that requires an additional
memory read cycle.
Instruction Execute Cycle for ACI 8 bit number
M2 Machine Cycle – Operand Fetch &
Execution

This is memory Read cycle

Operand (8 bit number is fetched and


subtraction is performed in this Machine
Cycle itself

Data
Arithmetic Instructions (INR R/M
INR R/M (ALL FLAGS EXCEPT CARRY FLAG ARE AFFECTED)
Increment contents of Register or Memory by 1

E.g. INR C Increment contents of register C by 1 C C+1


INR M Increment contents of memory location, whose address is in HL, by 1
[HL] [HL] + 1
Arithmetic Instructions (DCR R/M
INR R/M (ALL FLAGS EXCEPT CARRY FLAG ARE AFFECTED)
Decrement contents of Register or Memory by 1

E.g. INR C Increment contents of register C by 1 C C-1


INR M Increment contents of memory location, whose address is in HL, by 1
[HL] [HL] - 1
Arithmetic Instructions (INR R/M) / (DCR R/M)
INR R/M or DCR R/M

Size of Instruction : 01 Byte


T-States Required for fetching & execution:
◦ In case if INR/DCR R
◦ 01 Machine cycle of 4 T States
◦ In case of INR/DCR M
◦ M1- 04 T- states – Fetch op code
M2 -03 T-States - Fetch the data stored in memory location whose address is in HL, into the ALU and increment
M3 – 03 T-States – Incremented number is written back into memory location whose address is in HL
Arithmetic Instructions (INX Rp) / (DCX Rp)
INX Rp / DCX Rp (No flags are affected)
Increment or decrementing contents of Register pair BC, DE, HL or SP

E.g. INX B Increment contents of register BC by 1 BC BC+1


INX H Increment contents of memory location, whose address is in HL, by 1
HL HL + 1
Write a program in 8085 assembly language
to subtract the number stored at 2001H from
the number stored at 2002H and store the
difference in 2003H
LDA 2001H 3 13 LXI H 2002H 3 10 LXI H 2002H 3 10
MOV B,A 1 4 MOV A,M 1 7 MOV A,M 1 7
LDA 2002H 3 13 DCX H 1 6 DCX H 1 6

SUB B 1 4 SUB M 1 7 SUB M 1 7


STA 2003H 3 13 INX H 1 6
STA 2003H 3 13
9
11 47 43 INX H 1 6
MOV M,A 1 7
9
49
Write a program in 8085 assembly language
to add the number 54H to the numbers stored
at memory location 2000H, 2001H & 2002H
LDA 2000H LXI H, 2000H LDA 2000H
ADI 54H MVI A, 54H MVI B, 54H
STA 2000h ADD M ADD B
LDA 2001H MOV M,A STA 2000H
ADI 54H INX H
STA 2001H MVI A, 54H
LDA 2002H ADD M
ADI 54H MOV M,A
STA 2002H
Write a program in 8085 assembly language
to add the 03 numbers stored at memory
location 2000H, 2001H & 2002H and store the
sum in 2003H
LXI H, 2000H LDA 2000H
MOV A,M MOV B,A
INX H LDA 2001H
ADD M ADD B
INX H MOV B,A
ADD M LDA 2002H
INX H ADD B
MOV M,A STA 2003H
Write a program in 8085 assembly language
to add the 02 16 bit numbers stored at
memory location 2000H, 2001H & 2002H,
2003H and store the sum in 2004H, 2005H
LDA 2000H LDA 2000H
MOV B,A LXI H, 2002
LDA 2002H ADD M
ADD B STA 2004H
STA 2004H
LDA 2001H
LDA 2001H
LXI H, 2003H
MOV B,A
ADC M
LDA 2003H
STA 2005H
ADC B
STA 2005H
Write a program in 8085 assembly language
to add the 02 8 bit numbers stored at memory
location 2000H & 2001H and store the 16 bit
sum in 2003H, 2002H
MVI A, 00H 2 7
LDA 2000H //Adding two bytes from 3 13
STA 2003H //Store 00H at 2003H 3 13
MOV B,A //2000h & 2001H 1 4
LDA 2000H //Adding two bytes from 3 13
LDA 2001H //Store sum at 2002H 3 13
MOV B,A //2000h & 2001H 1 4
ADD B 1 4
LDA 2001H //Store sum at 2002H 3 13
STA 2002H 3 13
ADD B 1 4
STA 2002H 3 13
MVI A, 00H 2 7
LDA 2003H //Add carry bit to the 3 13
ACI 00H //Add carry bit to the 2 7
ACI 00H //number at 2003H 2 7
STA 2003H //number at 2003H 3 13
STA 2003H 3 13
18 74
24 96
Logic Instructions
ANA R/M A <- A AND R/M
ANI 8 bit number A <- A AND 8 bit number
XRA R/M A <- A XOR R/M Effect on Flags

XRI 8 bit number A <- A XOR 8 bit number 1. Zero flag (ZF), Sign flag (SF), Parity flag
(PF) are affected
ORA R/M A <- A OR R/M
2. Carry flag & Overflow Flags are not
ORI 8 bit number A <- A OR 8 bit number SBI
affected
CMA A <- NOT A
3. Except NOT, all logical instructions
CMP R/M A - R/M
clear carry flag (CF) and overflow flag
CPI 8 bit number A - 8 bit number (OF)
CMC COMPLEMENT CARRY FLAG 4. AC is undefined
STC CARRY FLAG=1
Logic Instructions (Contd.)

Each binary bit of the accumulator is rotated left by one


RLC Rotate the accumulator left position. Bit D7 is placed in the position of D0 as well as in the
Carry flag. CY is modified according to bit D7.
Each binary bit of the accumulator is rotated right by one
RRC Rotate the accumulator right position. Bit D0 is placed in the position of D7 as well as in the
Carry flag. CY is modified according to bit D0.
Each binary bit of the accumulator is rotated left by one
Rotate the accumulator left through position through the Carry flag. Bit D7 is placed in the Carry
RAL
carry flag, and the Carry flag is placed in the least significant position
D0. CY is modified according to bit D7.

Each binary bit of the accumulator is rotated right by one


Rotate the accumulator right through position through the Carry flag. Bit D0 is placed in the Carry
RAR
carry flag, and the Carry flag is placed in the most significant position
D7. CY is modified according to bit D0.
Logic Instructions (Contd.)

Each binary bit of the accumulator is rotated left by one


RLC Rotate the accumulator left position. Bit D7 is placed in the position of D0 as well as in the
Carry flag. CY is modified according to bit D7.

A = 0010 0111
RLC
RLC
RLC
CY = 0 A= 10011100 RLC
RLC

CY =1 A = 00111001
Logic Instructions (Contd.)

Each binary bit of the accumulator is rotated right by one


RRC Rotate the accumulator right position. Bit D0 is placed in the position of D7 as well as in the
Carry flag. CY is modified according to bit D0.

A= 10011100 CY = 0
RRC

A = 01001110 CY = 0
Logic Instructions (Contd.)

Each binary bit of the accumulator is rotated left by one


Rotate the accumulator left through position through the Carry flag. Bit D7 is placed in the Carry
RAL
carry flag, and the Carry flag is placed in the least significant position
D0. CY is modified according to bit D7.
Logic Instructions (Contd.)

Each binary bit of the accumulator is rotated right by one


Rotate the accumulator right through position through the Carry flag. Bit D0 is placed in the Carry
RAR
carry flag, and the Carry flag is placed in the most significant position
D7. CY is modified according to bit D0.
language to perform the Logic AND
operation on the two numbers stored at
2000H & 2001H and store the answer in
2002H
LXI H, 2000H
MOV A,M //Read number from 2000H and bring into A
INX H
ANA M //Logical AND with number at 2001H
INX H
MOV M,A //Store result at 2002H
Branching Instructions
There are three categories of Branching Instructions in the Instruction set of 8085:

1. Jump (unconditional and conditional)

2. Call (unconditional and conditional)

3. Return (unconditional and conditional)

OPCODE OPERAND EXPLANATION EXAMPLE

JMP address Jumps to the address JMP 2050

CALL Address Start Fetching Instruction from that address CALL 2050

RET Return from Subroutine unconditionally RET


Branching Instructions (JMP)
OPCODE OPERAND EXPLANATION EXAMPLE

JC address Jumps to the address if carry flag is 1 JC 2050

JNC address Jumps to the address if carry flag is 0 JNC 2050

JZ address Jumps to the address if zero flag is 1 JZ 2050

JNZ address Jumps to the address if zero flag is 0 JNZ 2050

JPE address Jumps to the address if parity flag is 1 JPE 2050

JPO address Jumps to the address if parity flag is 0 JPO 2050

JM address Jumps to the address if sign flag is 1 JM 2050

JP address Jumps to the address if sign flag 0 JP 2050


Branching Instructions (CALL)
OPCODE OPERAND EXPLANATION EXAMPLE

CC address Call if carry flag is 1 CC 2050

CNC address Call if carry flag is 0 CNC 2050

CZ address Calls if zero flag is 1 CZ 2050

CNZ address Calls if zero flag is 0 CNZ 2050

CPE address Calls if parity flag is 1 CPE 2050

CPO address Calls if parity flag is 0 CPO 2050

CM address Calls if sign flag is 1 CM 2050

CP address Calls if sign flag is 0 CP 2050


Branching Instructions (RET)
OPCODE OPERAND EXPLANATION EXAMPLE

RC none Return from the subroutine if carry flag is 1 RC

RNC none Return from the subroutine if carry flag is 0 RNC

RZ none Return from the subroutine if zero flag is 1 RZ

RNZ none Return from the subroutine if zero flag is 0 RNZ

RPE none Return from the subroutine if parity flag is 1 RPE

RPO none Return from the subroutine if parity flag is 0 RPO

RM none Returns from the subroutine if sign flag is 1 RM

RP none Returns from the subroutine if sign flag is 0 RP


Write a program in 8085 assembly language
to add the 02 8 bit numbers stored at memory
location 2000H & 2001H and store the 16 bit
sum in 2003H, 2002H
LDA 2000H //Adding two bytes from 3 13 LDA 2000H //Adding two bytes from 3 13

MOV B,A //2000h & 2001H 1 4 MOV B,A //2000h & 2001H 1 4
LDA 2001H //Store sum at 2002H 3 13
LDA 2001H //Store sum at 2002H 3 13
ADD B 1 4
ADD B 1 4
STA 2002H 3 13
STA 2002H 3 13 JC up IF CY=1 then goto NXT else goto next instruction
MVI A, 00H
MVI A, 00H 2 7
STA 2003H
ACI 00H //Add carry bit to the 2 7 HLT
STA 2003H //number at 2003H 3 13 up: MVI A, 01H
18 74 STA 2003H
HLT
to store the number 00H in 5 memory
locations starting from 2000H and the
program shall be stored from 1000H
LXI H, 2000H
A
MVI A, 00H 1000H LXI H, 2000H 3 10 00
MOV M,A 1003H MVI A, 00H 2 7
00 C
INX H 1005H MVI C, 05H 2 7
H L
MOV M,A 1007H MOV M,A 1 7
20 05
INX H 1008H INX H 1 6
MOV M,A 1009H DCR C 1 4 Z
INX H 100AH JNZ 1007H 3 7 / 10 1
MOV M,A 100DH HLT 1 4
INX H
MOV M,A
to add the 05 numbers stored starting from
memory location 2000H and store the 16 bit
sum at 2005H & 2006H
A
MVI C,04H ;Set counter for 4 loop 70
MVI D,00H ;Using as MSB
LXI H,2000H ; Initialise to starting memory
MOV A,M ;Get number from 2000H 01 D 0 C
AGAIN: INX H ;Point to next address H L
ADD M ;Perform addition
JNC AHEAD ;If carry then increment D 20 04
INR D 2000H 7F
AHEAD: DCR C ;Reduce counter
2001H 22 Z CY
JNZ AGAIN ;repeat addition
INX H ;Point to LSB location 2002H 36
CD 1 0
MOV M,A ;Store LSB 2003H 5F
INX H ;Point to MSB location
MOV M,D ;Store 2004H 4A
HLT 2005H 70
2006H 00
What will be the contents of Register A, HL,
Memory and the flags at the completion of
following programs
A

LXI H, 2000H 61
MVI M, 07H
INX H C
MVI M,5AH
LDA 2000H H L
ADD M 20 02
INX H
MOV M,A
HLT 2000H 07 P S Z AC CY
2001H 5A
0 0 0 1 0
2002H 61
2003H
2004H
2005H
What will be the contents of Register A, HL
and the flags at the completion of following
programs
A

LXI H, 2000H
MVI D,09H
AGAIN: MVI M, 07H 00 D
INX H
DCR D H L
JNZ AGAIN 20 09
HLT

2000H 07 P S Z AC CY
2001H 07
0 0 1 0 0
2002H 07
07
2003H 07
2004H 07
2005H
Data Transfer Instructions (LHLD 16 bit address)
LHLD 16 bit address

Load into Register L the data at memory location whose address is given in instruction and load into H
the data from the next memory location
E.g. If for the Memory locations given below execution of LHLD 2000H will result in 5A in L and 2F in H.
Execution of LHLD 2003H will result in 1FH in L and 22H in H
L (address) H (address +1)
Size of Instruction: 3 Bytes 2000H 5AH
Number of Machine Cycles to Fetch the Instruction: 03 M1, M2 & M3 (10 T)
Number of Machine Cycles to Execute the Instruction: 02 M4 & M5 (6 T) 2001H 2FH
2002H 39H
2003H 1FH
2004H 22H
Data Transfer Instructions (SHLD 16 bit address)
SHLD 16 bit address

Store the data in L into memory location whose address is given in instruction and store number in H
into the next memory location
E.g. Suppose data in HL is 379FH
Then SHLD 2000H will result in 9FH in memory location 2000H and 27H in 2001H
(address) L (address +1) H

2000H 5AH
Size of Instruction: 3 Bytes
Number of Machine Cycles to Fetch the Instruction: 03 M1, M2 & M3 (10 T) 2001H 2FH
Number of Machine Cycles to Execute the Instruction: 02 M4 & M5 (6 T) 2002H 39H
2003H 1FH
2004H 22H
Data Transfer Instructions (LDAX Rp)
LDAX Rp

Load into Accumulator the data from memory location whose address is given in the Register Pair
E.g. LDAX B
Suppose 16 bit number in BC is 2000H then the number stored in 2000H will be copied into
Accumulator
A (BC)

2000H 5AH
Size of Instruction: 1 Bytes
Number of Machine Cycles to Fetch the Instruction: 01 M1 (4 T) 2001H 2FH
Number of Machine Cycles to Execute the Instruction: 01 M2 (3 T) 2002H 39H
2003H 1FH
2004H 22H
Data Transfer Instructions (STAX Rp)
STAX Rp

Copy the number in Accumulator to memory location whose address is given in the Register Pair
E.g. STAX B
Suppose 16 bit number in BC is 2000H and number in A is 7FH then 7FH will be transferred into
memory location 2000H
(BC) A

2000H 5AH
Size of Instruction: 1 Bytes
Number of Machine Cycles to Fetch the Instruction: 01 M1 (4 T) 2001H 2FH
Number of Machine Cycles to Execute the Instruction: 01 M2 (3 T) 2002H 39H
2003H 1FH
2004H 22H
Data Transfer Instructions (XCHG)
XCHG

Exchange values of HL & DE register pair


E.g. STAX B
Suppose 16 bit number in HL is 2000H and DE is 5000H then after execution of XCHG HL will contain
5000H and DE will contain 2000H

2000H 5AH
Size of Instruction: 1 Bytes
Number of Machine Cycles to Fetch & Execute the Instruction: 01 M1 (4 T) 2001H 2FH
2002H 39H
2003H 1FH
2004H 22H
Arithmetic Instruction (DAA)
DAA

Used for addition of two BCD numbers

•If the LS hex digit in A is <= 9 and AC flag is 0, the LS hex digit value will not be altered.

•If the LS hex digit is >9, or if AC flag is set to 1, it adds 6 to the LS hex digit of A. If carry results, then it
increments the MS hex digit if this addition resulted in a carry to the MS digit position. In this process,
the Cy flag will be set to 1 if the MS hex digit was incremented from F to 0.

•If the MS hex digit is <= 9 and Cy flag is 0, the MS hex digit will not be altered, and Cy flag is reset to 0.

•If the MS hex digit is > 9, or if Cy flag is set to 1, it adds 6 to the MS hex digit of A and sets Cy flag to 1.

Size of Instruction: 1 Bytes


Number of Machine Cycles to Fetch & Execute the Instruction: 01 M1 (4 T)
DAA Instruction
Suppose there are 20 Chairs in a room, then in Hexadecimal we say 14H Chairs
In binary we represent the same as 0001 0100
In BCD we write 20 as 0010 0000
Suppose we add 15 more chairs in the same room, then in Hexadecimal the new count shall be 23H
14 H + 0FH = 23H
Now in BCD 20 Chairs = 0010 0000
15 Chairs = 0001 0101
Total chairs = 0011 0101 = 35

Suppose there are 09 chairs in the room = 0000 1001


Add 03 more chairs in the room = 0000 0011
So total Chairs in the room = 0000 1100 (Am I getting answer in BCD? – N
I fix the problem by adding 06H in the answer 0000 1100
0000 0110
0001 0010 (12)
Usage of DAA Instruction

MVI A, 09H A=09H


MVI B, 03H B=03H
ADD B A=0CH
DAA A=12H 0001 0010
Arithmetic Instruction (DAD Rp)
DAD Rp

16 bit addition of contents of HL + contents of Register Pair. Only Carry Flag is affected
HL HL + Rp
E.g.
DAD B HL HL + BC
DAD D HL HL + DE
DAD H HL HL + HL
DAD SP HL HL + SP

Size of Instruction: 1 Bytes


Number of Machine Cycles to Fetch & Execute the Instruction: 01 M1 (6 T)
Memory Stack & Related Instructions
Stack is a designated part of the RAM connected to the microprocessor which behaves in the Last In First
Out mode of operation.

In 8085 microprocessor, the Stack behaves in reverse manner i.e the Top of the Stack is the highest
memory address and the memory addresses lower than that are used as part of stack. The address of
Top of Stack is stored in SP (stack Pointer) Register.
The instruction used to store data into the stack is PUSH which essentially results in two memory write
cycles as two byres are stored in the stack in response to PUSH.

The instruction used to get back data from the stack is POP which essentially results in two memory read
cycles as two bytes are read back from the stack in response to POP.
Memory Stack & Related Instructions (PUSH Rp)

PUSH Rp
Store two bytes of the Register Pair into the stack. Higher byte is stored in memory whose address is
on lower than the ToS and the lower byte is stored in memory address even one lower than that.
E.g. PUSH B Stores B & C on stack
PUSH D Stores D & E on stack
PUSH H Stores H & L on stack
PUSH PSW Stores A & FLAG REGISTER (PSW) on stack

In response to PUSH Rp steps are as follows:


1. Address in SP is reduced by 1 (SP < - SP-1)
2. Store Higher Byte in stack memory whose address is in SP
3. Address in SP is reduced by 1 (SP < - SP-1)
4. Store Lower Byte in stack memory whose address is in SP
Example of (PUSH Rp)

Suppose initial value of BC=917FH, SP=2FFFH 2FFBH 5AH


2FFCH 2FH
2FFDH 39H
Execution of PUSH B instruction will result in following steps by CU of 8085
2FFEH 1FH
Step 1: SP=SP-1 i.e. SP=2FFEH
2FFFH 22H
Step 2: Store B in this memory i.e. value in B (91H) will be stored in 2FFEH
Step 3: SP=SP-1 i.e. SP=2FFDH
Step 4: Store C in this memory i.e. value in C (7FH) will be stored in 2FFDH
Memory Stack & Related Instructions (POP Rp)

POP Rp
Read two bytes from the top of Stack and store them in the Register Pair. Data stored at memory
whose address is in SP Register will be read into Lower Register and the data stored at the next higher
memory location is read into Higher Register.
E.g. POP B Two bytes will be read from Stack memory and stored in B & C Register
POP D Two bytes will be read from Stack memory and stored in D & E Register
POP H Two bytes will be read from Stack memory and stored in H & L Register
POP PSW Two bytes will be read from Stack memory and stored in A & FLAG REGISTER (PSW)

In response to POP Rp steps are as follows:


1. Data stored at memory location whose address is in SP is copied into the lower Register of Register Pair
2. Address in SP is incremented by 1 (SP < - SP+1)
3. Data stored at memory location whose address is in SP is copied into the Higher Register of Register Pair
4. Address in SP is incremented by 1 (SP < - SP+1)
Example of (POP Rp)

Suppose initial value of BC=917FH, SP=2FFDH and value in 2FFD is 39H and 2FFBH 5AH

Value in 2FFEH is 1FH 2FFCH 2FH


2FFDH 39H
Execution of POP B instruction will result in following steps by CU of 8085:
2FFEH 1FH
Step 1: Copy into C the contents of memory location whose address is in
2FFFH 22H
SP (2FFDH) i.e. the number 39H is copied into C
Step 2: SP=SP+1 i.e. SP=2FFEH
Step 3: Copy into C the contents of memory location whose address is in SP (2FFEH)
i.e. the number 1FH is copied into B
Step 4: SP=SP+1 i.e. SP=2FFFH
So new value in BC=1F39H
The contents of Accumulator and Zero Flag at the end of
execution of following program are 39h, 1___________

BC = 2957H
DE = 3962H 2FF9H 62H
A FLAGS = XX YYH 2FFAH 39H
2FFBH 57H
2FFCH 29H
A FLAGS = 39 62H SP 2FFDH YYH
BC = 2957H 2FFEH XXH
HL = XXYYH 2FFFH 22H
Write a program in 8085 assembly language to add the
02 16 bit numbers stored at memory location 2000H,
2001H & 2002H, 2003H and store the sum in 2004H,
2005H

LHLD 2000H //Read 2000H into L, 2001H into H


XCHG //Store HL in DE i.e. first 16 bit number in DE
LHLD 2002H //Read 2002H into L, 2003H into H
DAD D //HL=HL+DE
SHLD 2004H //Store 16 bit answer at 2004H and 2005H
Write a program in 8085 assembly language to add the
02 16 bit numbers stored at memory location 2000H,
2001H & 2002H, 2003H and store the sum in 2004H,
2005H & 2006H
Write a program in 8085 assembly language unpack
the packed 2 digit BCD number stored at memory
location 2000H and store the two unpacked BCD
numbers at 2001H & 2002H

2000H 57 0101 0111


2001H 05 0000 0101
2002H 07 0000 0111
Mask off the Upper Nibble AND 57 with 0F 0101 0111
0000 1111
0000 0111
Mask off the Lower Nibble AND 57 with F0 0101 0111
1111 0000
0101 0000 = 0000 0101
Write a program in 8085 assembly language unpack
the packed 2 digit BCD number stored at memory
location 2000H and store the two unpacked BCD
numbers at 2001H & 2002H

LDA 2000H
ANI 0x0F
STA 2002H
LDA 2000H
ANI 0xF0
RLC
RLC
RLC
RLC
STA 2001H
unpacks the packed 2 digit BCD number passed to it in H
and returns the two unpacked BCD numbers in H & L
registers. Now write a program to read packed 2 digit
BCD number from 2000H and store unpacked 2 digits in
2001H and 2002H. Call the subroutine for the unpacking
LDA 2000H Subroutine Called UNPACK
Main Program
//This subroutine will accept a packed 2 digit BCD number
ANI 0x0F LXI SP, 2FFFH in Register H, then unpack the two BCD digits and store
STA 2002H them in Register H & L. Then return to Calling Program
LDA 2000H
MOV B,H
LDA 2000H MOV H,A MOV A,B
ANI 0xF0 CALL UNPACK ANI 0x0F
MOV H,A
RLC MOV A,H MOV A,B
STA 2001H ANI 0xF0
RLC RLC
RLC MOV A,L RLC
RLC
STA 2002H
RLC RLC
HLT MOV L,A
STA 2001H RET
Write a program in 8085 assembly language to
transfer 10 bytes of data starting from memory
location 2000H onwards to memory location
starting from 3000H onwards
LXI B, 2000H //Initialize BC to 2000H 10 X 1 =10
LXI D, 3000H //Initialize DE to 3000H 10 X 1 = 10
MVI H, 0x0A //Set counter for 10 times 7 X 1 =7
AGAIN: LDAX B //Read one byte from memory whose address is in BC 7 X 10=70
STAX D //Store the byte in memory whose address is in DE 7 X 10 = 70
INX B //Increment both pointers 6 X 10 =60
INX D 6 X 10 = 60
DCR H //Reduce counter and check to run the loop 10 times 4 X 10 = 40
JNZ AGAIN 10 X9 + 7 X 1 = 97
HLT 4 X 1 =4
Write a program in 8085 assembly language to
transfer 10 bytes of data starting from memory
location 2000H onwards to memory location
starting from 3000H onwards

LXI H, 2000H //Initialize BC to 2000H


LXI D, 3000H //Initialize DE to 3000H
MVI C, 0x0A //Set counter for 10 times
AGAIN: MOV A,M //Read one byte from memory
XCHG //Exchange HL & DE
MOV M,A //Increment both pointers
XCHG
INX H
INX D
DCR C //Reduce counter and check to run the loop 10 times

JNZ AGAIN
HLT
to add the 05 numbers stored starting from
memory location 2000H and store the 16 bit
sum at 2005H & 2006H
A
MVI C,04H ;Set counter for 4 loop 70
MVI D,00H ;Using as MSB
LXI H,2000H ; Initialise to starting memory
MOV A,M ;Get number from 2000H 01 D 0 C
AGAIN: INX H ;Point to next address H L
ADD M ;Perform addition
JNC AHEAD ;If carry then increment D 20 04
INR D 2000H 7F
AHEAD: DCR C ;Reduce counter
2001H 22 Z CY
JNZ AGAIN ;repeat addition
INX H ;Point to LSB location 2002H 36
CD 1 0
MOV M,A ;Store LSB 2003H 5F
INX H ;Point to MSB location
MOV M,D ;Store 2004H 4A
HLT 2005H 70
2006H 00
unpacks the packed 2 digit BCD number passed to it in H
and returns the two unpacked BCD numbers in H & L
registers. Now write a program to read packed 2 digit
BCD number from 2000H and store unpacked 2 digits in
2001H and 2002H. Call the subroutine for the unpacking
LDA 2000H Subroutine Called UNPACK
Main Program
//This subroutine will accept a packed 2 digit BCD number
ANI 0x0F LXI SP, 2FFFH in Register H, then unpack the two BCD digits and store
STA 2002H them in Register H & L. Then return to Calling Program
LDA 2000H
MOV B,H
LDA 2000H MOV H,A MOV A,B
ANI 0xF0 CALL UNPACK ANI 0x0F
MOV H,A
RLC MOV A,H MOV A,B
STA 2001H ANI 0xF0
RLC RLC
RLC MOV A,L RLC
RLC
STA 2002H
RLC RLC
HLT MOV L,A
STA 2001H RET
Program Counter (PC) 010AH A 03 B 38 C 0
H L
08 03
Main Program Address Instruction
Address Instruction
0200H MOV B,H
0100H LXI SP, 2FFFH
0201H MOV A,B
0103H LDA 2000H
0202H ANI 0x0F
0106H MOV H,A
0204H MOV H,A
0107H CALL 0200H
2000H 38 0205H MOV A,B
010AH MOV A,H
2001H 00 0206H ANI 0xF0
010BH STA 2001H
2002H 00 0208H RLC
010EH MOV A,L
0209H RLC
010FH STA 2002H
2FFCH 5F 020AH RLC
0112H HLT
2FFDH 0A (PCL) 020BH RLC
SP 2FFEH 020CH MOV L,A
01 (PCH)
2FFFH 2FFFH 00 020DH RET
Program Counter (PC) 010AH A 03 B 38 C 0
H L
08 03 Subroutine Unpack Subroutine SWAP
Main Program Address Instruction Address Instruction
Address Instruction
0200H PUSH B 0300H RLC
0100H LXI SP, 2FFFH 2000H 38
0201H MOV B,H 0301H RLC
0103H LDA 2000H 2001H 00
0202H MOV A,B 0302H RLC
0106H MOV H,A 2002H 00
0203H ANI 0x0F 0304H RLC
0107H CALL 0200H
0205H MOV H,A 0305H RET
010AH MOV A,H
2FF9H 00 0206H MOV A,B
010BH STA 2001H
2FFAH 00 0208H ANI 0xF0
010EH MOV A,L
2FFBH 0B (PCL) 020BH CALL 0300H
010FH STA 2002H
2FFCH 02 (PCH) 020EH MOV L,A
0112H HLT
2FFDH 0A (PCL) 020FH POP B
SP 2FFEH 01 (PCH) 0210H RET
2FFFH 2FFFH 00

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