[Video
FPGA
Title] Design for Embedded
Systems
Hardware Description
[Instructor Name(s)]
Languages for Logic
[Department Name]
Design
Copyright © 2019 University of
Colorado
Synchronous Logic : D Latch
How can we make a D Latch in VHDL?
D
Q
GATE
CLR
Copyright © 2019 University of
Colorado
Synchronous Logic : D Latch
-- Entity
entity DLatches is port (
d, gate, clr : in std_logic;
q : out std_logic );
end entity DLatches;
-- Architecture
architecture LArch of DLatches is begin
latch_proc_1 : process (gate, d)
begin
if (gate='1') then q <= d;
-- No rising_edge()
end if;
-- No gate=0 value, so latch
inferred
end process latch_proc_1;
Copyright © 2019 University of
Colorado
Synchronous Logic : D Latch
-- another Latch example
latch_proc_2 : process (gate, d, clr)
begin
if (clr ='1') then q <= '0';
elsif (gate='1') then q <= d;
end if;
end process latch_proc_2;
end architecture LArch;
Copyright © 2019 University of
Colorado
Combinatorial Logic
• Finite time for best case or worst case
[Video logic value to propagate a result through
wires and logic cells across the chip
Title] • 0 -> 1 transition for path C to Y
• 0.2 + 0.9 + 0.3 + 1.1 + 0.2 = 2.7nano seconds
D
C
0.2ns 0.3ns Y
0.9ns 0.2ns
A E 1.1ns
B
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Colorado
Synchronous Logic
• Logic path synchronized to CLK
C
D Y
D Q
A E
B CLK
Reset
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Colorado
Synchronous Logic : D Flip Flop
How can we make a D Flip Flop in VHDL?
D Q
Copyright © 2019 University of
Colorado
Synchronous Logic : D Flip Flop – Sync Reset
-- Entity
entity DFF is port (
d, clk, reset : in std_logic;
q : out
std_logic );
end entity DFF;
Copyright © 2019 University of
Colorado
Synchronous Logic : D Flip Flop – Sync Reset
-- Architecture,
-- could use (clk'event and clk='1')
architecture DFF_Arch of DFF is
begin dff_proc_1 : process (clk)
begin
if (rising_edge(clk)) then
if (reset='1') then q <= '0';
-- Sync Reset
else q <= d;
end if;
end if;
end process dff_proc_1;
end architecture DFF_Arch;
Copyright © 2019 University of
Colorado
Synchronous Logic : D Flip Flop – Async Reset
How can we make a D Flip Flop in VHDL?
S
D Q
Copyright © 2019 University of
Colorado
Synchronous Logic : D Flip Flop – Async Reset
-- Entity
entity DFF is port (
d, clk, set, reset : in std_logic;
q : out std_logic );
end entity DFF;
-- Architecture, Next Slide
Copyright © 2019 University of
Colorado
Synchronous Logic : D Flip Flop – Async Reset
-- Architecture
architecture DFF_Arch of DFF is
begin dff_proc_2 : process (clk, set,
reset)
begin
if (reset='1') then q <=
'0';
-- Async
elsif (rising_edge(clk)) then
if (set='0') then q <=
'1';
-- Sync
else q <=
d;
-- Sync
end if;
end if;
end process dff_proc_2;
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end architecture DFF_Arch;
Colorado
Synchronous Logic : D Flip Flop
How can we make a Clock Enable in VHDL?
D Q
En
R
Copyright © 2019 University of
Colorado
Synchronous Logic : D Flip Flop – Clock Enable
-- Entity
entity DFF is port (
d, clk, ce, reset : in std_logic;
q : out std_logic );
end entity DFF;
-- Architecture, Next Slide
Copyright © 2019 University of
Colorado
Synchronous Logic : D Flip Flop – Clock Enable
-- Architecture
architecture DFF_Arch of DFF is
begin dff_proc_3 : process (clk, ce, reset)
begin
if (reset='1') then q <= '0';
-- Async
elsif (rising_edge(clk)) then
if (ce='1') then q <= d;
-- Sync
end if;
end if;
end process dff_proc_3;
end architecture DFF_Arch;
Copyright © 2019 University of
Colorado
Summary – VHDL for Synchronous Circuits
In this video, you have learned:
• How to describe synchronous circuits in
VHDL
• How to design flip flops with synchronous
and asynchronous set and reset
Copyright © 2019 University of
Colorado
