Microprocessor and

Interfacing Techniques
Course Code- CSI2006
Module:1 Intel x86/ARM Processors:
Architecture and Signal Description, Register and Memory Organization,
General Bus Operations and IO Addressing Capability, Special Processor
Activities, Min and Max Modes, Reduced-Instruction-Set Computing(RISC)
Module:2 Assembly Language Programming and Tools:
Addressing modes and Instruction Set, Assembler Directives and Operators,
Introduction to emu8086 emulator and MASM assembler, Assembly Language
example programs.
Module:3 Special Architectural Features and Programming:
Stack – stack structure of 8086/ARM and programming; Interrupt – interrupt
cycle, non-mask able, mask- able, Interrupt Service Routine, programming;
procedure and macro– definition and passing parameters; handling larger
programs; timing and delays – clock cycle, states, instruction execution time,
clock count for generating delays; file management – create, open, close, read,
write and delete operations;
Module:4 Basic Peripherals Interfacing:
Memory Interfacing – Interleaving, static and dynamic RAM
interfacing; IO Ports Interfacing – memory mapped I/O, I/O mapped
I/O; PIO 8255 – architecture, pin, control word register, operation
modes; A/D Interfacing – 0808 SAR, 7109 dual-slope, interfacing; D/A
– 7523, DAC0800; Stepper Motor – 4 winding internal schematic,
excitation sequence, sample programs.
Module:5 Special Purpose Programmable Peripheral Interfacing:
Timer/Counter 8253 – architecture, pin, control word register, operation
modes, programming; PIC-8259 – architecture, pin, interrupt sequence,
command words, operation modes, programming; 8279 – architecture,
pin, operation modes, programming; 8251 – communication methods,
architecture, pin, operation modes, programming; 8257 – architecture,
pin, DMA transfers and operations, programming.
Module:6 Numeric Co-Processor 8087:
Overview, compatible processor and coprocessor, pin, architecture,
block diagram - control unit, numeric execution unit, registers, status
word, circuit connection of 8086-8087,data types, IEEE floating point
standard, instruction set, sample programs.
Module:7 Case Study on Microcontroller Boards :
Introduction to Microcontroller, UNO Board, IDE, Programming using
GPIO for LED, LCD, Keypad, Motor, Sensor interfacing, case study on
smart system design.
Module:8 Recent Trends
Module:1 Intel x86/ARM Processors:
Origin of Microprocessor:
• Microprocessor is the greatest invention of the 20 th Century
• Evolution started from the earlier mechanical calculating devices-In
1930
• In 1950-Replaced by Vacuum tubes-Replaced by transistors
• Transistor Technology led to the introduction of minicomputer in the
1960s and the PC revolution in the 1970s
• TT led to the development of complex devices called ICs
 • MPU later evolved as an IC and was designed to fetch instructions and
execute the predefined arithmetic and logic functions.
• Intel was the 1st MPU producer and has been holding a large share of the
world market for this product.
• Evolution of the microprocessor is categorized into five generations.
• Origin of Microprocessors-First generation(1971-1973)
• 1st microprocessor-4004-introduced in 1971
• 4-bit 4004 microprocessors ran at 108kHz and contained 2300 transistors
• Fabrication using p-channel MOS tech.
• low cost, slow speed
• In 1972, Intel made 8-bit 8008 and 8080 µP.
• Origin of Microprocessors-Second generation(1974-1978)
• 2nd generation devices- use of newer semiconductor tech to fabricate chips.
• By using n-channel (NMOS) tech.
• Advantages: Five-fold increase in instruction execution speed and higher chip
densities.
• Origin of Microprocessors-Third generation(1978-1980)
• 3rd generation as dominated by Intel’s 8086 and Zilog’s Z8000.
• 16-bit processors with minicomputer-like performance
• Example: Motorola’s MC68020-On chip cache was incorporated for the first time and
pipeline was increased to five or more stages.
• Design techniques-HMOS tech.
• Advantages:
• Speed-power product is four times better than that of the NMOS.
• Can accommodate twice the circuit density of NMOS.
• Origin of Microprocessors-Fourth generation(1981-1995)
• 4th generation designs contains more than a million transistor in a single
package.
• Beginning of 32-bit µP’s.
• Intel 80386 and Motorola 68020/68030 were introduced
• Fabrication-High density/High speed CMOS(HCMOS)
• Origin of Microprocessors-Fifth generation(1995-till date)
• It employs decoupled super scalar processing.
• Design contains more than 10 million transistors
• Introduction of an on-chip functionalities
• High speed memory I/O devices, intro of 64-bit µP’s
• Intel lead the show here with Pentium, Celeron, Dual-and quad-core and very
recently i3,i5,i7 working with up to 3.33 GHz Turbo Boost speed.
Applications
• The microprocessor has made possible the
– inexpensive hand-held electronic calculator, the digital wristwatch, and the
electronic game.
• Microprocessors are used to control consumer electronic devices, such
as the
– programmable microwave oven and videocassette recorder;
– to regulate gasoline consumption and antilock brakes in automobiles;
– to monitor alarm systems; and to operate automatic tracking and
– targeting systems in aircraft, tanks, and missiles and to control radar arrays that
track and identify aircraft, among other defense applications.
8086 Microprocessor
• In 1978, Intel released its first 16-bit microprocessor-8086.
• It executes the instructions at 2.5MIPS (Million Instruction per
Second).
• Execution time for one instruction is 400ns(1/MIPS).
• 8086 can address 1MB(1MB=220 bytes) of memory-20 bit address bus
• Width of the data bus is 16bits
• Feature- Small six-byte instruction queue
• Instruction fetched from the memory are placed before they are executed.
• Intel 8086 is a 16-bit HMOS
microprocessor. It is available in
40 pin DIP chip.
• It uses a 5V DC supply for its
operation.
• The 8086 uses 20-line address
bus. It has a 16-line data bus.
• The 20 lines of the address bus
operate in multiplexed mode.
• The 16-low order address bus
lines have been multiplexed with
data and 4 high-order address bus
lines have been multiplexed with
status signals.
• AD0-AD15: Address/Data bus. These are low order address bus. They
are multiplexed with data. When AD lines are used to transmit
memory address the symbol A is used instead of AD, for example A0-
A15.
• A16-A19: High order address bus. These are multiplexed with status
signals.
• S2, S1, S0: Status pins. These pins are active during T4, T1 and T2
states and is returned to passive state (1, 1, 1 during T3 or Tw (when
ready is inactive).
• A16/S3, A17/S4, A18/S5, A19/S6: The specified address lines are
multiplexed with corresponding status signals. These are the 4
address/status buses. During the first clock cycle, it carries 4- bit
address and later it carries status signals.
• BHE’/S7: Bus High Enable/Status. During T1 it is low. It is used to
enable data onto the most significant half of data bus, D8-D15. 8-bit
device connected to upper half of the data bus use BHE (Active Low)
signal.
• RD’: This is used for read operation. It is an output signal. It is active
when low.
• READY: This is the acknowledgement from the memory or slow
device that they have completed the data transfer.
• INTR: Interrupt Request. This is triggered input. This is sampled
during the last clock cycles of each instruction for determining the
availability of the request. If any interrupt request is found pending,
the processor enters the interrupt acknowledge cycle.
• NMI: Non maskable interrupt. This is an edge triggered input which
results in a type II interrupt. A subroutine is then vectored through an
interrupt vector lookup table which is located in the system memory.
• INTA: Interrupt acknowledge. It is active low (0) during T2, T3 and
Tw of each interrupt acknowledge cycle.
• MN/MX’: Minimum/Maximum. This pin signal indicates what mode
the processor will operate in.
• RQ’/GT1′, RQ’/GT0′: These are the Request/Grant signals used by the
other processors requesting the CPU to release the system bus. When
the signal is received by CPU, then it sends acknowledgment.
RQ/GT0 has a higher priority than RQ/GT1.
• LOCK’: It’s an active low pin. It indicates that other system bus
masters have not been allowed to gain control of the system bus while
LOCK’ is active low (0). The LOCK signal will be active until the
completion of the next instruction.
• RESET: This pin requires the microprocessor to terminate its present
activity immediately. The signal must be active high (1) for at least
four clock cycles.
• TEST’: This examined by a ‘WAIT’ instruction. If the TEST pin goes
low (0), execution will continue, else the processor remains in an idle
state. The input is internally synchronized during each of the clock
cycle on leading edge of the clock.
• CLK: Clock Input. The clock
input provides the basic timing
for processing operation and bus
control activity. It’s an
asymmetric square wave with a
33% duty cycle.
• Vcc: Power Supply (+5V D.C.)
• GND: Ground
• QS1, QS0: Queue Status. These
signals indicate the status of the
internal 8086 instruction queue
according to the table shown
below
• DT/R: Data Transmit/Receive. This pin is required in minimum systems
that want to use an 8286 or 8287 data bus transceiver. The direction of
data flow is controlled through the transceiver.
• DEN: Data enable. This pin is provided as an output enable for the
8286/8287 in a minimum system which uses transceiver. DEN is active
low (0) during each memory and input-output access and for INTA cycles.
• HOLD/HOLDA: HOLD indicates that another master has been requesting
a local bus .This is an active high (1). The microprocessor receiving the
HOLD request will issue HLDA (high) as an acknowledgement in the
middle of a T4 or T1 clock cycle.
• ALE: Address Latch Enable. ALE is provided by the microprocessor to
latch the address into the 8282 or 8283 address latch. It is an active high
(1) pulse during T1 of any bus cycle. ALE signal is never floated, is
always integer.
Architecture • Functional block diagram of 8086,
subdivided into the following two
units:
• Execution unit (EU)
• Bus interface unit (BIU)
• Execution unit: It includes the
ALU, eight 16-bit general purpose
registers, a 16-bit flag register, and a
control unit
• Bus Interface unit: It includes an
adder for address calculations, four-
16 bit segment registers
(CS,DS,SS,ES), a 16-bit instruction
pointer (IP), a six-byte instruction
queue, and bus control logic
Execution Unit:
• The execution unit of the 8086 tells the BIU where to fetch
instructions or data from, decodes instructions, and executes
instructions.
• The EU contains control circuitry, which directs internal operations.
• A decoder in the EU translates instructions fetched from memory into
a series of actions, which the EU carries out.
• The EU has a 16-bit arithmetic logic unit (ALU) which can add,
subtract, AND, OR, XOR, increment, decrement, complement or shift
binary numbers.
• The main functions of EU are:
• Decoding of Instructions
• Execution of instructions
• Steps:
• EU extracts instructions from top of queue in BIU
• Decode the instructions
• Generates operands if necessary
• Passes operands to BIU & requests it to perform read or write bus cycles to
memory or I/O
• Perform the operation specified by the instruction on operands
Bus Interface Unit (BIU):
• The BIU sends out addresses, fetches instructions from memory, reads data
from ports and memory, and writes data to ports and memory.
• In simple words, the BIU handles all transfers of data and addresses on the
buses for the execution unit.
Register Organization
• 8086 has a powerful set of registers known as
general purpose registers and special purpose
registers. All of them are 16-bit registers.
• General purpose registers:
• These registers can be used as either 8-bit registers or
16-bit registers.
• They may be either used for holding data, variables
and intermediate results temporarily or for other
purposes like a counter or for storing offset address
for some particular addressing modes etc.
• Special purpose registers:
• These registers are used as segment registers,
pointers, index registers or as offset storage registers
for particular addressing modes.
• The 8086 registers are classified into the following
types:
• General Data Registers
• Segment Registers
• Pointers
• Index Registers Flag Register
General Data Registers:
• The registers AX, BX, CX and DX are the general purpose 16-bit registers.
• AX is used as 16-bit accumulator. The lower 8-bit is designated as AL and
higher 8-bit is designated as AH.
• AL Can be used as an 8-bit accumulator for 8-bit operation.
• All data register can be used as either 16 bit or 8 bit. BX is a 16 bit register,
but BL indicates the lower 8-bitof BX and BH indicates the higher 8-bit of
BX. The register BX is used as offset storage for forming physical address
in case of certain addressing modes.
• The register CX is used default counter in case of string and loop
instructions.
• DX register is a general purpose register which may be used as an implicit
operand or destination in case of a few instructions.
Segment Registers:
• There are 4 segment registers.
• They are:
• Code Segment Register(CS)
• Data Segment Register(DS)
• Extra Segment Register(ES)
• Stack Segment Register(SS)
• The 8086 architecture uses the concept of segmented memory. 8086
able to address a memory capacity of 1 megabyte and it is byte
organized.
• This 1 megabyte memory is divided into 16 logical segments. Each
segment contains 64 Kbytes of memory
• Code segment register (CS): It is used for addressing memory location in the
code segment of the memory, where the executable program is stored.
• Data segment register (DS): It points to the data segment of the memory
where the data is stored.
• Extra Segment Register (ES) : It also refers to a segment in the memory
which is another data segment in the memory.
• Stack Segment Register (SS): It is used for addressing stack segment of the
memory. The stack segment is that segment of memory which is used to store
stack data.
• While addressing any location in the memory bank, the physical address is
calculated from two parts: Physical address= segment address + offset address
• The first is segment address, the segment registers contain 16-bit segment base
addresses, related to different segment.
• The second part is the offset value in that segment.
Pointers and Index Registers:
• The index and pointer registers are given below:
• IP—Instruction pointer-store memory location of next instruction to be executed
• BP—Base pointer
• SP—Stack pointer
• SI—Source index
• DI—Destination index
8086 flag register and its functions:
• The 8086 flag register contents indicate the results of computation in the ALU. It
also contains some flag bits to control the CPU operations.
• A 16 bit flag register is used in 8086. It is divided into two parts.
• Condition code or status flags Machine control flags : The condition code flag
register is the lower byte of the 16-bit flag register. The condition code flag register
is identical to 8085 flag register, with an additional overflow flag.
• The control flag register is the higher byte of the flag register. It contains three flags
namely direction flag (D), interrupt flag (I) and trap flag (T).
• SF (Sign Flag): This flag is set, when the result of any computation is negative.
For signed computations the sign flag equals the MSB of the result.
• ZF (Zero Flag): This flag is set, if the result of the computation or comparison
performed by the previous instruction is zero.
• PF (Parity Flag): This flag is set to 1, if the lower byte of the result contains even
number of 1’s.
• CF (Carry Flag): This flag is set, when there is a carry out of MSB in case of
addition or a borrow in case of subtraction.
• AF (Auxiliary Carry Flag): This is set, if there is a carry from the lowest nibble,
i.e., bit three during addition, or borrow for the lowest nibble, i.e., bit three,
during subtraction.
• OF (Over flow Flag): This flag is set, if an overflow occurs, i.e., if the result of a
signed operation is large enough to accommodate in a destination register. The
result is of more than 7-bits in size in case of 8-bit signed operation and more than
15-bits in size in case of 16-bit sign operations, and then the overflow will be set.
• TF (Tarp Flag): If this flag is set, the processor enters the single step
execution mode. The processor executes the current instruction and the
control is transferred to the Trap interrupt service routine.
• IF (Interrupt Flag): If this flag is set, the mask able interrupts are
recognized by the CPU, otherwise they are ignored.
• D (Direction Flag): This is used by string manipulation instructions. If
this flag bit is ‘0’, the string is processed beginning from the lowest
address to the highest address, i.e., auto incrementing mode.
Otherwise, the string is processed from the highest address towards the
lowest address, i.e., auto decrementing mode.
Memory Organization
• Segmented Memory Two types of memory organization are used:
• Linear addressing where the entire memory is available to the
processor at all the times (Motorola 68000 family).
• Segmented addressing where the memory space is divided into
several segments and the processor is limited to access program
instructions and data in specific segments.
• 8086 Memory Organization Each memory location 8086 is a byte
while the 8086 is a 16-bits microprocessor.
Memory Segmentation:
• The memory in an 8086 based system is organized as segmented
memory.
• The CPU 8086 is able to access 1MB of physical memory. The
complete 1MB of memory can be divided into 16 segments, each of
64KB size and is addressed by one of the segment register.
• The 16-bit contents of the segment register actually point to the
starting location of a particular segment. The address of the segments
may be assigned as 0000H to F000h respectively.
• To address a specific memory location within a segment, we need an
offset address. The offset address values are from 0000H to FFFFH so
that the physical addresses range from 00000H to FFFFFH.
• If code segment register is 1245H and instruction pointer is 1561H.
Find the physical address.
PA= SR x 10H +OP
PA= 1245H x 10H +1561H
PA=1391B1H
• If code segment register is FFFFH and instruction pointer is 0000H.
Find the physical address.
????
General Bus Operation
• The 8086 has a combined address and data bus commonly referred as a time
multiplexed address and data bus.
• The main reason behind multiplexing address and data over the same pins is the
maximum utilization of processor pins and it facilitates the use of 40 pin standard DIP
package.
• The bus can be de multiplexed using a few latches and transceivers, whenever required.
• Basically, all the processor bus cycles consist of at least four clock cycles. These are
referred to as T1, T2, T3, and T4. The address is transmitted by the processor during T1.
It is present on the bus only for one cycle.
• The negative edge of this ALE pulse is used to separate the address and the data or
status information. In maximum mode, the status lines S0, S1 and S2 are used to
indicate the type of operation.
• Status bits S3 to S7 are multiplexed with higher order address bits and the BHE signal.
Address is valid during T1 while status bits S3 to S7 are valid during T2 through T4.
Minimum and Maximum Mode
• Minimum mode is used when the 8086 microprocessor is operating as
a standalone processor without any external coprocessors or support
chips. In this mode, the 8086 uses a single 8-bit bus for both data and
instructions, and a single 20-bit address bus. The minimum mode
requires a minimum set of support chips, such as clock generator,
address latch, and bus controller.
• Maximum mode is used when the 8086 microprocessor is operating
with one or more external coprocessors or support chips. In this mode,
the 8086 uses a multiplexed bus for data and instructions, and a 20-bit
address bus. The maximum mode requires additional support chips,
such as a bus controller, a clock generator, and a data buffer.
Reduced Instruction Set Architecture
(RISC)
• RISC is the way to make hardware simpler.
• The main idea behind this is to simplify hardware
by using an instruction set composed of a few
basic steps for loading, evaluating, and storing
operations just like a load command will load
data, a store command will store the data.
• Characteristics of RISC
• Simpler instruction, hence simple instruction
decoding.
• Instruction comes undersize of one word.
• Instruction takes a single clock cycle to get
executed.
• More general-purpose registers.
• Simple Addressing Modes.
• Fewer Data types.
• A pipeline can be achieved
• Advantages of RISC
• Simpler instructions: RISC processors use a smaller set of simple
instructions, which makes them easier to decode and execute quickly. This
results in faster processing times.
• Faster execution: Because RISC processors have a simpler instruction set,
they can execute instructions faster than CISC processors.
• Lower power consumption: RISC processors consume less power than CISC
processors, making them ideal for portable devices.
• Disadvantages of RISC
• More instructions required: RISC processors require more instructions to
perform complex tasks than CISC processors.
• Increased memory usage: RISC processors require more memory to store the
additional instructions needed to perform complex tasks.
• Higher cost: Developing and manufacturing RISC processors can be more
expensive than CISC processors.