Basic Computer Organization

Purpose of This Chapter

• In this chapter we introduce a basic
computer and show how its operation can
be specified with register transfer
statements.

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 Instruction Codes

A process is controlled by a program

– A program is a set of instructions that
specify the operations, data, and the
control sequence
– An instruction is stored in binary code that
specifies a sequence of microoperations
– Instruction codes together with data are
stored in memory (Stored Program
Concept)

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 Program statements and
computer instructions

Computer instruction

Field specifying the Field specifying the data

operation to be executed To be operated on

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 Instruction code format
• Instruction code format with two parts :
Op. Code + Address
– Op. Code : specify 16 possible operations(4 bits)
– Address : specify the address of an operand(12 bits)
– If an operation in an instruction code does not need
an operand from memory, the rest of the bits in the
instruction(address field) can be used for other
purpose

15 12 11 0 15 12 11 0

Op. Code Address data

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instruction Not an instruction
 Example

Step Instruction ACC Value Memory Updates

1 LOAD 100 5 —
2 ADD 101 12 (5+7) —
3 STORE 102 12 M[102] ← 12
4 HALT — —

Address Value
0100 5
0101 7
0102 12

ACC => Accumulator 6

 Components of Instructions
• Operations (opcodes)
• Number of operands (Number of data locations)

opcode:add value in src1 to

value in src2 and place the add r1,r2,r3
result in dst.
opcode src1 src2 dst
ADD R1, R2, R3 R1  R2 + R3

• Instruction encodings
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 Number of Operands per
instruction
• No Operands HALT NOP

• 1 operand NOT R4 R4  R4

• 2 operands ADD R1, R2 R1  R1 + R2

• 3 operands ADD R1, R2, R3 R1  R2 + R3

• > 3 operands MADD R4,R1,R2,R3 R4  R1+(R2*R3)

• Each specify one operation and 1,2, 3 or 4 data locations.

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 Instructions are read from memory as
words

• Instructions can be formatted to fit in one or more

memory words.
• An instruction may contain
– An opcode + data (immediate operand)
– An opcode + the address of data (direct addressing)
– An opcode + an address where the address of the data
is found (indirect addressing)
– Data only (location has no instructions)
– An opcode only (register-reference or input/output
instruction)
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 Building A Basic Computer!
The basic computer instructions are
1. Memory
stored in the memory
address contents
The size of each memory word is 16 bits.
Each instruction occupy one word. 0000000000000001 0101010101010101
0000000000000010 1010101010101010
0000000000000011 1100110011001100
2. Program Counter
0000000000000100 0011001100110011
PC 000000000001
0000000000000101 0101010101010011
•A special register inside the CPU.
•Holds the address of the next instruction 0000000000000110 1010101010101010
• to be executed. 0000000000000111 1100110011001100
3. Instruction Register 0000000000001000 0011001100110011

IR 0101
010101010101
•A special register inside the CPU.
•Holds the current instruction being executed. 10
 The address register is connected to the
memory
+1
The Program Counter points to PC
the next address of the program
000000000010
00000001

1. Program Counter Increments

by units of addresses AR 000000000010
2. The next address is put on
the bus and is loaded into the
Direct access to
Address Register
Memory
3. The Bits of the AR are wired
directly to the RAM Address
lines to enable loading the
memory into the Instruction IR. IR 1010101010101010 11
 Direct address

Occurs when the Operand Part explicitly Contains the

Address of Needed Data.

1. Address part of IR is placed on the bus and loaded

back into the AR

2. Address is selected in memory where its corresponding

Data is placed on the bus to be loaded into the Data
Register (DR) and used for requested instructions

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Direct address

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 Indirect address

Occurs When the Operand Contains the Address of the Address

of Needed Data.

1. Address part of IR is placed on the bus and loaded back

into the AR

2. Address is selected in memory and placed on the bus to

be loaded Back into the AR

3. New Address is selected in memory and placed on the bus

to be loaded into the DR to use later

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Indirect address

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 Effective address:
• Effective address: Address where an
operand is physically located

Effective address: 457 Effective address: 1350

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 Direct and Indirect addressing example

Addressing
Mode

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Mano’s Computer Figure 5-4 s0 s1 s2
Bus
Memory Unit
7
4096x16
Address
WRITE READ
AR 1
LD INR CLR
PC 2
LD INR CLR
DR 3
LD INR CLR

Adder E
& Logic
AC 4
LD INR CLR

INPR

IR 5
LD
TR 6
LD INR CLR
OUTR
Clock
LD
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16-bit common bus
Computer System Architecture, Mano, Copyright (C) 1993 Prentice-Hall, Inc.
 Computer Registers
–Accumulator(AC) : takes input from ALU
»The ALU takes input from DR, AC and INPR :
»ADD DR to AC, AND DR to AC
–Note) Input register is not connected to the bus.
–The input register is connected only to the ALU

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 5-2 Computer Registers
• Data Register(DR) : hold the operand(Data) read from memory

• Accumulator Register(AC) : general purpose processing register

• Instruction Register(IR) : hold the instruction read from memory

• Temporary Register(TR) : hold a temporary data during processing

• Address Register(AR) : hold a memory address, 12 bit width

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 5-2 Computer Registers
• Program Counter(PC) :
• Holds the address of the next instruction to be read from me
mory after the current instruction is executed
• Instruction words are read and executed in sequence unless
a branch instruction is encountered
• A branch instruction calls for a transfer to a nonconsecutive i
nstruction in the program
• The address part of a branch instruction is transferred to PC
to become the address of the next instruction
• To read instruction, memory read cycle is initiated, and PC is
incremented by one(next instruction fetch)

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 5-2 Computer Registers
• Input Register(INPR) : receive an 8-bit
character from an input device
• Output Register(OUTR) : hold an 8-bit
character for an output device

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 5-2 Computer Registers
Register Number Register Register
symbol of bits name Function-----------------------
DR 16 Data register Holds memory operands
AR 12 Address register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction register Holds instruction code
PC 12 Program counter Holds address of
instruction
TR 16 Temporary register Holds temporary data
INPR 8 Input register Holds input character
OUTR 8 Output register Holds output character

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 Mano’s Computer: each instruction
occupies one Memory Words
15 12 11 0

• 4-bit opcode Bits 15-12

• How many possible instructions?
– 24=16
• This leaves 12 bits for the address
– How many words of memory?
– 212 = 22•210 = 4K = 4096 16-bit words

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 Mano's simple Computer:
Instructions 0
15 12 11

Any bits other than 0111 and

I 1111 are called memory
reference instructions
000 AND 100 BUN
001 ADD (Branch Unconditional)
010 LDA 101 BSA
(Load Accumulator) (Branch and Store Address)
011 STA 110 ISZ
(Store Accumulator) (Increment and Skip if Zero)

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 Hex Code
Symbol I =0 I =1 Description
AND 0xxx 8xxx And memory word to AC
ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load memory word to AC
STA 3xxx Bxxx Store content of AC in memory
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and Save return address
ISZ 6xxx Exxx Increment and skip if zero
CLA 7800 Clear AC
CLE 7400 Clear E
CMS 7200 Complement AC
CME m 7100 e Comp
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instruction if AC positive
SNA 7008 Skip next instruction if AC negative
SZA 7004 Skip next instruction if AC zero
SZE 7002 Skip next instruction if E is 0
HLT 7001 Halt computer
INP F800 Input character to AC
OUT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on output flag
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ION F080 Interrup
IOF F040 Inter
 5-3. Computer Instruction
•
– 3 Instruction Code Formats : Fig. 5-5 Hex Code
Symbol I =0 I =1 Description
• Memory-reference instruction AND 0xxx 8xxx And memory word to AC
ADD 1xxx 9xxx Add memory word to AC
–Opcode = 000  110 LDA 2xxx Axxx Load memory word to AC
STA 3xxx Bxxx Store content of AC in memory
»I=0 : 0xxx ~ 6xxx, I=1: 8xxx ~Exxx BUN 4xxx Cxxx Branch unconditionally
I=0 : Direct, 15 14 12 11 0 BSA 5xxx Dxxx Branch and Save return address
I=1 : Indirect ISZ 6xxx Exxx Increment and skip if zero
I Opcode Address CLA 7800 Clear AC
CLE 7400 Clear E
CMS 7200 Complement AC
»Register-reference instruction CME m 7100 e Comp
CIR 7080 Circulate right AC and E
–7xxx (7800 ~ 7001) : CLA, CMA, CIL 7040 Circulate left AC and E
15 14 12 11 0 INC 7020 Increment AC
SPA 7010 Skip next instruction if AC positive
0 1 1 1 Register Operation
SNA 7008 Skip next instruction if AC negative
SZA 7004 Skip next instruction if AC zero
–Input-Output instruction SZE
HLT
7002
7001
Skip next instruction if E is 0
Halt computer
–Fxxx(F800 ~ F040) : INP, OUT, ION, SKI, INP
OUT
F800
F400
Input character to AC
Output character from AC
SKI F200 Skip on input flag
15 14 12 11 0
SKO F100 Skip on output flag
1 1 1 1 I/O Operation ION F080 Interrup
IOF F040 Inter
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 Common Bus System
 The basic computer has eight registers, a
memory unit, and a control unit.

• Paths must be provided to transfer information

from one register to another and between
memory and registers

• A more efficient scheme for transferring

information in a system with many registers is to
use a common bus.

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Mano’s Computer Figure 5-4 s0 s1 s2
Bus
Memory Unit
7
4096x16
Address
WRITE READ
AR 1
LD INR CLR
PC 2
LD INR CLR
DR 3
LD INR CLR

Adder E
& Logic
AC 4
LD INR CLR

INPR

IR 5
LD
TR 6
LD INR CLR
OUTR
Clock
LD
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16-bit common bus
Computer System Architecture, Mano, Copyright (C) 1993 Prentice-Hall, Inc.
 Common Bus System
– The connection of the registers and memory of the
basic computer to a common bus system :

– The outputs of seven registers and memory are connected to

the common bus
– The specific output is selected by mux(S0, S1, S2) :
» Memory(7), AR(1), PC(2), DR(3), AC(4), IR(5), TR(6)
» When LD(Load Input) is enable, the particular register
receives the data from the bus
– Control Input : LD, INC, CLR, Write, Read

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 COMMON BUS SYSTEM
Control variables: the bus is controlled by

1- Selection switches for selecting the source of

information

2- Enable switches at the destination device to accept

the information.

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 Control of Bus Selection
• We need each bus selection combination to select one item to
appear on the bus
• For example to select the AR to appear on the bus search the RTL
table for all instructions that have AR as source
• We will find:

• Which can be grouped together as

• Same for memory will give

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