Introduction to CMOS VLSI Design

Test

Outline
Testing Logic Verification Silicon Debug Manufacturing Test Fault Models Observability and Controllability Design for Test Scan BIST Boundary Scan
Test CMOS VLSI Design Slide 2

Testing
Testing is one of the most expensive parts of chips Logic verification accounts for > 50% of design effort for many chips Debug time after fabrication has enormous opportunity cost Shipping defective parts can sink a company Example: Intel FDIV bug Logic error not caught until > 1M units shipped Recall cost $450M (!!!)
Test CMOS VLSI Design Slide 3

Logic Verification
Does the chip simulate correctly? Usually done at HDL level Verification engineers write test bench for HDL Cant test all cases Look for corner cases Try to break logic design Ex: 32-bit adder Test all combinations of corner cases as inputs: 0, 1, 2, 231-1, -1, -231, a few random numbers Good tests require ingenuity
Test CMOS VLSI Design Slide 4

Silicon Debug
Test the first chips back from fabrication If you are lucky, they work the first time If not Logic bugs vs. electrical failures Most chip failures are logic bugs from inadequate simulation Some are electrical failures Crosstalk Dynamic nodes: leakage, charge sharing Ratio failures A few are tool or methodology failures (e.g. DRC) Fix the bugs and fabricate a corrected chip
Test CMOS VLSI Design Slide 5

Shmoo Plots
How to diagnose failures? Hard to access chips Picoprobes Electron beam Laser voltage probing Built-in self-test Shmoo plots Vary voltage, frequency Look for cause of electrical failures
Test CMOS VLSI Design Slide 6

Shmoo Plots
How to diagnose failures? Hard to access chips Picoprobes Electron beam Laser voltage probing Built-in self-test Shmoo plots Vary voltage, frequency Look for cause of electrical failures
Test CMOS VLSI Design Slide 7

Manufacturing Test
A speck of dust on a wafer is sufficient to kill chip Yield of any chip is < 100% Must test chips after manufacturing before delivery to customers to only ship good parts Manufacturing testers are very expensive Minimize time on tester Careful selection of test vectors

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CMOS VLSI Design

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Cheap Testers
If you dont have a multimillion dollar tester: Build a breadboard with LEDs and switches Hook up a logic analyzer and pattern generator Or use a low-cost functional chip tester

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CMOS VLSI Design

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TestosterICs
Ex: TestosterICs functional chip tester Reads test vectors, applies them to your chip, and reports assertion failures

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CMOS VLSI Design

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Stuck-At Faults
How does a chip fail? Usually failures are shorts between two conductors or opens in a conductor This can cause very complicated behavior A simpler model: Stuck-At Assume all failures cause nodes to be stuck-at 0 or 1, i.e. shorted to GND or VDD Not quite true, but works well in practice

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CMOS VLSI Design

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Examples

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CMOS VLSI Design

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Observability & Controllability

Observability: ease of observing a node by watching external output pins of the chip Controllability: ease of forcing a node to 0 or 1 by driving input pins of the chip Combinational logic is usually easy to observe and control Finite state machines can be very difficult, requiring many cycles to enter desired state Especially if state transition diagram is not known to the test engineer
Test CMOS VLSI Design Slide 13

Test Pattern Generation

Manufacturing test ideally would check every node in the circuit to prove it is not stuck. Apply the smallest sequence of test vectors necessary to prove each node is not stuck. Good observability and controllability reduces number of test vectors required for manufacturing test. Reduces the cost of testing Motivates design-for-test

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CMOS VLSI Design

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Test Example
SA1 A3 A2 A1 A0 n1 n2 n3 Y SA0
A3 A2 n2 n1 Y n3 A1 A0

Minimum set:
Test CMOS VLSI Design Slide 15

Test Example
A3 A2 A1 A0 n1 n2 n3 Y SA1 {0110} SA0 {1110}
A3 A2 n2 n1 Y n3 A1 A0

Minimum set:
Test CMOS VLSI Design Slide 16

Test Example
A3 A2 A1 A0 n1 n2 n3 Y SA1 {0110} {1010} SA0 {1110} {1110}
A3 A2 n2 n1 Y n3 A1 A0

Minimum set:
Test CMOS VLSI Design Slide 17

Test Example
A3 A2 A1 A0 n1 n2 n3 Y SA1 {0110} {1010} {0100} SA0 {1110} {1110} {0110}
A3 A2 n2 n1 Y n3 A1 A0

Minimum set:
Test CMOS VLSI Design Slide 18

Test Example
A3 A2 A1 A0 n1 n2 n3 Y SA1 {0110} {1010} {0100} {0110} SA0 {1110} {1110} {0110} {0111}
A3 A2 n2 n1 Y n3 A1 A0

Minimum set:
Test CMOS VLSI Design Slide 19

Test Example
A3 A2 A1 A0 n1 n2 n3 Y SA1 {0110} {1010} {0100} {0110} {1110} SA0 {1110} {1110} {0110} {0111} {0110}
A3 A2 n2 n1 Y n3 A1 A0

Minimum set:
Test CMOS VLSI Design Slide 20

Test Example
A3 A2 A1 A0 n1 n2 n3 Y SA1 {0110} {1010} {0100} {0110} {1110} {0110} SA0 {1110} {1110} {0110} {0111} {0110} {0100}
A3 A2 n2 n1 Y n3 A1 A0

Minimum set:
Test CMOS VLSI Design Slide 21

Test Example
A3 A2 A1 A0 n1 n2 n3 Y SA1 {0110} {1010} {0100} {0110} {1110} {0110} {0101} SA0 {1110} {1110} {0110} {0111} {0110} {0100} {0110}
A3 A2 n2 n1 Y n3 A1 A0

Minimum set:
Test CMOS VLSI Design Slide 22

Test Example
A3 A2 A1 A0 n1 n2 n3 Y SA1 {0110} {1010} {0100} {0110} {1110} {0110} {0101} {0110} SA0 {1110} {1110} {0110} {0111} {0110} {0100} {0110} {1110}
A3 A2 n2 n1 Y n3 A1 A0

Minimum set: {0100, 0101, 0110, 0111, 1010, 1110}

Test CMOS VLSI Design Slide 23

Design for Test

Design the chip to increase observability and controllability If each register could be observed and controlled, test problem reduces to testing combinational logic between registers. Better yet, logic blocks could enter test mode where they generate test patterns and report the results automatically.

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CMOS VLSI Design

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Scan
Convert each flip-flop to a scan register SCAN Only costs one extra multiplexer SI D Normal mode: flip-flops behave as usual Scan mode: flip-flops behave as shift register
scan-in Flop Flop

CLK Flop
Flop Flop outputs Flop Flop scanout

Contents of flops can be scanned out and new values scanned in

Test

Flop

inputs Flop

Logic Cloud Flop

Flop

Logic Cloud

Flop

CMOS VLSI Design

Flop

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Scannable Flip-flops
SCAN SCAN CLK Flop D (a) SI 0 1 D Q SI (b) d SCAN d D d s SI s X Q Q X Q Q

s (c)

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Built-in Self-test
Built-in self-test lets blocks test themselves Generate pseudo-random inputs to comb. logic Combine outputs into a syndrome With high probability, block is fault-free if it produces the expected syndrome

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PRSG
Linear Feedback Shift Register Shift register with input taken from XOR of state Pseudo-Random Sequence Generator
Step
CLK Flop Flop Flop D Q[0] D Q[1] D Q[2]

Q 111

0 1 2 3 4 5 6

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CMOS VLSI Design

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PRSG
Linear Feedback Shift Register Shift register with input taken from XOR of state Pseudo-Random Sequence Generator
Step
CLK Flop Flop Flop D Q[0] D Q[1] D Q[2]

Q 111 110

0 1 2 3 4 5 6

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7 CMOS VLSI Design

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PRSG
Linear Feedback Shift Register Shift register with input taken from XOR of state Pseudo-Random Sequence Generator
Step
CLK Flop Flop Flop D Q[0] D Q[1] D Q[2]

Q 111 110 101

0 1 2 3 4 5 6

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CMOS VLSI Design

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PRSG
Linear Feedback Shift Register Shift register with input taken from XOR of state Pseudo-Random Sequence Generator
Step
CLK Flop Flop Flop D Q[0] D Q[1] D Q[2]

Q 111 110 101 010

0 1 2 3 4 5 6 7

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CMOS VLSI Design

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PRSG
Linear Feedback Shift Register Shift register with input taken from XOR of state Pseudo-Random Sequence Generator
Step
CLK Flop Flop Flop D Q[0] D Q[1] D Q[2]

Q 111 110 101 010 100

0 1 2 3 4 5 6 7

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CMOS VLSI Design

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PRSG
Linear Feedback Shift Register Shift register with input taken from XOR of state Pseudo-Random Sequence Generator
Step
CLK Flop Flop Flop D Q[0] D Q[1] D Q[2]

Q 111 110 101 010 100 001

0 1 2 3 4 5 6 7

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CMOS VLSI Design

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PRSG
Linear Feedback Shift Register Shift register with input taken from XOR of state Pseudo-Random Sequence Generator
Step
CLK Flop Flop Flop D Q[0] D Q[1] D Q[2]

Q 111 110 101 010 100 001 011

0 1 2 3 4 5 6 7

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CMOS VLSI Design

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PRSG
Linear Feedback Shift Register Shift register with input taken from XOR of state Pseudo-Random Sequence Generator
Step
CLK Flop Flop Flop D Q[0] D Q[1] D Q[2]

Q 111 110 101 010 100 001 011 111 (repeats)

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0 1 2 3 4 5 6 7

Test

CMOS VLSI Design

BILBO
Built-in Logic Block Observer Combine scan with PRSG & signature analysis
D[0] C[0] C[1] D[1] D[2]

Flop

Flop

SI

1 0

Q[0]

Q[1]

PRSG

Logic Cloud

Signature Analyzer

MODE Scan Test Reset Normal

C[1] 0 0 1 1

Flop

Q[2] / SO

C[0] 0 1 0 1

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CMOS VLSI Design

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Boundary Scan
Testing boards is also difficult Need to verify solder joints are good Drive a pin to 0, then to 1 Check that all connected pins get the values Through-hold boards used bed of nails SMT and BGA boards cannot easily contact pins Build capability of observing and controlling pins into each chip to make board test easier

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CMOS VLSI Design

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Boundary Scan Example

PackageInterconnect

CHIP B

CHIP C

Serial Data Out

CHIP A

CHIP D

IO pad and Boundary Scan Cell Serial Data In

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CMOS VLSI Design

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Boundary Scan Interface

Boundary scan is accessed through five pins TCK: test clock TMS: test mode select TDI: test data in TDO: test data out TRST*: test reset (optional) Chips with internal scan chains can access the chains through boundary scan for unified test strategy.

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CMOS VLSI Design

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Summary
Think about testing from the beginning Simulate as you go Plan for test after fabrication If you dont test it, it wont work! (Guaranteed)

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CMOS VLSI Design

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