FPGA (Field Programmable Gate Arrays ) overview
Lecture Outline
Available choice for digital designer FPGA a choice for designers Interconnection Framework
FPGAs and CPLDs
Field programmability and programming technologies
SRAM, Anti-fuse, EPROM and EEPROM
Design steps Commercially available devices
Xilinx Altera MAX
Why do we need FPGA
Designers Choice
Digital designer has various options
SSI (small scale integrated circuits) or MSI (medium scale integrated circuits) components
Difficulties arises as design size increases Interconnections grow with complexity resulting in a prolonged testing phase
Simple programmable logic devices
PALs (programmable array logic) PLAs (programmable logic array) Architecture not scalable; Power consumption and delays play an important role in extending the architecture to complex designs Implementation of larger designs leads to same difficulty as that of discrete components
Designers Choice
Quest for high capacity; Two choices available
MPGA (Masked Programmable Logic Devices)
Customized during fabrication Low volume expensive
FPGA (Field Programmable Logic Devices)
Customized by end user Implements multi-level logic function
Comparison
A look on FPGA as designer's choice
Two dimensional array of customizable logic block placed in an interconnect array Like PLDs programmable at users site Like MPGAs, implements thousands of gates of logic in a single device
Employs logic and interconnect structure capable of implementing multi-level logic Scalable in proportion with logic removing many of the size limitations of PLD derived two level architecture
FPGAs offer the benefit of both MPGAs and PLDs!
Interconnection Framework
Granularity and interconnection structure has caused a split in the industry FPGA
Fine grained Variable length interconnect segments Timing in general is not predictable Timing extracted after placement and route
Interconnection Framework
CPLD
Coarse grained (SPLD like blocks) Programmable crossbar interconnect structure Interconnect structure uses continuous metal lines The switch matrix may or may not be fully populated Timing predictable if fully populated Architecture does not scale well
FPGA
Based on the principle of functional completeness FPGA: Functionally complete elements (Logic Blocks) placed in an interconnect framework Interconnection framework comprises of wire segments and switches; Provide a means to interconnect logic blocks Circuits are partitioned to logic block size, mapped and routed
Basic elements of FPGA
Basic building blocks Interconnects
Field Programmability
Field programmability is achieved through switches (Transistors controlled by memory elements or fuses) Switches control the following aspects
Interconnection among wire segments Configuration of logic blocks
Distributed memory elements controlling the switches and configuration of logic blocks are together called Configuration Memory
Technology of Programmable Elements
Vary from vendor to vendor. All share the common property: Configurable in one of the two positions ON or OFF Can be classified into three categories:
SRAM based Fuse based EPROM/EEPROM/Flash based
Desired properties:
Minimum area consumption Low on resistance; High off resistance Low parasitic capacitance to the attached wire Reliability in volume production
SRAM Programming Technology
Employs SRAM (Static RAM) cells to control pass transistors and/or transmission gates SRAM cells control the configuration of logic block as well Volatile Needs an external storage Needs a power-on configuration mechanism In-circuit re-programmable Lesser configuration time Occupies relatively larger area
Design Steps Involved in Designing With FPGAs
Understand and define design requirements Design description Behavioral simulation (Source code interpretation) Synthesis Functional or Gate level simulation Implementation Fitting Place and Route Timing or Post layout simulation Programming, Test and Debug
Commercially Available Devices
Architecture differs from vendor to vendor Characterized by
Structure and content of logic block Structure and content of routing resources
To examine, look at some of available devices
FPGA: Xilinx (XC4000) CPLD: Altera (MAX 5K)
