Architecturing RISC/DSP/VLIW and Array/Vector parallel processors including complete SW development tools set: compilers, optimizing Assemblers, clock-accurate SW models, etc
SOC/ASIC/ASSP Architecture for Multimedia and Networking – bandwidth and performance optimization, DDRx DRAM controllers, arbitration, SW/HW balancing, multiple Data Bus Standards, VLSI design and verification
Wide experience in specifying, implementing and performance optimizing of Voice, Audio and Video processing systems using the most of exisiting RISC and DSP platforms
Deep knowledge in Image Processing, Digital TV Standards and HD/SD interfaces worldwide, Content Security (DVB-CA, SVP, TPM, DRM, IPsec
Architecturing RISC/DSP/VLIW and Array/Vector parallel processors including complete SW development tools set: compilers, optimizing Assemblers, clock-accurate SW models, etc
SOC/ASIC/ASSP Architecture for Multimedia and Networking – bandwidth and performance optimization, DDRx DRAM controllers, arbitration, SW/HW balancing, multiple Data Bus Standards, VLSI design and verification
Wide experience in specifying, implementing and performance optimizing of Voice, Audio and Video processing systems using the most of exisiting RISC and DSP platforms
Deep knowledge in Image Processing, Digital TV Standards and HD/SD interfaces worldwide, Content Security (DVB-CA, SVP, TPM, DRM, IPsec
