74 hc hct393

74HC393; 74HCT393
Dual 4-bit binary ripple counter
Rev. 5 — 1 April 2014 Product data sheet
1. General description
The 74HC393; 7474HCT393 is a dual 4-stage binary ripple counter. Each counter
features a clock input (nCP), an overriding asynchronous master reset input (nMR) and 4
buffered parallel outputs (nQ0 to nQ3). The counter advances on the HIGH-to-LOW
transition of nCP. A HIGH on nMR clears the counter stages and forces the outputs LOW,
independent of the state of nCP. Inputs include clamp diodes. This enables the use of
current limiting resistors to interface inputs to voltages in excess of VCC.
2. Features and benefits
 Input levels:
 For 74HC393: CMOS level
 For 74HCT393: TTL level
 Complies with JEDEC standard no. 7A
 ESD protection:
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V.
 Two 4-bit binary counters with individual clocks
 Divide by any binary module up to 28 in one package
 Two master resets to clear each 4-bit counter individually
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC393N 40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
74HCT393N
74HC393D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
74HCT393D
74HC393DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body width
5.3 mm
SOT337-1
74HCT393DB
74HC393PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; body
width 4.4 mm
SOT402-1
74HCT393PW
74HC393BQ 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin
quad flat package; no leads; 14 terminals;
body 2.5  3  0.85 mm
SOT762-1
74HCT393BQ

NXP Semiconductors 74HC393; 74HCT393
4. Functional diagram
3
4
5
6
1Q0
1Q1
1Q2
1Q3
11
10
9
8
2Q0
2Q1
2Q2
2Q3
001aad532
1CP
1
1
2
1MR
2CP
2
13
12
2MR
CTR4
CT = 0
+
CTR4
CT = 0
2
1
12
13
+
Fig 1. Logic symbol Fig 2. IEC logic symbol
3
4
5
6
11
10
9
8
0
3
0
3
001aad533
CT
CT
3
4
5
6
1Q0
1Q1
1Q2
1Q3
11
10
9
8
2Q0
2Q1
2Q2
2Q3
001aad534
1CP
4-BIT
BINARY
RIPPLE
COUNTER
4-BIT
BINARY
RIPPLE
COUNTER
1
2
1MR
2CP
13
12
2MR
0
15
14
13
12
1 2 3 4
11 10 9 8
Fig 3. Functional diagram Fig 4. State diagram
5
6
7
001aad535
74HC_HCT393 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 1 April 2014 2 of 21

CP T
MR
Fig 5. Logic diagram (one counter)
5. Pinning information
5.1 Pinning
Q
Q0 Q1 Q2 Q3
001aad536
FF
1
RD
Q
FF
2
RD
T
Q
FF
3
RD
T
Q
FF
4
RD
T
Fig 6. Pin configuration DIP14 and SO14
+
+7

3 9
05 3
4 05
4 4
4 4
4 4
*1' 4
DDD


+
+7

3 9
05 3
4 05
4 4
4 4
4 4
*1' 4
DDD

3
9

WHUPLQDO
LQGH[DUHD
05 3

4 05

4 4
9

4 4

4 4
DDD
+
+7

*1'
4
7UDQVSDUHQWWRSYLHZ
Fig 7. Pin configuration SSOP14 and TSSOP14 Fig 8. Pin configuration DHVQFN14
5.2 Pin description
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to VCC.
Table 2. Pin description
Symbol Pin Description
1CP 1 clock input (HIGH-to-LOW, edge-triggered)
1MR 2 asynchronous master reset input (active HIGH)
1Q0 3 flip-flop output
GND 7 ground (0 V)
2MR 12 asynchronous master reset input (active HIGH)
2CP 13 clock input (HIGH-to-LOW, edge-triggered)
VCC 14 supply voltage

6. Functional description
Table 3. Count sequence for one counter [1]
Count Output
nQ0 nQ1 nQ2 nQ3
0 L L L L
1 H L L L
2 L H L L
3 H H L L
4 L L H L
5 H L H L
6 L H H L
7 H H H L
8 L L L H
9 H L L H
10 L H L H
11 H H L H
12 L L H H
13 H L H H
14 L H H H
15 H H H H
[1] H = HIGH voltage level; L = LOW voltage level.
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7 V
IIK input clamping current VI 0.5 V or VI VCC + 0.5 V - 20 mA
IOK output clamping current VO 0.5 V or VO VCC + 0.5 V - 20 mA
IO output current VO = 0.5 V to VCC + 0.5 V - 25 mA
ICC supply current - ±50 mA
IGND ground current - 50 mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation DIP14 package [1] - 750 mW
SO14, SSOP14, TSSOP14 and
DHVQFN14 package
[1] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 C.
[2] For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.
For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C.
[2] - 500 mW

8. Recommended operating conditions
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions 74HC393 74HCT393 Unit
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VI input voltage 0 - VCC 0 - VCC V
VO output voltage 0 - VCC 0 - VCC V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
9. Static characteristics
Min Typ Max Min Typ Max
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
74HC393
VIH HIGH-level
input voltage
VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage
VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level
output voltage
VI = VIH or VIL
IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V
IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage
VI = VIH or VIL
IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
II input leakage
current
VI = VCC or GND;
VCC = 6.0 V
- - 0.1 - 0.1 - 0.1 A
ICC supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
- - 8.0 - 80 - 160 A

Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
CI input
capacitance
- 3.5 - pF
74HCT393
VIH HIGH-level
input voltage
VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage
VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V
IO = 6 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A - 0 0.1 - 0.1 - 0.1 V
IO = 6.0 mA - 0.15 0.26 - 0.33 - 0.4 V
II input leakage
current
VI = VCC or GND;
VCC = 5.5 V
- - 0.1 - 1.0 - 1.0 A
ICC supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
- - 8.0 - 80 - 160 A
ICC additional
supply current
VI = VCC  2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V; IO = 0 A
per input pin; nCP - 40 144 - 180 - 196 A
per input pin; nMR - 100 360 - 450 - 490 A
CI input
capacitance
- 3.5 - pF

10. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 11.
74HC393
tpd propagation
delay
nCP to nQ0; see Figure 9 [1]
VCC = 2.0 V - 41 125 - 155 - 190 ns
VCC = 4.5 V - 15 25 - 31 - 38 ns
VCC = 5 V; CL = 15 pF - 12 - - - - - ns
VCC = 6.0 V - 12 21 - 26 - 32 ns
nQx to nQ(x1);
[1]
see Figure 9
VCC = 2.0 V - 14 45 - 55 - 70 ns
VCC = 4.5 V - 5 9 - 11 - 14 ns
VCC = 5 V; CL = 15 pF - 5 - - - - - ns
VCC = 6.0 V - 4 8 - 9 - 12 ns
tPHL HIGH to
LOW
propagation
delay
nMR to nQx; see Figure 10
VCC = 2.0 V - 39 140 - 175 - 210 ns
VCC = 4.5 V - 14 28 - 35 - 42 ns
VCC = 5 V; CL = 15 pF - 11 - - - - - ns
VCC = 6.0 V - 11 24 - 30 - 36 ns
tt transition
time
Qn; see Figure 9 [2]
VCC = 2.0 V - 19 75 - 95 - 110 ns
VCC = 4.5 V - 7 15 - 19 - 22 ns
VCC = 6.0 V - 6 13 - 16 - 19 ns
tW pulse width nCP HIGH or LOW;
see Figure 9
VCC = 2.0 V 80 17 - 100 - 120 - ns
VCC = 4.5 V 16 6 - 20 - 24 - ns
VCC = 6.0 V 14 5 - 17 - 20 - ns
nMR HIGH; see Figure 10
VCC = 2.0 V 80 19 - 100 - 120 - ns
VCC = 4.5 V 16 7 - 20 - 24 - ns
VCC = 6.0 V 14 6 - 17 - 20 - ns
trec recovery
time
nMR to nCP; see Figure 10
VCC = 2.0 V 5 3 - 5 - 5 - ns
VCC = 4.5 V 5 1 - 5 - 5 - ns
VCC = 6.0 V 5 1 - 5 - 5 - ns

Table 7. Dynamic characteristics …continued
fclk(max) maximum
clock
frequency
see Figure 9
VCC = 2.0 V 6 30 - 5 - 4 - MHz
VCC = 4.5 V 30 90 - 24 - 20 - MHz
VCC = 5 V; CL = 15 pF - 99 - - - - - MHz
VCC = 6.0 V 35 107 - 28 24 - MHz
CPD power
dissipation
capacitance
CL = 50 pF; f = 1 MHz;
VI = GND to VCC
[3] - 23 - - - - - pF
74HCT393
tpd propagation
delay
nCP to nQ0; see Figure 9 [1]
VCC = 4.5 V - 15 25 - 31 - 38 ns
VCC = 5 V; CL = 15 pF - 20 - - - - - ns
nQx to nQ(x1);
[1]
see Figure 9
VCC = 4.5 V - 6 10 - 13 - 15 ns
VCC = 5 V; CL = 15 pF - 6 - - - - - ns
tPHL HIGH to
LOW
propagation
delay
nMR to nQx; see Figure 10
VCC = 4.5 V - 18 32 - 40 - 48 ns
VCC = 5 V; CL = 15 pF - 15 - - - - - ns
tt transition
time
Qn; see Figure 9 [2]
VCC = 4.5 V - 7 15 - 19 - 22 ns
tW pulse width nCP HIGH or LOW;
see Figure 9
VCC = 4.5 V 19 11 - 24 - 29 - ns
nMR HIGH; see Figure 10
VCC = 4.5 V 16 6 - 20 - 24 - ns
trec recovery
time
nMR to nCP;
see Figure 10
VCC = 4.5 V 5 0 - 5 - 5 - ns
fclk(max) maximum
clock
frequency
see Figure 9
VCC = 4.5 V 27 48 - 22 - 18 - MHz
VCC = 5 V; CL = 15 pF - 53 - - - - - MHz

Table 7. Dynamic characteristics …continued
CPD power
dissipation
capacitance
CL = 50 pF; f = 1 MHz;
VI = GND to VCC  1.5 V
[3] - 25 - - - - - pF
[1] tpd is the same as tPLH and tPHL.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL  VCC2  fo) = sum of outputs.
10.1 Waveforms
VM
tPHL
VI
input nCP
GND
VOH
output nQx
VOL
Measurement points are given in Table 8.
1/fmax
tTHL tTLH
001aad537
VM
tPLH
Fig 9. Propagation delays clock (nCP) to output (nQx), the output transition times and the maximum clock
frequency
Table 8. Measurement points
Type Input Output
VM VM
74HC393 0.5VCC 0.5VCC
74HCT393 1.3 V 1.3 V

VI
input nMR VM
GND
VI
input nCP
GND
VOH
output nQx
VOL
001aad538
trec
VM
tPHL
VM
tW
Fig 10. Propagation delays clock (nCP) to output (nQx), pulse width master reset (nMR), and recovery time
master reset (nMR) to clock (nCP)

90 % 90 %
VI
negative
pulse
0 V
VI
positive
pulse
0 V
tr
tf
tf
tr
10 % 10 %
a. Input pulse definition
001aac221
tW
VM VM
90 %
VM VM
tW
10 %
CL
mna101
VCC
VI VO
GENERATOR D.U.T.
RT
PULSE
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
b. Test circuit
Fig 11. Test circuit for measuring switching times
Table 9. Test data
Type Input Load
VI tr, tf CL
74HC393 VCC 6 ns 15 pF, 50 pF
74HCT393 3 V 6 ns 15 pF, 50 pF

11. Package outline
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
c
w M
bp
D
Z
e
8
7
14
1
y
pin 1 index
0 2.5 5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
X
E
HE
Q
A
A A 1
θ
A2
Lp
L
detail X
v M A
(A 3 )
A
max. A1 A2 A3 bp c D(1) E(1) e HE L Lp Q v w y Z (1) θ
mm
inches
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
0.069
0.010
0.004
0.057
0.049
0.01
0.019
0.014
0.0100
0.0075
0.35
0.34
0.16
0.15
0.05
1.05
0.041
0.244
0.228
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
OUTLINE REFERENCES
VERSION
1.27
IEC JEDEC JEITA
SOT108-1
076E06 MS-012
Fig 12. Package outline SOT108-1 (SO14)
0.7
0.3 8
0
0.25 0.1
0.028
0.012
0.01 0.01
0.004
0.25
EUROPEAN
PROJECTION ISSUE DATE
6.2
5.8
0.7
0.6
o
o
1.0
0.4
0.028
0.024
0.039
0.016
99-12-27
03-02-19

DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1
L
seating plane
b1
e
D
Z
14
pin 1 index
1
8
7
b
0 5 10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT A
max.
ME
(e 1 )
MH
c
A
A1
w M
A2
E
Z (1) E e L MH
A
min.
A
max. b max.
1 2 b (1) (1) 1 c D
mm
inches
1.73
1.13
0.53
0.38
0.36
0.23
19.50
18.55
4.2 0.51 3.2 2.2
0.068
0.044
0.021
0.015
0.77
0.73
0.014
0.009
0.17 0.02 0.13 0.087
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
OUTLINE REFERENCES
VERSION
6.48
6.20
0.26
0.24
IEC JEDEC JEITA
SOT27-1
050G04 MO-001 SC-501-14
Fig 13. Package outline SOT27-1 (DIP14)
e1 ME w
8.25
7.80
10.0
8.3
2.54 7.62 0.254
0.32
0.31
0.39
0.33
0.1 0.3 0.01
EUROPEAN
99-12-27
03-02-13
3.60
3.05
0.14
0.12

SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1
14 8
pin 1 index
1 7
bp
D
Z
e
y
DIMENSIONS (mm are the original dimensions)
w M
E
HE
c
X
v M A
A
θ
A
A1
A2
Q
Lp
L
detail X
(A 3 )
0 2.5 5 mm
scale
A
max.
UNIT A1 A2 A3 bp c D(1) E(1) e HE L Lp Q v w y Z θ
mm 0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
2
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE REFERENCES
VERSION
7.9
7.6
1.03
0.63
0.9
0.7
0.65 1.25 0.2
IEC JEDEC JEITA
SOT337-1
MO-150
Fig 14. Package outline SOT337-1 (SSOP14)
(1)
1.4
0.9
8
0
0.13 0.1 o
EUROPEAN
o
99-12-27
03-02-19

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
D
Z
y
14 8
pin 1 index
1 7
e
w M
bp
X
θ
v M A
A
A1
A2
Lp
Q
L
E
HE
detail X
A
(A 3 )
c
0 2.5 5 mm
scale
A
max.
UNIT A1 A2 A3 bp c D(1) E (2) e HE L Lp Q v w y Z (1) θ
mm 0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.25
1.1
Notes
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE REFERENCES
VERSION
0.65
IEC JEDEC JEITA
SOT402-1 MO-153
Fig 15. Package outline SOT402-1 (TSSOP14)
0.72
0.38
8
0
0.75
0.50
1 0.2 0.13 0.1 o
EUROPEAN
6.6
6.2
0.4
0.3
o
99-12-27
03-02-18

DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
terminal 1
index area
terminal 1
index area
A
A1
D
e1
B A
E
C
e y1 C y
2 6
1 7
13 9
Dh
v M B
w M
e
b
8
C A
C
0 2.5 5 mm
L
Eh
14
scale
A(1)
max.
E(1)
D(1)
UNIT A1 b c
Eh e y
0.30
0.18
mm 3.1
Dh
1.65
1.35
2.6
2.4
1.15
0.85
0.05
0.00
1 0.5
0.2
2.9
Note
OUTLINE REFERENCES
VERSION
e1
2
IEC JEDEC JEITA
SOT762-1 - - - MO-241 - - -
Fig 16. Package outline SOT762-1 (DHVQFN14)
y1
0.05 0.1
SOT762-1
c
detail X
X
EUROPEAN
L
0.5
0.3
v
0.1
w
0.05
02-10-17
03-01-27

12. Abbreviations
Table 10. Abbreviations
Acronym Description
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
13. Revision history
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT393 v.5 20140401 Product data sheet - 74HC_HCT393 v.4
Modifications: • The conditions for CPD have been corrected (errata).
74HC_HCT393 v.4 20130516 Product data sheet - 74HC_HCT393 v.3
Modifications: • The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
74HC_HCT393 v.3 20050906 Product data sheet - 74HC_HCT393_CNV v.2
74HC_HCT393_CNV v.2 19901201 Product specification - -

14. Legal information
14.1 Data sheet status
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
14.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com

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