ASIC Design Flow | Physical Design | VLSI
Download as PPTX, PDF•5 likes•3,456 views
This document provides an overview of the ASIC design process, which includes the following main steps: 1. Front-end design including market research, specification, architecture, and RTL design. 2. Verification of the RTL code by verification engineers. 3. Synthesis of the RTL code into a gate-level netlist, followed by equivalence checking. 4. Physical design including placement and routing of standard cells, followed by extraction of parasitic components and timing analysis. 5. Physical verification including design rule checking and layout vs schematic checking.
ASIC Design Flow | Physical Design | VLSI
- 1. ASIC DESIGN
- 2. ■ ASIC stands for “Application specific integrated circuit” ■ An ASIC (application-specific integrated circuit) is a microchip designed for a special application, such as a particular kind of transmission protocol or a hand-held computer. You might contrast it with general integrated circuits, such as the microprocessor and the random access memory chips in your PC. ASICs are used in a wide-range of applications, including auto emission control, environmental monitoring, and personal digital assistants. ■ An ASIC can be pre-manufactured for a special application or it can be custom manufactured (typically using components from a "building block" library of components) for a particular customer application. ■ We are talking about designing chips like shown below in the image. The black thingies with the white text on it are integrated circuits or chips.
- 3. Front End Back End
- 4. 1. RTL – RegisterTransfer Level ■ MRD (Market Research Department) – MRD collects the information from the market and finds out what is the requirement in the market. It is necessary to have a MRD team because you can’t start working on anything without knowing whether it is needed in the market or not. ■ Specification – The required specification for the required product is decide by specification team. (Speed, Size, Power requirement, Pin width information etc) ■ Architecture – Complete layout of the required product is made. ■ Micro-Architecture – The complete layout is divided into sub block layout (because the complete design is big). Now each block is given to RTL engineer. ■ RTL Engineer – RTL engineer writes RTL code for all sub block using different tools. The output file generated by tool is known is netlist whose extension is (.v) • RTL code can be write inVerilog as well asVHDL • VHDL language is not in use anymore. • Tools used are –Verlog XLCadence, Synopsy’sVCS, Model Sim Note – Netlist - In electronic design, a netlist is a description of the connectivity of an electronic circuit.
- 5. 2.Verification Engineer ■ Verification engineer search for the bug in the netlist (.v) if there is any then the netlist is send back to RTL engineer to debug the code. And this loop remains continues unless the bug is removed. ■ Once the netlist is verified, it is send to check whether our design meets the design goal or not. Design goal were already specified by the specification team. ■ If the design goal is met then the netlist is send for synthesis. If not, then it is send back to verification engineer.
- 6. 3. Synthesis ■ Synthesis – This process is conducted on the RTL code. This is the process whereby the RTL code is converted into logic gates. The logic gate produced is the functional equivalent of the RTL code as intended in the design. It is the process of converting the RTL code (.v)/netlist into gate level netlist (GLN) or optimized gate level netlist. The input required for synthesis is netlist, standard cell library file, and constraint file. Its output is gate level netlist. ■ LEC (Logical Equivalence Check) – It compare the netlist (.v) and gate level netlist to check whether the functionality of both are same or not after synthesis.Tool used is “Conformal” ■ Pre-layout STA - Static timing analysis is performed before the layout is created. Since the layout is not created, the wire delay, cell delay etc are not included during timing analysis. The tool used for Pre-layout STA is Prime time,Tempus. Note – Standard Cell - A standard cell library is a collection of low-level electronic logic functions such as AND, OR, INVERT, flip-flops, latches, and buffers. These cells are realized as fixed-height, variable-width full-custom cells. Constraint – Parameters which should not be change. Constraint file contains these parameters with their values. Wire delay – Due to the resistance of wire, the signal gets delayed.
- 7. 4. Physical Design ■ APR – Automatic Place & Route 1. Floor Plan – Plan the core, die etc 2. Power Plan – Power lines are placed (Horizontally &Vertically) 3. Placement – Place the macros and standard cells. 4. CTS – Distribute the clock to all sequential circuit. 5. Routing – Connect all the macros, cell using conductor with the power lines. Tools used for APR is – Encounter/Innovus ■ LEC (Logical Equivalence Check) – It compare the GLN (.v) and netlist obtained from APR to check whether the functionality of both are same or not after APR.Tool used is “Conformal” ■ PEX (Parasitic Extraction) – The conductor (copper wire) used for routing purpose has parasitic (Resistance and capacitance, RC) due to which there will be some delay in wire called wire delay so in PEX we find the value RC. Tool used is Synopsys, Star XC. The required input file is netlist obtained from APR, Rule file & mapping file, both the rule file and mapping file is provided by the fabrication house. The output of PEX is SPEF/SDF file. ■ Post-layout STA – Static timing analysis is performed. The inputs are netlist(.v), library file, constraint file(.sdc) and SPEF.The output is GDS.Tool used is Prime time,Tempus.
- 8. ■ PhysicalVerification –Various verification tests are performed such as 1. Design Rule Check (DRC) – Spacing,Width, Overlapping etc. are check Tool used is Calibre (Mentor Graphic),Assura (Cadence) &Virtuso (Cadence) Input file is GDS & Rule deck file (contain all the restriction/limitation) Output file is DRC error summary, GDS-II, Report 2. Layout v/s Schematic (LVS) – Compare the connection of layout (GDS) and schematic (.v). Input file is GDS, Source netlist (.v) & Rule deck file (contain all the restriction/limitation).Output file is LVS error summary, GDS-II, Report.There can be 4 errors – Open, Short, Mismatch, Floating pins. 3. Electrical Rule Check (ERC) – It varies company to company. ■ Tapeout – GDS-II file is send to fabrication house.
- 9. Some usefulVLSI Blogs - ■ https://www.vlsiguide.com/ ■ https://www.vlsisystemdesign.com/inception-content-vsd/ ■ http://www.vlsi-expert.com/ ■ http://vlsi.pro/ ■ http://www.signoffsemi.com/blog/ ■ http://www.vlsi-basics.com/ ■ http://mantravlsi.blogspot.com/ ■ http://vlsi-soc.blogspot.com/ ■ http://asicpd.blogspot.com/ ■ https://vlsiuniverse.blogspot.com/ ■ http://www.vlsijunction.com/ ■ https://vlsipd.blogspot.com/ ■ http://vlsichip.blogspot.com/ ■ http://asicforphysicaldesign.blogspot.com/ ■ http://www.vlsifacts.com/ All Links are available in the description.
- 10. THANKYOU ■ Download the ppt from the description. ■ Let me know on what other topics you need notes.