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![CMOS Inverter Transfer Characteristics
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Cmos design
The document describes the CMOS design and fabrication process. Key points include: - CMOS uses complementary n-type and p-type MOS transistors to reduce power consumption. - Transistors are built on a silicon substrate using dopants to create n-type and p-type regions. PN junctions form diodes and MOS capacitors. - The CMOS fabrication process involves layering and patterning of silicon, oxides, and metals through steps like oxidation, lithography, etching, and doping.
Cmos design
- 1.
- 2. Introduction Integrated circuits: manytransistors on one chip. Very Large Scale Integration (VLSI): very many Metal Oxide Semiconductor (MOS) transistor Fast, cheap, low-power transistors Complementary: mixture of n- and p-type leads to less power How to build your own simple CMOS chip CMOS transistors Building logic gates from transistors Transistor layout and fabrication
- 3. Silicon Lattice Transistors arebuilt on a silicon substrate Silicon is a Group IV material Forms crystal lattice with bonds to four neighbors Si SiSi Si SiSi Si SiSi
- 4. Dopants Silicon is asemiconductor Pure silicon has no free carriers and conducts poorly Adding dopants increases the conductivity Group V: extra electron (n-type) Group III: missing electron, called hole (p-type) As SiSi Si SiSi Si SiSi B SiSi Si SiSi Si SiSi - + + -
- 5. p-n Junctions A junctionbetween p-type and n-type semiconductor forms a diode. Current flows only in one direction p-type n-type anode cathode
- 6. NMOS Transistor Four terminals:gate, source, drain, body Gate – oxide – body stack looks like a capacitor Gate and body are conductors SiO2 (oxide) is a very good insulator Called metal – oxide – semiconductor (MOS) capacitor Even though gate is no longer made of metal n+ p GateSource Drain bulk Si SiO2 Polysilicon n+
- 7. NMOS Operation Body iscommonly tied to ground (0 V) When the gate is at a low voltage: P-type body is at low voltage Source-body and drain-body diodes are OFF No current flows, transistor is OFF n+ p GateSource Drain bulk Si SiO2 Polysilicon n+ D 0 S
- 8. Body is commonlytied to ground (0 V) When the gate is at a low voltage: P-type body is at low voltage Source-body and drain-body diodes are OFF No current flows, transistor is OFF n+ p GateSource Drain bulk Si SiO2 Polysilicon n+ D 0 S NMOS Operation
- 9. PMOS Transistor Similar, butdoping and voltages reversed Body tied to high voltage (VDD) Gate low: transistor ON Gate high: transistor OFF Bubble indicates inverted behavior SiO2 n GateSource Drain bulk Si Polysilicon p+ p+
- 10. Power Supply Voltage GND= 0 V In 1980’s, VDD = 5V VDD has decreased in modern processes High VDD would damage modern tiny transistors Lower VDD saves power VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
- 11. Transistors as Switches Wecan view MOS transistors as electrically controlled switches Voltage at gate controls path from source to drain g s d g = 0 s d g = 1 s d g s d s d s d nMOS pMOS OFF ON ON OFF
- 12. CMOS Inverter A Y 0 1 VDD AY GND A Y
- 13. A Y 0 1 0 VDD A=1Y=0 GND ON OFF A Y CMOS Inverter
- 14. A Y 0 1 10 VDD A=0 Y=1 GND OFF ON A Y CMOS Inverter
- 15. CMOS NAND Gate AB Y 0 0 1 0 1 1 1 0 1 1 1 0 A=1 B=1 Y=0 ON OFF OFF ON
- 16. CMOS NOR Gate AB Y 0 0 1 0 1 0 1 0 0 1 1 0 A B Y
- 17. 3-input NAND Gate Ypulls low if ALL inputs are 1 Y pulls high if ANY input is 0 A B Y C
- 18.
- 19. Outline Introduction MOS Capacitor nMOS I-VCharacteristics pMOS I-V Characteristics Gate and Diffusion Capacitance
- 20. Introduction So far, wehave treated transistors as ideal switches An ON transistor passes a finite amount of current Depends on terminal voltages Derive current-voltage (I-V) relationships Transistor gate, source, drain all have capacitance I = C (DV/Dt) -> Dt = (C/I) DV Capacitance and current determine speed Also explore what a “degraded level” really means
- 21. MOS Capacitor Gate andbody form MOS capacitor Operating modes Accumulation Depletion Inversion polysilicon gate (a) silicon dioxide insulator p-type body + - Vg < 0 (b) + - 0 < Vg < Vt depletion region (c) + - Vg > Vt depletion region inversion region
- 22. Terminal Voltages Mode ofoperation depends on Vg, Vd, Vs Vgs = Vg – Vs Vgd = Vg – Vd Vds = Vd – Vs = Vgs - Vgd Source and drain are symmetric diffusion terminals By convention, source is terminal at lower voltage Hence Vds ≥ 0 nMOS body is grounded. First assume source is 0 . Three regions of operation Cutoff Linear Saturation
- 23. nMOS Cutoff No channel Ids= 0 + - Vgs = 0 n+ n+ + - Vgd p-type body b g s d
- 24. nMOS Linear Channel forms Currentflows from d to s e- from s to d Ids increases with Vds Similar to linear resistor + - Vgs > Vt n+ n+ + - Vgd = Vgs + - Vgs > Vt n+ n+ + - Vgs > Vgd > Vt Vds = 0 0 < Vds < Vgs -Vt p-type body p-type body b g s d b g s d Ids
- 25. nMOS Saturation Channel pinchesoff Ids independent of Vds We say current saturates Similar to current source + - Vgs > Vt n+ n+ + - Vgd < Vt Vds > Vgs -Vt p-type body b g s d Ids
- 26. I-V Characteristics In Linearregion, Ids depends on How much charge is in the channel? How fast is the charge moving?
- 27. Channel Charge MOS structurelooks like parallel plate capacitor while operating in inversion Gate – oxide – channel Qchannel = n+ n+ p-type body + Vgd gate + + source - Vgs - drain Vds channel - Vg Vs Vd Cg n+ n+ p-type body W L tox SiO2 gate oxide (good insulator, εox = 3.9) polysilicon gate
- 28. Channel Charge MOS structurelooks like parallel plate capacitor while operating in inversion Gate – oxide – channel Qchannel = CV C = Cg = eoxWL/tox = CoxWL V = Vgc – Vt = (Vgs – Vds/2) – Vt n+ n+ p-type body + Vgd gate + + source - Vgs - drain Vds channel - Vg Vs Vd Cg n+ n+ p-type body W L tox SiO2 gate oxide (good insulator, εox = 3.9) polysilicon gate
- 29. Carrier velocity Charge iscarried by e- Carrier velocity v proportional to lateral E-field between source and drain v = mE m called mobility E = Vds/L Time for carrier to cross channel: t = L / v
- 30. nMOS Linear I-V Nowwe know How much charge Qchannel is in the channel How much time t each carrier takes to cross channel ox 2 2 ds ds gs t ds ds gs t ds Q I t W V C V V V L V V V V µ β = = − − ÷ = − − ÷ ox= W C L β µ
- 31. nMOS Saturation I-V IfVgd < Vt, channel pinches off near drain When Vds > Vdsat = Vgs – Vt Now drain voltage no longer increases current ( ) 2 2 2 dsat ds gs t dsat gs t V I V V V V V β β = − − ÷ = −
- 32. nMOS I-V Summary Shockley1st order transistor models ( ) 2 cutoff linear saturatio 0 2 2 n gs t ds ds gs t ds ds dsat gs t ds dsat V V V I V V V V V V V V V β β < = − − < ÷ − >
- 33. pMOS I-V All dopingsand voltages are inverted for pMOS Mobility mp is determined by holes Typically 2-3x lower than that of electrons mn 120 cm2 /V*s in AMI 0.6 mm process Thus pMOS must be wider to provide same current In this class, assume mn / mp = 2
- 34. Capacitance Any two conductorsseparated by an insulator have capacitance Gate to channel capacitor is very important Creates channel charge necessary for operation Source and drain have capacitance to body Across reverse-biased diodes Called diffusion capacitance because it is associated with source/drain diffusion
- 35. Gate Capacitance Approximate channelas connected to source Cgs = eoxWL/tox = CoxWL = CpermicronW Cpermicron is typically about 2 fF/mm n+ n+ p-type body W L tox SiO2 gate oxide (good insulator, εox = 3.9ε0 ) polysilicon gate
- 36. Diffusion Capacitance Csb, Cdb Undesirable,called parasitic capacitance Capacitance depends on area and perimeter Use small diffusion nodes Comparable to Cg for contacted diff ½ Cg for uncontacted Varies with process
- 37.
- 38. Overview of CMOS CMOSFabrication Process Overview CMOS Fabrication Process Problems with Current CMOS Fabrication Future Changes in CMOS Fabrication Outline
- 39. Complementary metal–oxide–semiconductor(CMOS) Has many different uses: Integrated Circuits Data converters Integrated transceivers Image sensors Logic circuits What is CMOS?
- 40. NAND Circuit What isCMOS?
- 41. CMOS Fabrication ProcessOverview
- 42. 1. Create apattern. 2. Oxidize small layer, about 1µm thick. 3. Place photoresist on top of SiO2 4. Place mask(pattern) above photoresist and expose it to UV light. CMOS Fabrication Process
- 43.
- 44. 1. Etch awaySiO2 using HF acid or plasma. 2. Remove remaining photoresist with acids. CMOS Fabrication Process
- 45. To createa n well: Diffusion Heat wafer in Arsenic gas chamber until diffusion occurs. Ion Implantation Arsenic or phosphorous are implanted in window. n well SiO2 CMOS Fabrication Process
- 46.
- 47. A thin layerof oxide is deposited. A thin layer of polysilicon is deposited using Chemical Vapor Deposition (CVD) . p substrate n well CMOS Fabrication Process
- 48. Remove oxide layerusing acid. Dope open area using Ion implantation or diffusion. psubstrate nwell n+n+ n+p+p+p+ CMOS Fabrication Process
- 49. p substrate Metal Thick fieldoxide n well n+n+ n+p+p+p+ CMOS Fabrication Process
- 50.
- 51. Problems with CurrentCMOS Fabrication Optical lithography is limited by the light frequency. Material limitations Yield limitations Space limitations
- 52. Future Changes inCMOS Fabrication Material changes like using high-k materials. Design changes SOI(Silicon On Insulator) Double Gate (Finfet) Twin-Tub Process
- 53. DC Characteristics ofa CMOS Inveter
- 54. DC Characteristics ofa CMOS Inverter A complementary CMOS inverter consists of a p-type and an n-type device connected in series. The DC transfer characteristics of the inverter are a function of the output voltage (Vout) with respect to the input voltage (Vin).
- 55. The MOS devicefirst order Shockley equations describing the transistors in cut-off, linear and saturation modes can be used to generate the transfer characteristics of a CMOS inverter. Plotting these equations for both the n- and p-type devices produces the traces below.
- 56. IV Curves fornMOS
- 57.
- 58. The DC transfercharacteristic curve is determined by plotting the common points of Vgs intersection after taking the absolute value of the p-device IV curves, reflecting them about the x-axis and superimposing them on the n-device IV curves. We basically solve for Vin(n-type) = Vin(p-type) and Ids(n-type)=Ids(p-type) The desired switching point must be designed to be 50 % of magnitude of the supply voltage i.e. VDD/2. Analysis of the superimposed n-type and p-type IV curves results in five regions in which the inverter operates.
- 59. Region A occurswhen 0 leqVin leq Vt(n-type). The n-device is in cut-off (Idsn =0). p-device is in linear region, Idsn = 0 therefore -Idsp = 0 Vdsp = Vout – VDD, but Vdsp =0 leading to an output of Vout = VDD. Region B occurs when the condition Vtn leq Vin le VDD/2 is met. Here p-device is in its non-saturated region Vds neq 0. n-device is in saturation Saturation current Idsn is obtained by setting Vgs = Vin resulting in the equation:
- 60. CMOS Inverter DCCharacteristics
- 61. CMOS Inverter TransferCharacteristics In region B Idsp is governed by voltages Vgs and Vds described by: ( ) ( ) [ ] ( )( ) ( ) − −−−−=−− =− − −−−−−= 22 :thatRecall 2 2 2 2 DDout DDouttpDDinptnin n dspdsn DDout DDouttpDDinpdsp VV VVVVVVV II VV VVVVVI β β β ( ) ( )DDoutdsDDings VVVVVV −=−= and
- 62. Region C hasthat both n- and p-devices are in saturation. Saturation currents for the two devices are: ( ) ( ) tnintnin n dsn DDtpintpDDin p dsp VVVVI VVVVVVI >−= +<−−−= ; 2 AND ; 2 2 2 β β
- 63. Region D isdefined by the inequality p-device is in saturation while n-device is in its non-saturation region. Equating the drain currents allows us to solve for Vout. (See supplemental notes for algebraic manipulations). tpDDin DD VVV V +≤< 2 ( ) ( ) tnin out outtninndsn DDtpintpDDin p dsp VV V VVVI VVVVVVI > −−= +<−−−= ; 2 AND ; 2 2 2 β β
- 64. CMOS Inverter StaticCharateristics In Region E the input condition satisfies: The p-type device is in cut-off: Idsp=0 The n-type device is in linear mode Vgsp = Vin –VDD and this is a more positive value compared to Vtp. Vout = 0 tpDDin VVV −≥
- 65. nMOS & pMOSOperating points nMOS & pMOS Operating points A C B D E Vtp Vtn VDD 0 VDD/2 VDD+Vtp VDD Both in sat nMOS in sat pMOS in sat OutputVoltage Vout =Vin-Vtp Vout =Vin-Vtn
- 66.
- 67. Outline CMOS Gate Design PassTransistors CMOS Latches & Flip-Flops Standard Cell Layouts Stick Diagrams
- 68. CMOS Gate Design Activity: Sketcha 4-input CMOS NOR gate A B C D Y
- 69. Complementary CMOS Complementary CMOSlogic gates nMOS pull-down network pMOS pull-up network a.k.a. static CMOS pMOS pull-up network output inputs nMOS pull-down network Pull-up OFF Pull-up ON Pull-down OFF Z (float) 1 Pull-down ON 0 X (crowbar)
- 70. Series and Parallel nMOS:1 = ON pMOS: 0 = ON Series: both must be ON Parallel: either can be ON (a) a b a b g1 g2 0 0 a b 0 1 a b 1 0 a b 1 1 OFF OFF OFF ON (b) a b a b g1 g2 0 0 a b 0 1 a b 1 0 a b 1 1 ON OFF OFF OFF (c) a b a b g1 g2 0 0 OFF ON ON ON (d) ON ON ON OFF a b 0 a b 1 a b 11 0 1 a b 0 0 a b 0 a b 1 a b 11 0 1 a b g1 g2
- 71. Conduction Complement Complementary CMOSgates always produce 0 or 1 Ex: NAND gate Series nMOS: Y=0 when both inputs are 1 Thus Y=1 when either input is 0 Requires parallel pMOS Rule of Conduction Complements Pull-up network is complement of pull-down Parallel -> series, series -> parallel A B Y
- 72. Compound Gates Compound gatescan do any inverting function Ex: A B C D A B C D A B C D A B C D B D Y A C A C A B C D B D Y (a) (c) (e) (b) (d) (f)
- 73. Example: O3AI A B Y C D DC B A Y= ((A+B+C).D)’
- 74. Signal Strength Strength ofsignal How close it approximates ideal voltage source VDD and GND rails are strongest 1 and 0 nMOS pass strong 0 But degraded or weak 1 pMOS pass strong 1 But degraded or weak 0 Thus nMOS are best for pull-down network
- 75. Pass Transistors g s d g sd Transistors can be used as switches
- 76. Pass Transistors g s d g= 0 s d g = 1 s d 0 strong 0 Input Output 1 degraded 1 g s d g = 0 s d g = 1 s d 0 degraded 0 Input Output strong 1 g = 1 g = 1 g = 0 g = 0 Transistors can be used as switches
- 77. Transmission Gates Pass transistorsproduce degraded outputs Transmission gates pass both 0 and 1 well g = 0, gb = 1 a b g = 1, gb = 0 a b 0 strong 0 Input Output 1 strong 1 g gb a b a b g gb a b g gb a b g gb g = 1, gb = 0 g = 1, gb = 0
- 78. Tristates EN A Y 00 0 1 1 0 1 1 A Y EN A Y EN EN Tristate buffer produces Z when not enabled
- 79. Nonrestoring Tristate Transmission gateacts as tristate buffer Only two transistors But nonrestoring Noise on A is passed on to Y A Y EN EN
- 80. Tristate Inverter Tristate inverterproduces restored output Violates conduction complement rule Because we want a Z output A Y EN EN
- 81. A Y EN A Y EN = 0 Y= 'Z' Y EN = 1 Y = A A EN Tristate inverter produces restored output Violates conduction complement rule Because we want a Z output Tristate Inverter
- 82. Multiplexers 2:1 multiplexer choosesbetween two inputs S D1 D0 Y 0 X 0 0 X 1 1 0 X 1 1 X 0 1 S D0 D1 Y
- 83. 2:1 multiplexer choosesbetween two inputs S D1 D0 Y 0 X 0 0 0 X 1 1 1 0 X 0 1 1 X 1 0 1 S D0 D1 Y Multiplexers
- 84. Gate-Level Mux Design Howmany transistors are needed? 20 4 4 D1 D0 S Y 4 2 2 2 Y 2 D1 D0 S 1 0 (too many transistors)Y SD SD= +
- 85. Transmission Gate Mux Nonrestoringmux uses two transmission gates Only 4 transistors S S D0 D1 YS
- 86. Inverting Mux Inverting multiplexer Usecompound AOI22 Or pair of tristate inverters Essentially the same thing Non inverting multiplexer adds an inverter S D0 D1 Y S D0 D1 Y 0 1 S Y D0 D1 S S S S S S
- 87. 4:1 Multiplexer 4:1 muxchooses one of 4 inputs using two selects Two levels of 2:1 muxes Or four tristates S0 D0 D1 0 1 0 1 0 1 Y S1 D2 D3 D0 D1 D2 D3 Y S1S0 S1S0 S1S0 S1S0
- 88. D Latch When CLK= 1, latch is transparent D flows through to Q like a buffer When CLK = 0, the latch is opaque Q holds its old value independent of D a.k.a. transparent latch or level-sensitive latch CLK D Q Latch D CLK Q
- 89. Multiplexer chooses Dor old Q 1 0 D CLK Q CLK CLKCLK CLK DQ Q Q D Latch
- 90. D Latch Design Circuitsand LayoutSlide 90 Multiplexer chooses D or old Q 1 0 D CLK Q CLK CLKCLK CLK DQ Q Q
- 91. D Latch Operation CLK= 1 D Q Q CLK = 0 D Q Q D CLK Q
- 92. D Flip-flop When CLKrises, D is copied to Q At all other times, Q holds its value a.k.a. positive edge-triggered flip-flop, master-slave flip-flop Flop CLK D Q D CLK Q
- 93. D Flip-flop Design Builtfrom master and slave D latches QM CLK CLKCLK CLK Q CLK CLK CLK CLK D Latch Latch D Q QM CLK CLK
- 94. D Flip-flop Operation CLK= 1 D CLK = 0 Q D QM QM Q D CLK Q
- 95. Race Condition Back-to-back flopscan malfunction from clock skew Second flip-flop fires late Sees first flip-flop change and captures its result Called hold-time failure or race condition CLK1 D Q1 Flop Flop CLK2 Q2 CLK1 CLK2 Q1 Q2
- 96. Non overlapping Clocks Nonoverlapping clocks can prevent races As long as non overlap exceeds clock skew We will use them in this class for safe design Industry manages skew more carefully instead φ1 φ1φ1 φ1 φ2 φ2φ2 φ2 φ2 φ1 QM QD
- 97. Stick Diagram &ScalableStick Diagram & Scalable Design RulesDesign Rules
- 98. IC Layout Concept Stick Diagram Design Rules Layout Verification
- 99. Basic Concept Basedon the view point of IC layout, the stick diagram can help us understand the circuit function and its geometrical location relative to other circuit blocks. Legend: contact metal 2 metal 1 poly ndiff pdiff VDD in VSS out ■
- 100. Although the stickdiagram is an abstract presentation of real layout, it can use graphical symbols or legend to allocate the circuit to 2-diomensional plane and reach the aim same as the physical layout does. The stick diagram is similar to a backbone of the real layout but without the real size and aspect ratio of the devices, it still can reflect the real condition to layout of the silicon chip. Basic Concept
- 101. Notations of thestick diagram
- 102. Intermediate representation between the transistor level and the mask (layout) level. Gives topological information (identifies different layers and their relationship) Assumes that wires have no width. It is possible to translate stick diagram automatically to layout with correct design rules. Stick Diagram
- 103. Stick Diagram Whenthe same material (on the same layer) touch or cross, they are connected and belong to the same electrical node. When polysilicon crosses N or P diffusion, an N or P transistor is formed. Polysilicon is drawn on top of diffusion. Diffusion must be drawn connecting the source and the drain. Gate is automatically self-aligned during fabrication.
- 104. When ametal line needs to be connected to one of the other three conductors, a contact cut (via) is required. Stick Diagram
- 105. Manhattan geometricalrule: When we use only vertical and horizontal lines In orthogonal to describe circuitry. Boston geometrical rule: The stick diagram also allows curves to describe circuitry. In order to describe N/PMOS more completely, to add n- well 、 P+ select 、 well contact and substrate contact are optional for 4-terminal notation. Stick Diagram
- 106. Conclusion Stick diagramis a draft of real layout, it serves as an abstract view between the schematic and layout. Stick diagram uses different lines, colors and geometrical shapes to present circuit nodes, devices, and their relative location. Stick diagram doesn’t include information about the accurate coordinates and sizes of device, the length and width of conductors and the real size of well region.
- 107. CMOS Inverter StickDiagrams Basic layout ․ More area efficient layout
- 108. CMOS inverter describedin other way. VDD in VSS out CMOS Inverter Stick Diagrams
- 109. The transmission gateCircuit schematic Stick diagram CMOS Transmission Gate
- 110. CMOS Stick DiagramsNAND/NOR
- 111.
- 112. < Exercise 1> To draw the following circuitry by using a stick diagram
- 113.
- 114. Lambda-based Design Rules Lambdadesign rules are based on a reference metric λthat has units of um. All widths, spacing and distances are written in the form Value = m λ Where m is scaling multiplier. <e.g.> λ= 1um w = 2 λ=2um s = 3λ=3um
- 115. Lambda-based Design Rules Lambdabased design: half of technology since 1985. As technology changes with smaller dimensions, a simple change in the value of λ can be used to produce a new mask set. All device mask dimensions are based on multiples of λ, e.g., polysilicon minimum width = 2λ. Minimum metal to metal spacing = 3λ 6λ 2λ 6λ λ 3λ 3λ
- 116. Active Contact andSurround Rule Example of surrounded design rule
- 117. Potential Problem -Misalignment Misalignment –induced defect
- 118. Potential Problem –Short between Source and Drain Example of an extended (gate over hang)design rule
- 119. Design Rule (0) Dueto the photo resolution, concentration, temperature and reaction time of the chemical reagents, the layout should tolerate some errors caused by process environment. In order to avoid the influence from process variation, the layout of the circuit schematics should follow the design Rule 。
- 120. The purpose ofdesign rules Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width scalable design rules: lambda parameter absolute dimensions (micron rules)
- 121. Design Rule (1) Layoutrules are used for preparing the masks for fabrication. Fabrication processes have inherent limitations in accuracy. Design rules specify geometry of masks to optimize yield and reliability (trade-offs: area, yield, reliability). Three major rules: Wire width: Minimum dimension associated with a given feature. Wire separation: Allowable separation. Contact: overlap rules.
- 122. Two major approaches: “Micron”rules: stated at micron resolution. λ rules: simplified micron rules with limited scaling attributes. λ may be viewed as the size of minimum feature. Design rules represents a tolerance which insures very high probability of correct fabrication (not a hard boundary between correct and incorrect fabrication). Design rules are determined by experience. Design Rule (2)
- 123. Terminology & Definition Min. Width : The min. width of the line (layer) <Example> Wpoly(min.) = 0.5um Min. Space : The min. spacing between lines with same material <Example> Spoly-poly(min.) = 0.5um
- 124. Terminology & Definition <Min. Extension : The min. extension over different layers <Example> Poly-gate extension over diffusion area = 0.55um Min. Overlap : The overlap between different layers <Example> Poly1 overlap Poly2 min. = 0.7um
- 125. Max. areaof the specific region. <Example> Bonding Pad Area, max. = 100um x 100um Terminology & Definition
- 126. Conventional Layer Definition Layer Polysilicon Metal1 Metal2 ContactTo Poly Contact To Diffusion Via Well (p,n) Active Area (n+,p+) Color Representation Yellow Green Red Blue Magenta Black Black Black Select (p+,n+) Green Layer Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Well (p,n) Active Area (n+,p+) Color Representation Yellow Green Red Blue Magenta Black Black Black Select (p+,n+) Green Layer Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Well (p,n) Active Area (n+,p+) Color Representation Yellow Green Red Blue Magenta Black Black Black Select (p+,n+) Green
- 127. IntraIntra--Layer Design RulesLayerDesign Rules Metal2 4 3 SCMOS Design Rules
- 128. 1 2 1 Via Metal to Poly ContactMetalto Active Contact 1 2 5 4 3 2 2 SCMOS Design Rules
- 129.
- 130. MOSIS Layout DesignRules 3 basic design rules: Wire width Wire separation Contact rule
- 131. Layout Verification DRC –Design Rule Check ERC – Electrical Rule Check LVS – Layout Versus Schematic LPE – Layout Parameter Extraction
- 132. Layout Verification DRC(Design RuleCheck) ： => To check the min. line width and spacing based on the design rules. ERC(Electrical Rule Check) ： => To check the short circuit between Power and Ground, or check the floating node or devices.
- 133. LVS(Layout versus Schematic)： => To verify the consistency between Schematic and Layout. For example ： to check the amount of transistor numbers, sizes of W/L. LPE or PEX(Layout Parameter Extraction) ： => From the database of layout, to extract the devices with parasitics including effective W/L, parasitic capacitances and series resistance. The extracted file is in SPICE format and can be used for Post-Layout Simulation 。 Layout Verification
- 134. Simulations Pre-Layout Simulation -before layout work Post-Layout Simulation – after layout work, post layout simulation will reflect more realistic circuit performance. Layout Verification
- 135. The complete designenvironment of Fill-Custom Design Design database – Cadence Design Framework II Circuit Editor – Text editor/Schematic editor (S-edit, Composer) Circuit Simulator – SPICE,TSPICE, HSPICE Layout Editor – Cadence Virtuoso, Laker, L-edit Layout Verification Diva, Dracula, Calibre, Hercules Layout Verification
- 136. Concluding Remarks Milestones technologyin silicon era Transistor Integrated Circuits CMOS Technology Key weapons in SOC era Design Automation Design Reuse Breakthrough techniques in design automation Simulation (e.g., SPICE, Verilog-XL, etc.) Automatic Placement and Routing (APR) Logic Synthesis (e.g., Design Compiler) Formal Verification Test Pattern Generation It is EDA that pushes the IC design technology forward !