![7
Executing an Instruction
● Fetch the contents of the memory location
pointed to by the PC. The contents of this
location are loaded into the IR (fetch phase).
IR ← [[PC]]
● Assuming that the memory is byte addressable,
increment the contents of the PC by 4 (fetch
phase).
PC ← [PC] + 4
● Carry out the actions specified by the
instruction in the IR (execution phase).](https://image.slidesharecdn.com/unit2part-1-250817124429-70e7e109/85/Computer-Architecture-and-Organization-_-Instruction-set-7-320.jpg)
![14
Fetching a Word from Memory
● The response time of each memory access
varies (cache miss, memory-mapped I/O,…).
● To accommodate this, the processor waits until
it receives an indication that the requested
operation has been completed (Memory-
Function-Completed, MFC).
● Move (R1), R2
MAR ← [R1]
Start a Read operation on the memory bus
Wait for the MFC response from the memory
Load MDR from the memory bus
R2 ← [MDR]](https://image.slidesharecdn.com/unit2part-1-250817124429-70e7e109/85/Computer-Architecture-and-Organization-_-Instruction-set-14-320.jpg)
Computer Architecture and Organization _ Instruction set
- 1. 1 Prof Srinivas Prasad, FIE, FIETE BE (SGBAU), MS (BITS), MTECH (IIT-ISM), PhD (UU) UNIT-2(part-1) 24CSEN2021:COMPUTER ORGANIZATION AND ARCHITECTURE
- 2. 2 2 Text/Reference Books TextBooks: 1. C. Hamacher, Z. Vranesic and S. Zaky, "Computer Organization", 5th edition, McGrawHill, 2017 2. W. Stallings, "Computer Organization and Architecture -Designing for Performance", 11th edition, Prentice Hall of India,2022 References: 1. D. A. Patterson and J. L. Hennessy, "Computer Organization and Design The Hardware/Software Interface", 1998 2. J .P. Hayes, "Computer Architecture and Organization", 1998 3.,https://onlinecourses.nptel.ac.in/noc21_cs61/ preview
- 4. 4 Overview ● Instruction Set Processor (ISP) ● Central Processing Unit (CPU) ● A typical computing task consists of a series of steps specified by a sequence of machine instructions that constitute a program. ● An instruction is executed by carrying out a sequence of more rudimentary operations.
- 6. 6 Fundamental Concepts ● Processor fetches one instruction at a time and perform the operation specified. ● Instructions are fetched from successive memory locations until a branch or a jump instruction is encountered. ● Processor keeps track of the address of the memory location containing the next instruction to be fetched using Program Counter (PC). ● Instruction Register (IR)
- 7. 7 Executing an Instruction ● Fetch the contents of the memory location pointed to by the PC. The contents of this location are loaded into the IR (fetch phase). IR ← [[PC]] ● Assuming that the memory is byte addressable, increment the contents of the PC by 4 (fetch phase). PC ← [PC] + 4 ● Carry out the actions specified by the instruction in the IR (execution phase).
- 8. 8 Processor Organization lines Data Address lines bus Memory Carry-in ALU PC MAR MDR Y Z Add XOR Sub bus IR TEMP R0 control ALU lines Control signals R n 1 - Instruction decoder and Internal processor control logic A B Figure 7.1. Single-bus organization of the datapath inside a processor. MUX Select Constant 4 Datapath MDR HAS TWO INPUTS AND TWO OUTPUTS
- 9. 9 Executing an Instruction ● Transfer a word of data from one processor register to another or to the ALU. ● Perform an arithmetic or a logic operation and store the result in a processor register. ● Fetch the contents of a given memory location and load them into a processor register. ● Store a word of data from a processor register into a given memory location.
- 10. 10 Register Transfers B A Z ALU Yin Y Z in Z out Riin Ri Riout bus Internal processor Constant 4 MUX FInput and output gating for the registers . Select
- 11. 11 Register Transfers ● All operations and data transfers are controlled by the processor clock. Figure 7.3. Input and output g ating for one re gister bit. D Q Q Clock 1 0 Riout Riin Bus Input and output gating for one register bit.
- 12. 12 Performing an Arithmetic or Logic Operation ● The ALU is a combinational circuit that has no internal storage. ● ALU gets the two operands from MUX and bus. The result is temporarily stored in register Z. ● What is the sequence of operations to add the contents of register R1 to those of R2 and store the result in R3? 1. R1out, Yin 2. R2out, SelectY, Add, Zin 3. Zout, R3in
- 13. 13 Fetching a Word from Memory ● Address into MAR; issue Read operation; data into MDR. MDR Memory-bus Figure 7.4. Connection and control signals for re gister MDR. data lines Internal processor bus MDRout MDRoutE MDRin MDRinE Connection and control signals for register MDR.
- 14. 14 Fetching a Word from Memory ● The response time of each memory access varies (cache miss, memory-mapped I/O,…). ● To accommodate this, the processor waits until it receives an indication that the requested operation has been completed (Memory- Function-Completed, MFC). ● Move (R1), R2 MAR ← [R1] Start a Read operation on the memory bus Wait for the MFC response from the memory Load MDR from the memory bus R2 ← [MDR]
- 15. 15 Execution of a Complete Instruction ● Add (R3), R1 ● Fetch the instruction ● Fetch the first operand (the contents of the memory location pointed to by R3) ● Perform the addition ● Load the result into R1
- 16. 16 Architecture B A Z ALU Yin Y Z in Z out Riin Ri Riout bus Internal processor Constant 4 MUX Input and output gating for the registers in Figure . Select
- 17. 17 Execution of a Complete Instruction Step Action 1 PCout , MAR in , Read, Select4,Add, Zin 2 Zout , PCin , Yin , WMF C 3 MDRout , IRin 4 R3out , MAR in , Read 5 R1out , Yin , WMF C 6 MDRout , SelectY, Add, Zin 7 Zout , R1in , End Figure 7.6. Control sequence for execution of the instruction Add (R3),R1. lines Data Address lines bus Memory Carry-in ALU PC MAR MDR Y Z Add XOR Sub bus IR TEMP R0 control ALU lines Control signals R n 1 - Instruction decoder and Internal processor control logic A B Figure 7.1. Single-bus organization of the datapath inside a processor. MUX Select Constant 4 Add (R3), R1
- 18. 18 Execution of Branch Instructions ● A branch instruction replaces the contents of PC with the branch target address, which is usually obtained by adding an offset X given in the branch instruction. ● The offset X is usually the difference between the branch target address and the address immediately following the branch instruction. ● Conditional branch
- 19. 19 Execution of Branch Instructions Step Action 1 PC out , MAR in , Read, Select4, Add, Z in 2 Zout, PC in , Y in, WMF C 3 MDR out , IR in 4 Offset-field-of-IR out, Add, Z in 5 Z out, PC in , End Control sequence for an unconditional branch instruction.
- 20. 20 Multiple-Bus Organization Memory b us data lines Figure 7.8. Three-b us or g anization of the datapath. Bus A Bus B Bus C Instruction decoder PC Re gister file Constant 4 ALU MDR A B R MUX Incrementer Address lines MAR IR
- 21. 21 Multiple-Bus Organization ● Add R4, R5, R6 StepAction 1 PCout, R=B, MARin , Read,IncPC 2 WMF C 3 MDR outB , R=B,IRin 4 R4outA, R5outB , SelectA, Add,R6in, End Control sequence for the instruction. Add R4,R5,R6, for the three-bus organization
- 22. 22 Quiz ● What is the control sequence for execution of the instruction Add R1, R2 including the instruction fetch phase? (Assume single bus architecture) lines Data Address lines bus Memory Carry-in ALU PC MAR MDR Y Z Add XOR Sub bus IR TEMP R0 control ALU lines Control signals R n 1 - Instruction decoder and Internal processor control logic A B Figure 7.1. Single-bus organization of the datapath inside a processor. MUX Select Constant 4
- 23. 23
- 25. 25 Overview ● To execute instructions, the processor must have some means of generating the control signals needed in the proper sequence. ● Two categories: hardwired control and microprogrammed control ● Hardwired system can operate at high speed; but with little flexibility.
- 26. 26 Control Unit Organization Control unit organization. CLK Clock Control step IR encoder Decoder/ Control signals codes counter inputs Condition External
- 27. 27 Detailed Block Description External inputs Figure 7.11. Separation of the decoding and encoding functions. Encoder Reset CLK Clock Control signals counter Run End Condition codes decoder Instruction Step decoder Control step IR T1 T2 Tn INS1 INS2 INSm
- 28. 28 Generating Zin ● Zin = T1 + T6 • ADD + T4 • BR + … Generation of the Zin control signal for the processor in Figure 7.1. T 1 Add Branch T4 T 6
- 29. 29 Generating End ● End = T7 • ADD + T5 • BR + (T5 • N + T4 • N) • BRN +… Figure 7.13. Generation of the End control signal. T7 Add Branch Branch<0 T 5 End N N T 4 T 5
- 30. 30 A Complete Processor Instruction unit Integer unit Floating-point unit Instruction cache Data cache Bus interface Main memory Input/ Output System b us Processor Figure 7.14. Block diagram of a complete processor .
- 32. 32 Overview ● Control signals are generated by a program similar to machine language programs. ● Control Word (CW); microroutine; microinstruction PC in PC out MAR in Read MDR out IR in Y in Select Add Z in Z out R1 out R1 in R3 out WMFC End 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 1 0 0 Micro - instruction 1 2 3 4 5 6 7 Figure 7.15 An example of microinstructions for Figure 7.6.
- 33. 33 Overview Step Action 1 PCout , MAR in , Read, Select4,Add, Zin 2 Zout , PCin , Yin , WMF C 3 MDRout , IRin 4 R3out , MAR in , Read 5 R1out , Yin , WMF C 6 MDRout , SelectY, Add, Zin 7 Zout , R1in , End Figure 7.6. Control sequence for execution of the instruction Add (R3),R1.
- 34. 34 Overview ● Control store Figure 7.16. Basic organization of a microprogrammed control unit. store Control generator Starting address CW Clock PC IR One function cannot be carried out by this simple organization.
- 35. 35 Overview ● The previous organization cannot handle the situation when the control unit is required to check the status of the condition codes or external inputs to choose between alternative courses of action. ● Use conditional branch microinstruction. Address Microinstruction 0 PC out , MAR in , Read, Select4, Add, Z in 1 Zout , PC in , Y in , WMF C 2 MDR out , IR in 3 Branch to starting addressof appropriate microroutine . ... .. ... . .. . . ... .. . .. ... .. ... . .. .. .. . .. .. . .. . .. . .. . . ... ... .. ... .. 25 If N=0, then branch to microinstruction 0 26 Offset-field-of-IR out , SelectY, Add, Z in 27 Zout , PC in , End Figure 7.17. Microroutine for the instruction Branch<0.
- 36. 36 Overview Figure 7.18. Organization of the control unit to allow conditional branching in the microprogram. Control store Clock generator Starting and branch address Condition codes inputs External CW IR PC
- 37. 37 Microinstructions ● A straightforward way to structure microinstructions is to assign one bit position to each control signal. ● However, this is very inefficient. ● The length can be reduced: most signals are not needed simultaneously, and many signals are mutually exclusive. ● All mutually exclusive signals are placed in the same group in binary coding.
- 38. 38 Further Improvement ● Enumerate the patterns of required signals in all possible microinstructions. Each meaningful combination of active control signals can then be assigned a distinct code. ● Vertical organization ● Horizontal organization
- 39. 39 Microprogram Sequencing ● If all microprograms require only straightforward sequential execution of microinstructions except for branches, letting a μPC governs the sequencing would be efficient. ● However, two disadvantages: Having a separate microroutine for each machine instruction results in a large total number of microinstructions and a large control store. Longer execution time because it takes more time to carry out the required branches. ● Example: Add src, Rdst ● Four addressing modes: register, autoincrement, autodecrement, and indexed (with indirect forms).
- 40. 40 40 Hardwired vs Micro-programmed Control ● Hardwired implementation of the CU – synthesizing a sequential circuit to obtain the desidered input-output relations for control signals ● Micro-programmed implementation of the CU – use sequences of micro-instructions to implement the execution of CPU micro-operations ● Called micro-programming or firmware production, since each sequence is made up by a small number of very simple operations
- 41. 41 Rev. (2008-09) by Luciano Gualà 41 Hardwired vs Micro-programmed ● Micro-programmed control simplifies the design of control unit – Cheaper – Less error-prone – Much more easier to revise and modify ● But the control unit is faster with hardwired CU ● Micro-programmed CU is used mainly for CISC architectures since flexibility of CU is more important for a complex instruction set ● On the other side, RISC architectures use hardwired CU since with a simpler instruction set flexibility is a less important requirement than speed of execution
- 42. 42 References 1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, Computer Organization,5/e, McGraw Hill,2001 References: !. M. Morris Mano, Computer System Architecture, 3/e, Pearson education, 2008 2. John P. Hayes, Computer Architecture and Organization, 3/e, McGraw Hill, 1998. 3. William Stallings, Computer Organization and Architecture, 6/e, Pearson PHI, 2012.