Computer Organization and Architecture_Unit 1_part b.pptx

Contents
• Accessing I/O Devices
• Interrupts – Interrupt Hardware
• Direct Memory Access
• Buses
• Interface Circuits
• Standard I/O Interfaces
• PCI Bus
• SCSI Bus
• USB

Accessing I/O devices
• Multiple I/O devices may be connected to the processor and the memory via a bus.
• The bus consists of three sets of lines to carry address, data, and control signals.
• Each I/O device is assigned a unique address.
• To access an I/O device, the processor places the address on the address lines.
• The device recognizes the address and responds to the control signals
Bus
I/O device 1 I/O device n
Processor Memory

Two alternate ways to connect I/O devices to address and data bus
• Memory –mapped device interface
• I/O mapped device interface

Memory mapped I/O
• The same address decoder selects memory and I/O ports.
• Some of the memory address space is occupied by I/O device.
• All data transfer instructions to/from memory can be used to transfer data to/from I/O devices.
• The processor need not have separate instruction for I/O, nor it need to specify whether an
address generated by the CPU is memory address or an I/O address.

I/O mapped device interface
Separate instructions for I/O data transfer (say, IN and OUT).
A processor signal identifies whether a generated address refers to a memory location or an I/O
device.
Separate address decoders for selecting memory and I/O ports.
The complete memory address space can be utilized

Hardware required to connect an I/O device to the bus
I/O
interfac
e
Address
decoder
Data and
status
registers
Control
circuits
Input
device
Bus
Address lines
Data lines
Control lines

• I/O device is connected to the bus using an I/O interface circuit which has:
• ‐ Address decoder, control circuit, and data and status registers.
• Address decoder decodes the address placed on the address lines thus enabling the device to recognize its address.
• Data register holds the data being transferred to or from the processor.
• Status register holds information necessary for the operation of the I/O device.
• Data and status registers are connected to the data lines and have unique addresses.
• I/O interface circuit which constitutes of address decoder, the data and status registers will
coordinates I/O transfers.

Example: I/O operation involving a keyboard and a display device in a computer
system.
• It is based on the Programmed controlled I/O mechanism
• The processor repeatedly checks a status flag to achieve the required synchronization between
the processor and input or output device.
• The four registers shown in fig a are used in the data transfer operations.
• DATA IN
• DATA OUT
• STATUS
• CONTROL
DIRQ KIRQ SOUT SIN
KEN
DEN

Register STATUS contains two control flags, SIN and SOUT which provides status information for the
keyboard and display unit respectively.
The two flags KIRQ and DIRQ in this register are used in conjunction with interrupts.
The KEN and DEN bits in register CONTROL.
Data from the keyboard are made available in the DATAIN register and data sent to the display are
stored in the DATAOUT register.

A program that reads one line from the keyboard stores it in memory buffer and echoes it back to the display
Move #LINE, R0 Initialize memory pointer
WAITK TestBit #0, STATUS Test SIN
Branch = 0 WAITK Wait for character to be entered
Move DataIN, R1 Read character
WAITD TestBit #1, STATUS Test SOUT
Branch = 0 WAITD wait for display to become ready
Move R1, DATAOUTSend character
Move R1, (R0)+ Store character and advance pointer
Compare #$0D, R1 Check if carriage Return
Branch = 0 WAITK If not get another character
Move #$A, DATAOUT Otherwise, send Linefeed
Call PROCESS Call a subroutine to process the input line

Mechanisms to Implement I/O Operations
• Program-controlled I/O – processor polls the device.
• Interrupt
• Direct Memory Access (DMA)

Program-Controlled I/O
• Processor repeatedly monitors a status flag to achieve the necessary synchronization.
• Processor polls the I/O device
• I/O devices operate at speeds that are very much different from that of the processor.
• Keyboard, for example, is very slow.
• It needs to make sure that only after a character is available in the input buffer of the keyboard
interface; also, this character must be read only once.

Interrupts
• Interrupt is a hardware signal generated by an I/O device when it is ready to perform a task.
• At least one of the bus control lines called the interrupt request line is usually dedicated to this
purpose
• Basically it avoids the processor’s role of continuously checking the status of external devices and
assures that the processor’s waiting period is utilized to perform other useful functions.
• Indeed, by using interrupts such waiting periods can be ideally eliminated

Interrupts
An example to illustrate interrupt concepts:
• A task that requires some computations to be performed and the results to be printed on a line
printer
• Let the program consists of 2 routines COMPUTE and PRINT
• Assume that COMPUTE produces a set of n lines of output, to be printed by PRINT routine.
• The printer accepts only one of text at a time
• This simple approach has a disadvantage. i.e the processor spends a considerable amount of time
waiting for printer to become ready.
•

Interrupts
• First, the routine is executed to send the first line of text to the printer.
• At this point, the PRINT routine may be temporarily suspended and execution of COMPUTE
routine continued.
• Whenever the printer becomes ready, it alerts the processor by sending an interrupt request
signal.
• In response, the processor interrupts execution of the COMPUTE routine and transfer control to
the PRINT routine.
• The PRINT routine sends the second line to the printer and is again suspended.
• Then the interrupted COMPUTE routine resumes execution at the point of interruption.
• This process continues until all n lines have been printed and the PRINT routine ends.

Interrupts
• The PRINT routine will be restarted whenever the next set of n lines is available for printing.
• If COMPUTE takes longer to generate n lines than the time required to print them, the processor
will be performing useful computation all the time.

Interrupts
• The routine executed in response to an interrupt request is called the interrupt-service routine.
• The processor first completes the execution of instruction i.
• Then it loads the program counter with the address of the first instruction of the interrupt service
routine, the processor has to come back to instruction i+1.
• Hence when an interrupt occurs, the current contents of the PC which points to i+1 must be
stored in a temporary location (a known location).
• This causes execution to resume at instruction i+1.
• During this process, the processor needs an acknowledgment that its request has been
recognized so that it can remove its interrupt-request signal.
• This can be accomplished through a special control signal on the bus called the interrupt
acknowledge signal.

Interrupts
• Interrupt procedure is similar to subroutine call, however there are some differences.
• The interrupt is usually initiated by external or internal signal rather than from the execution of an
instruction (except for s/w interrupt).
• The address of the interrupt service program is determined by the hardware rather than by the
address field of the instruction.
• Interrupt procedure stores all information necessary to define the state of the CPU rather than storing
only the program counter
• Subroutine call is called by the user through instructions, where as interrupt is called by the hardware
or any external signal.
• Interrupt concept finds its application in
• Operating System
• Real time processing applications – here processing of certain routines must be accurately timed
relative to external events.

Interrupts
• Interrupt Hardware:

Interrupts
• An I/O device requests an interrupt by activating a bus line called interrupt-request.
• A single interrupt-request line may be used to serve n devices as depicted in fig b.
• All devices are connected to the line via switches to ground
• To request an interrupt, a device closes its associated switch
• Thus, if all interrupt-requested signals INTR1 to INTRn are inactive, that is, if all switches are open,
the voltage on the interrupt-request line will be equal to Vdd. This is the inactive state of the line
• When a device requests an interrupt by closing its switch, the voltage on the line drops to 0.
• Causing the interrupt request signal, INTR received by the processor to go to 1
• Since the closing of one or more switches will cause the line voltage to drop to 0, the value of
INTR is the logical OR of the requests from individual devices i.e.
• INTR = INTR1 + INTR2 + ……………….. + INTRn

Interrupts
• It is customary to use the complemented form INTR, to name the interrupt request signal on the
common line, because this signal is active when in the low-voltage state.
• In the electronic implementation of the circuit in fig b. the special gates known as open-collector
(for bipolar circuits) or open drain (for MOS circuits) are used to drive the INTR line.
• The output of an open-collector or an open drain gate is equivalent to a switch to ground that is
open when the gates input is in the 0 state and closed when it is in the 1 state.
• The voltage level at the output of the gate is determined by the data applied to all the gates
connected to the bus according to the equation given above.
• Resistor R is called a pull-up resistor because it pulls the line voltage up to the high voltage state
when the switches are open.

Enabling and disabling Interrupts
• All computers fundamentally should be able to enable and disable interruptions as desired.
• The problem of infinite loop occurs due to successive interruptions of active INTR signals.
• There are three mechanism to solve infinite loop problems.
The first option:
• To have processor hardware ignore the interrupt request line until the execution of the first
instruction of the interrupt service routine has been completed.
• By using an Interrupt-disable instruction as the first instruction in interrupt service routine, the
programmer can ensure that no further interruptions will occur until an Interrupt-enable
instruction is executed.

• Typically, the Interrupts enable instruction will be the last instruction in the interrupt-service
routine before the return from-interrupt instruction.
• The processor must guarantee that execution of the Return-from-interrupt instruction is
completed before further instruction can occur.
• The second option:
• It is suitable for simple processor with only one interrupt request line.
• Here, the processor automatically disable interrupts before starting the execution of the
interrupt-service routine.
• After saving the counter of the PC and the processor status registers (PS) on the stack, the
processor performs the equivalent of executing an Interrupt –disable instruction.
• The one bit in the PS register, called Interrupt enable indicates whether interrupts are enabled.

• An interrupt request received while this bit is equal to 1 will be accepted.
• After saving the PS contents on the Stack, with the Interrupt enable bit equal to 1, the processor
clears the Interrupt enable bit in its PS register, thus disabling further interrupts.
• When a return – from – interrupt instruction is executed, the contents of the PS are restored from
stack, setting the interrupt enable bit back to 1. Hence, interrupts are again enabled.
The third option:
• The processor has a special interrupt-request line for which the interrupt-handling circuit
responds only to the leading edge of the signal such a line is named as edge triggered.
• Here, the processor will receive only one request regardless of how long the line is activated.
• Hence there is no threat of multiple interruptions and no need to explicitly disable interrupt
requests from line.

Handling Interrupt Request from Single device
Assuming that interrupts are enabled, the following is a typical scenario:
The device raises an interrupt request
The processor interrupts the program currently being executed
Interrupts are disabled by changing the control bits in the PS (except in the case of edge-triggered
interrupts)
The device is informed that its request has been recognized and in response it deactivates the
interrupt-request signal
The action requested by the interrupt is performed by the interrupt-service routine.
Interrupts are enabled and execution of the interrupted program is resumed.

Handling Multiple Devices
• When a request is received over the common interrupt-request line as shown in fig © additional
information is needed to identify the particular device that activated the line.
• Suppose if 2 devices have activated the line at the same time, it must be possible to break the tie
and select one of the two requests for service.

• The information needed to determine whether a device is requesting an interrupt is available in
its status register.
• When a device raises an interrupt request, it sets to 1 one of the bits in its status register, which
will call the IRQ bit the simplest way to identify the interrupting device:
• Polling
• Vectored interrupt
Polling scheme:
• Simplest way to identify the interrupting device.
• Here the interrupt-service routine polls all the I/O devices connected to the bus.
• The first device encountered with its IRQ bit set is the device that should be serviced.
• An appropriate subroutine is called to provide the requested service.

• Main disadvantage is the time spent interrogating the IRQ bits of all the devices that may not be
requesting any service.
Vectored interrupts
• To reduce the time involved in the polling process, a device requesting an interrupt may identify itself
directly to the processor.
• Then processor can immediately start executing the corresponding interrupt-service routine.
• The interrupt-handling scheme based on this approach is referred as vectored interrupts.
• The special-code-indicates starting address of ISR
• The special code length range from 4 to 8 bit
• The location pointed to by the interrupting-device is used to store the starting address to ISR

• The processor reads this address, called the interrupt vector, and loads into the PC.
• The interrupt vector may also include a new value for the process status register.
• In most computers, I/O devices send the interrupt-vector code over the data bus using the bus
control signals to ensure that devices do not interfere with each other.
• When a device sends an interrupt, the processor may not be ready to receive interrupt-vector
code immediately. There may be further delays if it interrupts happen to be disabled at the time
the request is raised.
• The interrupting device must wait to put data on the bus only when processor is ready to receive
it.
• When processor is ready to receive interrupt – vector code it activates the INTA line.
• Then the I/O device responds by sending its interrupt vector code and turning off the INTR signal.

Interrupt Nesting
• In this method, the I/O device is organized in a priority structure.
• Therefore, an interrupt request from a higher priority device is recognized where as a request
from a lower priority device is not
• The processor accepts interrupts only from devices/processes having priority.
• Processor’s priority is encoded in a few bits of PS (Processor Status Register).
• It can be changed by program instructions that write into the PS.
• The processor is in supervisor mode only while executing OS routines.
• It switches to user mode before executing application programs.
•

Multiple-level Priority Organization
• It is implemented by using separate INTR and INTA lines for each device
• Each INTR line is assigned a different priority level.
• Priority level of processor is the priority of programs that is currently being executed.
• Processor accepts interrupts only from devices that have higher priority than its own
• At this time of execution of ISR for some device priority of processor is raised to that of the
device.
• Thus, interrupts from devices at the same level of priority or lower are disabled.

Multiple-level Priority Organization
Privileged instruction:
Are instructions that can be executed only while the processor is running in supervisor mode.
These instructions can be used to change processors priority bits [ encoded in a few bits of the
processor status word].
Privileged Exception:
User program cannot
accidentally or intentionally change the priority of the processor
Disrupt the system-operation
An attempt to execute a privileged-instruction while in user-mode leads to a privileged Exception

Simultaneous Requests
• INTR line is common to all devices
• INTA line is connected in a daisy-chain fashion
• INTA signal propagates serially through devices.
• When several devices raise an interrupt-request INTR line is activated
• Processor responds by setting INTA line to 1 this signal is received by device 1
• Device – 1 passes signal onto device 2 only if it does not require any service.
• If device – 1 has a pending – request for interrupt the device – 1
• Blocks INTA signal and proceeds to put its identifying code on the data line.
• Therefore, in daisy chain arrangement the device that is electrically closed to the processor has
the highest priority.
• The second device along the chain has second highest priority and so on.

Simultaneous Requests
• Fig (e) is general structure designed by both multiple-priority scheme implemented using
separate interrupt request and interrupt acknowledge lines for each device and daisy chain
arrangement.
• Devices are organized in groups and each group is connected at a different priority level
• Within a group, devices are connected in a daisy chain

Exception
• An interrupt is an event that causes the execution of one program to be suspended and the
execution of another program to begin.
• The term exception is often used to refer to any event that causes an interruption.
• Hence, I/O interrupts are one example of an exception.
Kinds of Exception
• Recovery from errors
• Debugging
• Privilege Exception

Exception- Recovery from Errors
• Computers use a variety of techniques to ensure that all hardware components are operating
properly.
• If errors occur, the control hardware detects it and informs the processor by raising an interrupt.
• The processor may also interrupt a program if it detects an error or an unusual condition while
executing the instructions of this program.
• When exception processing is initiated because of such errors, the processor proceeds in the
same manner as in the case of an I/O interrupt request.
• It suspends the program being executed and starts an exception-service routine.
• When an interrupt is caused by an error, execution of the interrupted instruction cannot usually
be completed, and the processor begins exception processing immediately.

Exceptions- Debugging
• Another important type of exception is used as an aid in debugging programs.
• System software usually includes a program called a debugger, which helps the programmer find errors
in a program.
• The debugger uses exceptions to provide two important facilities called trace and breakpoints.
Trace mode
• an exception occurs after the execution of every instruction, using the debugging program as the
exception-service routine.
• The debugging program enables the user to examine the contents of registers, memory locations, and
so on.
• On return from the debugging program, the next instruction in the program being debugged is
executed, and then the debugging program is activated again. The trace exception is disabled during
the execution of the debugging program.

Exceptions- Breakpoint
• Breakpoint
• The program being debugged is interrupted only at specific points selected by the user.
• An instruction called Trap or Software-interrupt is usually provided for this purpose.
• Execution of this instruction results in the same actions as when a hardware interrupt request is
received.
• While debugging a program, the user may wish to interrupt program execution after instruction i.
• The debugging routine saves instruction i+1 and replaces it with a software interrupt instruction.
• When the program is executed and reaches that point, it is interrupted and the debugging routine is
activated.
• This gives the user a chance to examine memory and register contents.
• When the user is ready to continue executing the program being debugged, the debugging routine
restores the saved instruction that was a location i+1 and executes a Return-from-interrupt instruction

Exception – Privilege Exception
• To protect the operating system of a computer from being corrupted by user programs, certain
instructions can be executed only while the processor is in supervisor mode. These are called
privileged instructions.
• For example, when the processor is running in the user mode, it will not execute an instruction
that changes the priority level of the processor or that enables a user program to access areas in
the computer memory that have been allocated to other users.
• An attempt to execute such an instruction will produce a privilege exception, causing the
processor to switch to the supervisor mode and begin executing an appropriate routine in the
operating system

DMA
• A special control unit may be provided to transfer a block of data directly between an I/O device and
the main memory, without continuous intervention by the processor.
• The control unit which performs these transfers is a part of the I/O device’s interface circuit. This
control unit is called a DMA controller.
• DMA controller performs functions that would be normally carried out by the processor:
• For each word, it provides the memory address and all the control signals.
• To transfer a block of data, it increments the memory addresses and keeps track of the number of
transfers.
• Although a DMA controller transfers data without intervention by the processor, its operation must be
under the control of a program executed by the processor, usually an operating system routine.
• To initiate the transfer of a block of words, the processor sends to the DMA controller the starting
address, the number of words in the block, and the direction of the transfer.

DMA
• The DMA controller then proceeds to perform the requested operation.
• When the entire block has been transferred, it informs the processor by raising an interrupt.
The above figure shows an example of the DMA controller registers that are accessed by the
processor to initiate data transfer operations

DMA
• Three registers in a DMA interface are:
• Starting address
• Word count
• Status and control flag
• Two registers are used for storing the starting address and the word count.
• The third register contains status and control flags.
• The R/W bit determines the direction of the transfer.

DMA
• When this bit is set to 1 by a program instruction, the controller performs a Read operation, that
is, it transfers data from the memory to the I/O device. Otherwise, it performs a Write operation.
• Additional information is also transferred as may be required by the I/O device.
• When the controller has completed transferring a block of data and is ready to receive another
command, it sets the Done flag to 1
• Bit 30 is the Interrupt-enable flag, IE. When this flag is set to 1, it causes the controller to raise an
interrupt after it has completed transferring a block of data.
• Finally, the controller sets the IRQ bit to 1 when it has requested an interrupt.

DMA Controller in a Computer System

• One DMA controller connects a high-speed Ethernet to the computer’s I/O bus
• The disk controller, which controls two disks, also has DMA capability and provides two DMA
channels.
• It can perform two independent DMA operations as if each disk had its own DMA controller.
• The registers needed to store the memory address, the word count, and so on, are duplicated so
that one set can be used with each disk.
• To start a DMA transfer of a block of data from the main memory to one of the disks, an OS
routine writes the address and word count information into the registers of the disk controller.

• The DMA controller proceeds independently to implement the specified operation.
• When the transfer is completed, this fact is recorded in the status and control register of the DMA
channel by setting the Done bit.
• At the same time, if the IE bit is set, the controller sends an interrupt request to the processor
and sets the IRQ bit.
• The status register may also be used to record other information, such as whether the transfer
took place correctly or errors occurred.

There are 2 ways in which the DMA operation
can be carried out:
• Processor originates most memory-access cycles. DMA controller is said to "steal" memory cycles
from the processor. Hence, this technique is usually called Cycle Stealing.
• The DMA controller is given exclusive access to the main memory to transfer a block of data
without any interruption. This is known as Block Mode (or burst mode)
Cycle Stealing
Requests by DMA devices for using the bus have higher priority than processor requests
• Top priority is given to high-speed peripherals such as,
• Disk
• High-speed Network Interface and Graphics display device.
• Since the processor originates most memory access cycles, the DMA controller can be
said to steal the memory cycles from the processor.
• This interviewing technique is called Cycle stealing.

There are 2 ways in which the DMA operation
can be carried out:
Burst mode
• An entire block of data is transferred in one contiguous sequence.
• Once the DMA controller is granted access to the system bus by the CPU, it transfers all bytes of
data in the data block before releasing control of the system buses back to the CPU.
• This mode is useful for loading programs or data files into memory but renders the CPU inactive
for relatively long periods. The mode is also called Block Transfer Mode.

DMA
• A conflict may arise if both the processor and a DMA controller or two DMA controllers try to use
the bus at the same time to access the main memory.
• To resolve these conflicts, an arbitration procedure is implemented on the bus to coordinate the
activities of all devices requesting memory transfers.

Bus Arbitration
• It is the process by which the next device to become the bus master is selected and the bus
mastership is transferred to it.
• Types: There are 2 approaches to bus arbitration. They are:
• Centralized arbitration ( A single bus arbiter performs arbitration)
• Distributed arbitration (all devices participate in the selection of the next bus master)

Bus Arbitration-Centralized Arbitration

Bus Arbitration-Centralized Arbitration
• Here the processor is the bus master, and it may grant bus mastership to one of its DMA
controllers.
• A DMA controller indicates that it needs to become the bus master by activating the Bus Request
line (BR) which is an open drain line.
• The signal on BR is the logical OR of the bus request from all devices connected to it.
• When BR is activated, the processor activates the Bus Grant Signal (BGI) and indicates to the DMA
controller that they may use the bus when it becomes free.
• This signal is connected to all devices using a daisy chain arrangement.
• If DMA requests the bus, it blocks the propagation of Grant Signal to other devices and it
indicates to all devices that it is using the bus by activating the open collector line, Bus Busy
(BBSY).

Bus Arbitration-Distributed Arbitration

• All devices waiting to use the bus share the responsibility of carrying out the arbitration process.
• The arbitration process does not depend on a central arbiter and hence distributed arbitration
has higher reliability.
• Each device is assigned a 4 bit ID number.
‐
• All the devices are connected using 5 lines, 4 arbitration lines to transmit the ID, and one line for
the Start Arbitration signal.
‐
• To request the bus a device:
• Asserts the Start Arbitration signal.
‐
• Places its 4 bit ID number on the arbitration lines.
‐
• The pattern that appears on the arbitration lines is the logical OR of all the 4 bit device IDs placed
‐
on the arbitration lines

• Each device compares the pattern that appears on the arbitration lines to its ID, starting with
MSB.
• If it detects a difference, it transmits 0s on the arbitration lines for that and all lower bit positions.
• The pattern that appears on the arbitration lines is the logical OR of all the 4 bit device IDs placed
‐
on the arbitration lines.
• Device A has the ID 5 and wants to request the bus:
• ‐ Transmits the pattern 0101 on the arbitration lines.
• Device B has the ID 6 and wants to request the bus:
• ‐ Transmits the pattern 0110 on the arbitration lines.
• Pattern that appears on the arbitration lines is the logical OR of the patterns:
• ‐ Pattern 0111 appears on the arbitration lines.

Arbitration process:
• Each device compares the pattern that appears on the arbitration lines to its own ID,
starting with MSB.
• If it detects a difference, it transmits 0s on the arbitration lines for that and all lower bit
positions.
• Device A compares its ID 5 with a pattern 0101 to pattern 0111.
• It detects a difference at bit position 0, as a result, it transmits a pattern 0100 on the
arbitration lines.
• The pattern that appears on the arbitration lines is the logical OR of 0100 and 0110, which
‐
is 0110.
• This pattern is the same as the device ID of B, and hence B has won the arbitration.

Buses
• Primary function
• To provide a communication path for transfer of data
• Bus protocol is set of rules that govern the behavior of various devices connected to the buses
• Bus protocol specifies parameters such as:
• Asserting control signals
• Timing of placing information on bus
• Rate of data transfer
• A typical bus consists of 3 sets of lines
• Address
• Data
• Control lines

Buses
• Specify whether a read or a write operation is to be performed.
• Carry timing information i.e they specify time at which I/O devices place data on the bus
• Read/write line specifies
• Read-operation when R/W=1
• Write-operation when R/W=0
During data transfer operation
• One device plays the role of a bus-master
• Master-device initiates the data-transfer by issuing read/write command on the bus.
• The device addressed by the master is called slave.

Buses
• Two types of Buses:
• Synchronous
• Asynchronous

Synchronous Bus
• All devices derive timing information from a common clock-line
• Information travels over the bus at a speed determined by physical and electrical characteristics
• Clock pulse width (t-t0) must be longer than maximum propagation-delay between devices
connected to bus.
• The clock pulse width should be long enough to allow the devices to decode the address and
control signals.
• The slaves take no action or place any data on the bus before t1.
• Information on bus is unreliable during the period t0 to t1 because signals are changing its state
• The addressed slave places requested input-data on data lines at time t1.
• At end of clock cycle (at time t1), master strobes (captures) the data on the data-lines into its
input-buffer.

Synchronous Bus
• To load data correctly into any storage device (register built with flipflops) the data must be
available at the input of that device for a period greater than the setup time of the device.
• Hence, the period t2-t1 must be greater than the maximum propagation time on the bus plus the
setup time of the input buffer register of the master.
• A similar procedure is followed for an output operation. The master places the output data on the
data lines when it transmits the address and command information.
• At time t2, the addressed device strobes the data lines and loads the data into the buffer.

Synchronous Bus
• Signal takes time to travel from one device to another, hence a given signal transition is seen by
different devices at different times.
• We assume that the clock changes are seen at the same time by all the devices on the bus.

Synchronous Bus
• The master sends the address and command signals on the rising edge at the beginning of the
clock period 1 (t0).
• However, these signals do not appear on the bus until tAM, largely due to the delay in the bus
driver circuit.
• A while later, at tAS, the signals reach the slave.
• The slave decodes the address and at t1 sends the requested data.
• Here, again data signals do not appear on the bus until tDS.
• They travel toward master and arrive at time tDM.
• At time t2, master loads the data into its input buffer.
• Hence the period t2-tDM is the setup time for the master’s input buffer.
• The data must continue to be valid after t2 for period equal to the hold time of that buffer.

Synchronous Bus
Disadvantages
• Because a transfer has to be completed with in one clock cycle, the clock period, t2-t0, must be
chosen to accommodate the longest delays on the bus and the slowest device interface.
• This forces all devices to operate at the speed of the slowest device.
• There is no means for processor to determine whether the addressed device has responded. It
simply assumes that, at t2, the output data have been received by the I/O device or the input
data are available on the data lines.
• If any device fails to respond due to a malfunction, the error will not be detected.

Synchronous Bus
Solution:
• Most buses incorporate control signals that represents a response from the device.
• Theses signals inform the master that the slave has recognized its address and that it is ready to
participate in a data transfer operation.
• They also make it possible to adjust the duration of the data transfer period to suit the needs of
the participating devices.
• To simplify this process, a high-frequency clock is used such that a complete data transfer cycle
would span several clock cycles.
• The number of clock cycles involved can vary from one device to another.

Synchronous Bus – Multiple-Cycle Transfers

Synchronous Bus – Multiple-Cycle Transfers
• During clock cycle-1, master sends address/command into the bus requesting a “read” operation.
• The slave receives and decodes address/command information
• At the active edge of the clock i.e. the beginning of the clock cycle-2, it makes decision respond
and begins to access the requested data.
• Due to assumption that some delay is involved in getting the data, and hence slave cannot
respond immediately.
• The master, which has been waiting for this signal, strobes the data into its input buffer at the end
of clock cycle 3.
• The bus transfer operation is now complete.
• And the master sends a new address to start a new transfer in clock cycle 4.
• The slave ready is the acknowledgement from the slave to the master, confirming valid that valid
data have been sent.

Asynchronous Bus
• This method uses handshake-signals between master and slave for coordinating data-transfer
• There are 2 control-lines
• Master ready (MR) is used to indicate that master is ready for transaction.
• Slave ready (SR) is used to indicate that slave is ready for a transaction.

Asynchronous Bus
• Read operation

Asynchronous Bus
• Read operation
• A t0 master places address/command information on bus.
• At t1, master sets MR-signal to 1 to inform all devices that the address/command –info is ready.
• MR-signal = 1 causes all devices on the bus to decode the address.
• The delay t1-t0 is intended to allow for any skew that may occur on the bus.
• Skew occurs when 2 signals transmitted from one source arrive at destination at different time.
• Therefore, the delay t1-t0 should be larger than the maximum possible bus skew
• At t2, slave:
• Performs required input-operation and
• Sets SR signal to 1 to inform all devices that is ready

• At t3, Sr signal arrives at master indicating that the input-data are available on bus
• At t4, master removes address/command information from bus.
• At t5, when the device-interface receives the 1-to-0 transition of MR signal, it removes data and
SR signal from the bus. This completes the input transfer.

Asynchronous Bus
• The master places the output data on the data lines at the same time that it transmits the address
and command information.
• The selected slave strobes the data into its output buffer when it receives the Master-ready signal
and indicates that it has done so by setting the slave-ready signal to 1.
• In timing diagram, it is assumed that the master compensates for the bus skew and address
decoding delay. It introduces delay from t0 to t1 and from t3 to t4 for this purpose.
• If this delay provides sufficient time for the I/O device interface to decode the address, the
interface circuit can use the Master-ready signal directly to gate other signals to or from the bus.

Interface Circuits
• I/O interface consists of the circuitry required to connect an I/O device to a computer bus.
• On one side of the interface we have bus signals for:
• Address
• Data
• Control
• On the other side, we have a data path with its associated controls to transfer data between the
interface and the I/O device known as port.
• Ports can be classified into two:
• Parallel port
• Serial port

Interface Circuits
• Parallel port transfers data in the form of a number of bits, normally 8 or 16 to or from the device.
• Serial port transfer and receives data one bit at a time.
• Processor communication with the bus in the same way, whether it is a parallel port or a serial
port.
• The conversion from the parallel to the serial format and vice versa takes place inside the
interface circuit.
• In parallel-port the connection between the device and the computer uses
• A multiple-pin connector and
• A cable with as many wires
• This arrangement is suitable for devices that are physically close to the computer.
• In serial port, it is much more convenient and cost-effective where longer cables are needed.

Interface Circuits
• Functions of I/O interface
• Provides a storage buffer for at least one word of data.
• Contains status-flags that can be accessed by the processor to determine whether the buffer is
full or empty.
• Contains address-decoding circuitry to determine when it is being addressed by the processor.
• Generates the appropriate timing signals required by the bus control scheme.
• Performs any format conversion that may be necessary to transfer data between the bus and the
I/O device (such as parallel-serial conversion in the case of a serial port).

Interface circuits – Parallel Port

• On the keyboard side of the interface
• Encoder circuit which generates a code for the key pressed.
• Debouncing circuit which eliminates the effect of a key bounce (a single key stroke may appear as
multiple events to a processor).
• Data lines contain the code for the key.
• Valid line changes from 0to1 when the key is pressed. This causes the code to be loaded into
DATAIN and SIN to be set to ‘1’.
• The encoder output consists of
• Bits representing the encoded character and
• One signal called valid, which indicates the key pressed.

• Interface-circuits contain
• Data register DATAIN and
• Status flag SIN
• When a key is pressed, the valid signal changes from 0 to 1. then SIN = 1 when ASCII code is
loaded into DATAIN
• The interface-circuit is connected to the asynchronous bus.
• Data transfers on the bus are controlled using the handshake signals.
• Master ready
• Slave ready

Interface Circuits – Parallel Port
• Input interface circuit:
Figure 4.29: Input-interface-circuit

• Output-lines of DATAIN are connected to the data-lines of bus by means of 3-state drivers (Fig
4.29).
• Drivers are turned on when
• → processor issues a read signal and
• → address selects DATAIN.
• SIN signal is generated using a status-flag circuit (Figure 4.30).
• SIN signal is connected to line D0 of the processor-bus using a 3-state driver.
• Address-decoder selects the input-interface based on bits A1 through A31.
• Bit A0 determines whether the status or data register is to be read, when Master-ready is active.
• Processor activates the Slave-ready signal, when either the Read-status or Read-data is equal to 1.

• Printer interfaced to processor

• Printer interfaced to processor
• The interface contains a data register DATAOUT and a status flag, SOUT
• The SOUT flag is set to 1 when the printer is ready to accept another character and it is cleared to
0 when a new character is loaded into DATAOUT by the processor.
• When the printer is ready to accept a character it asserts its idle signal.
• On the processor-side of the interface we have
• Data lines
• Address lines
• Control or R/W line
• Master-Ready signal and
• Slave-Ready signal

Combined input/output interface circuit

Combined input/output interface circuit
• In this case, the over all interface is selected by the high-order 30 bits of the address. Address bits
A1 and A0 select one of the three addressable locations in the interface.
The addressable locations are:
• Two data registers
• Status register
• The status register contains the flags SIN and SOUT in bits 0 and 1, respectively.
• Since such locations in I/O interfaces are often referred to as registers, they are labeled as RS1
and RS0 (for register select) to denote the two inputs that determine the register being selected.
This circuit has separate input and output data lines for connection to an I/O device.

Figure 4.34: General 8 bit parallel interface

• A general 8-bit parallel interface:
• It is a more flexible parallel port, since the data lines to I/O devices are bidirectional.
• Data-lines P7 through PO can be used for either input or output purposes (Figure 4.34).
• For increased flexibility,
• some lines can be used as inputs and
• some lines can be used as outputs.
• The DATAOUT register is connected to data-lines via 3-state drivers that are controlled by a DDR.
• The processor can write any 8-bit pattern into DDR. (DDR  Data Direction Register).
• If DDR=1,
• Then, data-line acts as an output-line;
• Otherwise, data-line acts as an input-line.

• Two lines, C1 and C2 are used to control the interaction between interface-circuit and I/0
device. Two lines, C1 and C2 are also programmable.
• Line C2 is bidirectional to provide different modes of signaling, including the handshake.
• The Ready and Accept lines are the handshake control lines on the processor-bus side.
Hence, the Ready and Accept lines can be connected to Master-ready and Slave-ready.
• The input signal My-address should be connected to the output of an address-decoder. The
address-decoder recognizes the address assigned to the interface.
• There are 3 register select lines: RS0-RS2. Three register select lines allows up to eight
registers in the interface.
• An interrupt-request INTR is also provided. INTR should be connected to the interrupt-
request line on the computer-bus.

Interface Circuit – Serial port

• Serial port is used to connect the processor to I/O devices that require transmission of data one
bit at a time.
• Serial port communicates in a bit-serial fashion on the device side and bit parallel fashion on the
bus side.
• Transformation between the parallel and serial formats is achieved with shift registers that have
parallel access capability.
• Serial interface requires fewer wires and hence serial transmission is convenient for connecting
devices that are physically distant from the computer.
• Speed f transmission of the data over a serial interface is known as the “bit rate”.
• Bit rate depends on the nature of the devices connected.
• In order to accommodate devices with a range of speeds, a serial interface must be able to use a
range of clock speed.

• Several standard serial interfaces have been developed.
• Universal Asynchronous Receive Transmitter (UART) for low-speed serial devices.
• RS-232C for connection to communication links

Standard I/O Interface
• Standard interfaces have been developed to enable I/O devices to use interfaces that are
independent of a particular processor.
• Most standards are developed by a collaborative effort among many companies.
• Two buses are interconnected by a circuit called a bridge, that translates the signals and protocols
of one bus into those of the other.
• The bridge-circuit introduces a small delay in data transfer between processor and the devices.

Standard I/O interface
• It is not possible to define a uniform for the processor bus. Because the processor bus structure
depends on the following:
• Architecture of the processor.
• Electrical characteristics of the processor chip (like clock speed).
• Whereas the expansion bus is not subject to these limitations and therefore it can use a
standardized signaling scheme.
• Several standards have been developed for example: IBM developed a bus called ISA (Industry
Standard Architecture) for their personal computer known at the time as PC AT.
• IEEE, ANSI or ISO have given official status for the standards developed through industrial
cooperative efforts.

Standard I/O interface
• The 3 widely used standard I/O interfaces are:
• PCI (Peripheral Component Interconnect)
• SCSI (Small Computer System Interface)
• USB (Universal Serial Bus)
• PCI defines an expansion bus on the motherboard.
• SCSI and USB are used for connecting additional devices both inside and outside the computer system.
• SCSI bus is a high-speed parallel bus intended for devices such as disk and video display.
• USB uses a serial transmission to suit the needs of equipment ranging from keyboard to game control
to internal connection.
• IDE (Integrated Device Electronics) disk is compatible with ISA which shows the connection to an
Ethernet.

Standard I/O Interfaces – PCI Bus
Peripheral Component Interconnect (PCI) Bus
• PCI is developed as a low-cost bus that is truly processor-independent.
• PCI supports high-speed disk, graphics, and video devices.
• PCI has plug-and-play capability for connecting I/O devices.
• To connect new devices, the user simply connects the device interface board to the bus.

Data transfer in PCI
• The data are transferred between the cache and main memory.
• The data is a sequence of words that are stored in successive memory locations.
• During read-operation,
• When the processor specifies an address, the memory responds by sending a sequence of
data words from successive memory locations at that address.
• During write-operation,
• When the processor sends an address, a sequence of data words is written into successive
memory locations at that address.

• PCI supports read and write operations.
• A read/write operation involving a single word is treated as a burst of length one.
• PCI has 3 address spaces. They are
• Memory address-space
• I/O address-space &
• Configuration address space.
• I/O Address-space  Intended for use with processor.
• Configuration space  Intended to give PCI, its plug-and-play capability.

• PCI Bridge provides a separate physical connection to main memory.
• The master maintains the address information on the bus until the data transfer is completed.
• At any time, only one device acts as Bus-Master.
• A master is called an “initiator” which is either a processor or DMA.
• The addressed-device that responds to read and write commands is called a Target.
• A complete transfer operation on the bus, involving an address and burst of data is called a
transaction.
• Individual word transfers are called “phases’.

Read operation on PCI

• During Clock cycle-1,
 The processor a
→ asserts FRAME# to indicate the beginning of a transaction;
→ sends the address on AD lines and command on C/BE# Lines.
 The processor removes the address and disconnects its drivers from AD lines.
 Selected target
→ enables its drivers on AD lines and
→ fetches the requested-data to be placed on bus.

• C/BE# is
→ used to send a bus command and it is
→ used for different purpose during the rest of the transaction.
The initiator asserts IRDY# to indicate that it is ready to receive data.
If the target has data ready to send then it asserts TRDY#. In our eg, the target sends 3 more
words of data in clock cycle 4 to 6.

• During Clock cycle-5
The indicator uses FRAME# to indicate the duration of the burst, since it read 4 words, the
initiator negates FRAME# during clock cycle 5.
After sending 4th word, the target
→ disconnects its drivers and
→ negates DEVSEL# during clock cycle 7.

Device Configuration of PCI Bus
• The PCI has a configuration ROM that stores information about that device.
• The configuration ROM’s of all devices are accessible in the configuration address-space.
• The initialization software read these ROM’s whenever the system is powered up or reset.
• In each case, it determines whether the device is a printer, keyboard or disk controller.
• Devices are assigned address during initialization process.

Device Configuration of PCI Bus
• Each device has an input signal called IDSEL# (Initialization device select) which has 21 address- lines (AD11 to AD31).
• During configuration operation,
 The address is applied to AD input of the device and
 The corresponding AD line is set to 1 and all other lines are set to 0.
AD11 - AD31  Upper address-line
A0 - A10  Lower address-line: Specify the type of the operation and to access the content of device
configuration ROM.
• The configuration software scans all 21 locations. PCI bus has interrupt-request lines.
• Each device may requests an address in the I/O space or memory space

Standard I/O Interfaces – SCSI Bus
• SCSI stands for Small Computer System Interface.
• SCSI refers to the standard bus which is defined by ANSI (American National Standard Institute).
• SCSI bus the several options. It may be,

• Because of these various options, SCSI connector may have 50, 68 or 80 pins. The data transfer
rate ranges from 5MB/s to 160MB/s 320Mb/s, 640MB/s. The transfer rate depends on,
1) Length of the cable
2) Number of devices connected.
• To achieve high transfer rate, the bus length should be 1.6m for SE signaling and 12m for LVD
signaling.
• The SCSI bus is connected to the processor-bus through the SCSI controller. The data are stored
on a disk in blocks called sectors.
• Each sector contains several hundreds of bytes. These data will not be stored in contiguous
memory-location.
• SCSI protocol is designed to retrieve the data in the first sector or any other selected sectors.
• Using SCSI protocol, the burst of data are transferred at high speed.

• The controller connected to SCSI bus is of 2 types. They are1) Initiator 2) Target
1. Initiator
It has the ability to select a particular target & to send commands specifying the
operation to be performed.
They are the controllers on the processor side.
2. Target
The disk controller operates as a target.
It carries out the commands it receive from the initiator.
The initiator establishes a logical connection with the intended target.

Steps for Read-operation
1. The SCSI controller contends for control of the bus (initiator).
2. When the initiator wins the arbitration-process, the initiator
→ selects the target controller and
→ hands over control of the bus to it.
3. The target starts an output operation. The initiator sends a command specifying the required
read- operation.
4. The target
→ sends a message to initiator indicating that it will temporarily suspend connection b/w
them.
→ then releases the bus.

Steps for Read-operation
5. The target controller sends a command to the disk drive to move the read head to the first
sector involved in the requested read-operation.
6. The target
→ transfers the contents of the data buffer to the initiator and
→ then suspends the connection again.
7. The target controller sends a command to the disk drive to perform another seek operation.
8. As the initiator controller receives the data, it stores them into the main-memory using the
DMA approach.
9. The SCSI controller sends an interrupt to the processor indicating that the data are now
available.

Bus signals of SCSI
• The bus has no address-lines. Instead, it has data-lines to identify the bus-controllers involved in the
selection/reselection/arbitration-process.
• For narrow bus, there are 8 possible controllers numbered from 0 to 7. For a wide bus, there are 16 controllers.
• Once a connection is established b/w two controllers, there is no further need for addressing and the data-lines
are used to carry the data.
• All signal names are proceeded by minus sign.
• This indicates that the signals are active or that the data-line is equal to 1, when they are in the low voltage
state.

Bus signals of SCSI
Category Name Function
Data -DB0 to –DB7
-DB(P)
Data lines: carry one byte of information during the
information transformation phase and identify
device during arbitration, selection and reselection
phases.
Parity bit for the data bus
Phase -BSY
-SEL
BUSY: Asserted when bus is not free
Selection: Asserted during selection and reselection
Information type -C/D
-MSG
Control/Data: Asserted during the transformation
of control information (Command, Status, message)
Message: Indicates that information being
transferred is a message

Bus signals of SCSI
Category Name Function
Handshake -REQ
-ACK
Request: Asserted by a target to request a data
transfer cycle.
Acknowledge: Asserted by initiator when it has
completed a data transfer operation.
Direction of
transfer
-I/O Input/Output: Asserted to indicate an input/output
operation (relative to the initiator).
Other -ATN
-RST
Attention: Asserted by initiator when it wishes to
send message to a target.
Reset: Causes all device controls to disconnect from
the bus and assume their start-up state.

PHASES IN SCSI BUS
The phases in SCSI bus operation are:
• Arbitration
• Selection
• Information transfer
• Reselection

1. Arbitration
• When the –BSY signal is in inactive state,
→ the bus will be free &
→ any controller can request the use of bus.
• SCSI uses distributed arbitration scheme because each controller may generate requests at the
same time.
• Each controller on the bus is assigned a fixed priority.
• When –BSY becomes active, all controllers that are requesting the bus
→ examines the data-lines &
→ determine whether highest priority device is requesting bus at the same time.

1. Arbitration
• The controller using the highest numbered line realizes that it has won the arbitration-process.
• At that time, all other controllers disconnect from the bus & wait for –BSY to become inactive again.
2. Information Transfer
• The information transferred between two controllers may consist of
→ commands from the initiator to the target
→ status responses from the target to the initiator or
→ data-transferred to/from the I/0 device.
• Handshake signaling is used to control information transfers, with the target controller taking the role of the bus-
master.

3. Selection
• Here, Device
→ wins arbitration and
→ asserts –BSY and –DB6 signals.
• The Select Target Controller responds by asserting –BSY.
• This informs that the connection that it requested is established.
4. Reselection
• The connection between the two controllers has been reestablished, with the target in control of
the bus as required for data transfer to proceed.

Standard I/O Interface – Universal Serial Bus
(USB)
• USB stands for Universal Serial Bus.
• USB supports 3 speed of operation. They are,
1) Low speed (1.5 Mbps)
2) Full speed (12 mbps) &
3) High speed (480 mbps).
• The USB has been designed to meet the key objectives. They are,
1) Provide a simple, low-cost and easy to use interconnection system.
This overcomes difficulties due to the limited number of I/O ports available on a computer.
2) Accommodate a wide range of data transfer characteristics for I/O devices. For e.g. telephone and Internet
connections
3) Enhance user convenience through a “plug-and-play” mode of operation.

(USB)
USB Features
• Simple Connectivity
• Simple Cables
• One interface for many devices
• Automatic configuration
• No user setting
• Frees hardware resources for other devices
• Hot pluggable (Plug and Play)
• Data transfer rates
• Low cost and reliability

(USB)
• Advantage: USB helps to add many devices to a computer system at any time without opening the
computer-box.
Port Limitation
• Normally, the system has a few limited ports.
• To add new ports, the user must open the computer-box to gain access to the internal
expansion bus & install a new interface card.
• The user may also need to know to configure the device & the s/w.

(USB)
• Plug & Play
The main objective: USB provides a plug & play capability.
The plug & play feature enhances the connection of new device at any time, while the system
is operation.
The system should
→ Detect the existence of the new device automatically.
→ Identify the appropriate device driver s/w.
→ Establish the appropriate addresses.
→ Establish the logical connection for communication.

(USB)
Device Characteristics of USB
• The kinds of devices that may be connected to a computer cover a wide range of functionality.
• The speed, volume & timing constrains associated with data transfer to & from devices varies
significantly.
Eg: 1 Keyboard
Since the event of pressing a key is not synchronized to any other event in a computer system, the
data generated by keyboard are called asynchronous.
The data generated from keyboard depends upon the speed of the human operator which is about
100 bytes/sec.

(USB)
Device Characteristics of USB
Eg: 2 Microphone attached in a computer system internally/externally
The sound picked up by the microphone produces an analog electric signal, which must be
converted into digital form before it can be handled by the computer.
This is accomplished by sampling the analog signal periodically.
The sampling process yields a continuous stream of digitized samples that arrive at regular
intervals, synchronized with the sampling clock. Such a stream is called isochronous (i.e.)
successive events are separated by equal period of time.
If the sampling rate in „S‟ samples/sec then the maximum frequency captured by sampling
process is s/2.
A standard rate for digital sound is 44.1 KHz.

(USB)
USB Architecture

(USB)
USB Architecture
• To accommodate a large number of devices that can be added or removed at any time, the USB
has the tree structure as shown in the figure 7.17.
• Each node of the tree has a device called a Hub.
• A hub acts as an intermediate control point between the host and the I/O devices.
• At the root of the tree, a Root Hub connects the entire tree to the host computer.
• The leaves of the tree are the I/O devices being served (for example, keyboard or speaker).

(USB)
USB Architecture
• A hub copies a message that it receives from its upstream connection to all its downstream ports.
• As a result, a message sent by the host computer is broadcast to all I/O devices, but only the
addressed-device will respond to that message.

(USB)
USB Addressing
• Each device may be a hub or an I/O device.
• Each device on the USB is assigned a 7-bit address.
• This address
→ is local to the USB tree and
→ is not related in any way to the addresses used on the processor-bus.
• A hub may have any number of devices or other hubs connected to it, and addresses are assigned
arbitrarily.
• When a device is first connected to a hub, or when it is powered-on, it has the address 0.

(USB)
USB Addressing
• The hardware of the hub detects the device that has been connected, and it records this fact as
part of its own status information.
• Periodically, the host polls each hub to
→ collect status information and
→ learn about new devices that may have been added or disconnected.

(USB)
USB Addressing
• When the host is informed that a new device has been connected, it uses sequence of commands
to
→ send a reset signal on the corresponding hub port.
→ read information from the device about its capabilities.
→ send configuration information to the device, and
→ assign the device a unique USB address (enumeration).
• Once this sequence is completed, the device
→ begins normal operation and
→ responds only to the new address.

(USB)
USB Addressing
• The endpoints are the locations in the device to or from which data transfer can takes place.
• These are the status, control and data registers.
• They are identified by the 4 bit number.
• Each 4-bit value identifies a pair of endpoints, one for input and one for output.
• The 4-bit endpoint number is part of the addressing information sent by the host.

(USB)
USB Protocols
• All information transferred over the USB is organized in packets.
• A packet consists of one or more bytes of information.
• There are many types of packets that perform a variety of control functions.
• The information transferred on USB is divided into 2 broad categories: 1) Control and 2) Data.
• Control packets perform tasks such as
→ addressing a device to initiate data transfer.
→ acknowledging that data have been received correctly or
→ indicating an error.

(USB)
USB Protocols
• Data-packets carry information that is delivered to a device.
• A packet consists of one or more fields containing different kinds of information.
• The first field of any packet is called the Packet Identifier (PID) that contain identifying information.
Depending on the transaction, the PID may be followed by an endpoint address, status information, or frame
along with error checking bits.
• They are transmitted twice.
1) The first time they are sent with their true values and
2) The second time with each bit complemented.
• The four PID bits identify one of 16 different packet types.
• Some control packets, such as ACK (Acknowledge), consist only of the PID byte.
• Control packets used for controlling data transfer operations are called Token Packets.

(USB)
USB Protocols

(USB)
USB Protocols
• The USB uses the ACK (acknowledge) and NAK (Not Acknowledge) tokens to coordinate the
transfer of data packets between the host system.
• Once data packet is transferred from the host to the USB device, the USB device either transmits
an ACK or NAK token back to the host.
• If the data and CRC are received with out error then device sends ACK else NAK is sent.
• If the host receives a NAK token, it will retransmits the data packet until the receiver receives it
without errors. This method of data transfer is known as stop and wait flow control.

Important Questions
• List the differences between memory mapped I/O and I/O mapped I/O.
• With neat sketches, explain the various methods for handling multiple interrupts requests raised
by multiple devices.
• With neat diagram, explain centralized bus arbitration and distributed bus arbitration.
• Explain the I/O interface for an input device to the processor with a neat block diagram.
• With a neat diagram, explain synchronous bus transfer during an input operation.
• Explain the tree structure of USB with split bus operation.

Important Questions
Illustrate a program that reads one line from keyboard, stores it in memory buffer, and echoes it
back to the display in an I/O interfaces.
What is interrupt? What are interrupt service routines and what are vectored interrupts? Explain
with examples.
Demonstrate the DMA and its implementation and show how the data is transferred between
memory and I/O devices using DMA controller.
With a neat diagram explain the general 8-bit parallel interface circuits.
Explain PCI data bus in a computer system.
What is DMA bus arbitration? Explain different but arbitration technique.
Explain synchronous and asynchronous bus with neat diagrams.
With help of timing diagram explain the read operation on the PCI bus.

Important questions
• What is direct memory Access, when it is used? Explain it with block diagram,
• Define the terms cycle stealing and burst mode with respect to DMA.
• Define the bus arbitration. Explain in detail centralized bus arbitration.
• With a block diagram, explain how the keyboard is connected to processor.
• Explain the use of a PCI bus in a computer system with a neat sketch.
• What are design objectives of USB?
• Explain synchronous bus and asynchronous bus with neat timing diagrams.
• Enumerate the features of Universal Synchronous Bus (USB).
• Describe how a read operation is performed in a PCI bus.

Important questions
• Explain interrupt and interrupt hardware. State steps in enabling and disabling interrupts.
• Explain interrupt nesting and handling simultaneous requests in interrupts.
• Explain DMA transfer with bus arbitration.
• Explain USB Tree structure and protocols.
• Define bus arbitration. Explain the two approaches to bus arbitration.
• With help of timing diagram, explain the read operation on the PCI bus.

Computer Organization and Architecture_Unit 1_part b.pptx

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