Datasheet ni

Datasheet ni

• 1.
  TL082 Wide Bandwidth DualJFET Input Operational Amplifier General Description These devices are low cost, high speed, dual JFET input op- erational amplifiers with an internally trimmed input offset voltage (BI-FET II™ technology). They require low supply current yet maintain a large gain bandwidth product and fast slew rate. In addition, well matched high voltage JFET input devices provide very low input bias and offset currents. The TL082 is pin compatible with the standard LM1558 allowing designers to immediately upgrade the overall performance of existing LM1558 and most LM358 designs. These amplifiers may be used in applications such as high speed integrators, fast D/A converters, sample and hold cir- cuits and many other circuits requiring low input offset volt- age, low input bias current, high input impedance, high slew rate and wide bandwidth. The devices also exhibit low noise and offset voltage drift. Features n Internally trimmed offset voltage: 15 mV n Low input bias current: 50 pA n Low input noise voltage: 16nV/√Hz n Low input noise current: 0.01 pA/√Hz n Wide gain bandwidth: 4 MHz n High slew rate: 13 V/µs n Low supply current: 3.6 mA n High input impedance: 1012 Ω n Low total harmonic distortion AV = 10,: <0.02% RL = 10k, VO = 20 Vp − p, BW = 20 Hz−20 kHz n Low 1/f noise corner: 50 Hz n Fast settling time to 0.01%: 2 µs Typical Connection Connection Diagram Simplified Schematic BI-FET II™ is a trademark of National Semiconductor Corp. DS008357-1 DIP/SO Package (Top View) DS008357-3 Order Number TL082CM or TL082CP See NS Package Number M08A or N08E DS008357-2 April 1998 TL082WideBandwidthDualJFETInputOperationalAmplifier © 1999 National Semiconductor Corporation DS008357 www.national.com
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  Absolute Maximum Ratings(Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ±18V Power Dissipation (Note 2) Operating Temperature Range 0˚C to +70˚C Tj(MAX) 150˚C Differential Input Voltage ±30V Input Voltage Range (Note 3) ±15V Output Short Circuit Duration Continuous Storage Temperature Range −65˚C to +150˚C Lead Temp. (Soldering, 10 seconds) 260˚C ESD rating to be determined. Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. DC Electrical Characteristics (Note 5) Symbol Parameter Conditions TL082C Units Min Typ Max VOS Input Offset Voltage RS = 10 kΩ, TA = 25˚C 5 15 mV Over Temperature 20 mV ∆VOS/∆T Average TC of Input Offset RS = 10 kΩ 10 µV/˚C Voltage IOS Input Offset Current Tj = 25˚C, (Notes 5, 6) 25 200 pA Tj ≤ 70˚C 4 nA IB Input Bias Current Tj = 25˚C, (Notes 5, 6) 50 400 pA Tj ≤ 70˚C 8 nA RIN Input Resistance Tj = 25˚C 1012 Ω AVOL Large Signal Voltage Gain VS = ±15V, TA = 25˚C 25 100 V/mV VO = ±10V, RL = 2 kΩ Over Temperature 15 V/mV VO Output Voltage Swing VS = ±15V, RL = 10 kΩ ±12 ±13.5 V VCM Input Common-Mode Voltage VS = ±15V ±11 +15 V Range −12 V CMRR Common-Mode Rejection Ratio RS ≤ 10 kΩ 70 100 dB PSRR Supply Voltage Rejection Ratio (Note 7) 70 100 dB IS Supply Current 3.6 5.6 mA AC Electrical Characteristics (Note 5) Symbol Parameter Conditions TL082C Units Min Typ Max Amplifier to Amplifier Coupling TA = 25˚C, f = 1Hz- −120 dB 20 kHz (Input Referred) SR Slew Rate VS = ±15V, TA = 25˚C 8 13 V/µs GBW Gain Bandwidth Product VS = ±15V, TA = 25˚C 4 MHz en Equivalent Input Noise Voltage TA = 25˚C, RS = 100Ω, 25 nV/√Hz f = 1000 Hz in Equivalent Input Noise Current Tj = 25˚C, f = 1000 Hz 0.01 pA/√Hz Note 2: For operating at elevated temperature, the device must be derated based on a thermal resistance of 115˚C/W junction to ambient for the N package. Note 3: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage. Note 4: The power dissipation limit, however, cannot be exceeded. Note 5: These specifications apply for VS = ±15V and 0˚C ≤TA ≤ +70˚C. VOS, IB and IOS are measured at VCM = 0. Note 6: The input bias currents are junction leakage currents which approximately double for every 10˚C increase in the junction temperature, Tj. Due to the limited production test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambient temperature as a result of internal power dissipation, PD. Tj = TA + θjA PD where θjA is the thermal resistance from junction to ambient. Use of a heat sink is recom- mended if input bias current is to be kept to a minimum. Note 7: Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with common practice. VS = ±6V to ±15V. www.national.com 2
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  Typical Performance Characteristics InputBias Current DS008357-18 Input Bias Current DS008357-19 Supply Current DS008357-20 Positive Common-Mode Input Voltage Limit DS008357-21 Negative Common-Mode Input Voltage Limit DS008357-22 Positive Current Limit DS008357-23 Negative Current Limit DS008357-24 Voltage Swing DS008357-25 Output Voltage Swing DS008357-26 www.national.com3
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  Typical Performance Characteristics(Continued) Gain Bandwidth DS008357-27 Bode Plot DS008357-28 Slew Rate DS008357-29 Distortion vs Frequency DS008357-30 Undistorted Output Voltage Swing DS008357-31 Open Loop Frequency Response DS008357-32 Common-Mode Rejection Ratio DS008357-33 Power Supply Rejection Ratio DS008357-34 Equivalent Input Noise Voltage DS008357-35 www.national.com 4
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  Typical Performance Characteristics(Continued) Pulse Response Open Loop Voltage Gain (V/V) DS008357-36 Output Impedance DS008357-37 Inverter Setting Time DS008357-38 Small Signal Inverting DS008357-6 Small Signal Non-Inverting DS008357-7 Large Signal Inverting DS008357-8 Large Signal Non-Inverting DS008357-9 www.national.com5
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  Pulse Response (Continued) ApplicationHints These devices are op amps with an internally trimmed input offset voltage and JFET input devices (BI-FET II). These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need for clamps across the inputs. Therefore, large differential input voltages can easily be accommodated without a large increase in input current. The maximum differential input voltage is independent of the supply voltages. However, neither of the input voltages should be allowed to exceed the negative supply as this will cause large currents to flow which can result in a destroyed unit. Exceeding the negative common-mode limit on either input will cause a reversal of the phase to the output and force the amplifier output to the corresponding high or low state. Ex- ceeding the negative common-mode limit on both inputs will force the amplifier output to a high state. In neither case does a latch occur since raising the input back within the common-mode range again puts the input stage and thus the amplifier in a normal operating mode. Exceeding the positive common-mode limit on a single input will not change the phase of the output; however, if both in- puts exceed the limit, the output of the amplifier will be forced to a high state. The amplifiers will operate with a common-mode input volt- age equal to the positive supply; however, the gain band- width and slew rate may be decreased in this condition. When the negative common-mode voltage swings to within 3V of the negative supply, an increase in input offset voltage may occur. Each amplifier is individually biased by a zener reference which allows normal circuit operation on ±6V power sup- plies. Supply voltages less than these may result in lower gain bandwidth and slew rate. The amplifiers will drive a 2 kΩ load resistance to ±10V over the full temperature range of 0˚C to +70˚C. If the amplifier is forced to drive heavier load currents, however, an increase in input offset voltage may occur on the negative voltage swing and finally reach an active current limit on both posi- tive and negative swings. Precautions should be taken to ensure that the power supply for the integrated circuit never becomes reversed in polarity or that the unit is not inadvertently installed backwards in a socket as an unlimited current surge through the resulting forward diode within the IC could cause fusing of the internal conductors and result in a destroyed unit. Because these amplifiers are JFET rather than MOSFET in- put op amps they do not require special handling. As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in order to ensure stability. For example, resistors from the output to an input should be placed with the body close to the input to minimize “pick-up” and maximize the frequency of the feed- back pole by minimizing the capacitance from the input to ground. A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and capacitance from the input of the device (usually the inverting input) to AC ground set the frequency of the pole. In many instances the frequency of this pole is much greater than the expected 3 dB frequency of the closed loop gain and consequently there is negligible effect on stability margin. However, if the feed- back pole is less than approximately 6 times the expected 3 dB frequency a lead capacitor should be placed from the out- put to the input of the op amp. The value of the added ca- pacitor should be such that the RC time constant of this ca- pacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant. Current Limit (RL = 100Ω) DS008357-10 www.national.com 6
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  Detailed Schematic Typical Applications DS008357-11 Three-BandActive Tone Control DS008357-12 www.national.com7
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  Typical Applications (Continued) DS008357-13 •All potentiometers are linear taper • Use the LF347 Quad for stereo applications Note 8: All controls flat. Note 9: Bass and treble boost, mid flat. Note 10: Bass and treble cut, mid flat. Note 11: Mid boost, bass and treble flat. Note 12: Mid cut, bass and treble flat. Improved CMRR Instrumentation Amplifier DS008357-14 C and E are separate isolated grounds Matching of R2’s, R4’s and R5’s control CMRR With AVT = 1400, resistor matching = 0.01%: CMRR = 136 dB • Very high input impedance • Super high CMRR www.national.com 8
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  Typical Applications (Continued) FourthOrder Low Pass Butterworth Filter DS008357-15 Fourth Order High Pass Butterworth Filter DS008357-16 www.national.com9
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  Typical Applications (Continued) Ohmsto Volts Converter DS008357-17 www.national.com 10
• 11.
  Physical Dimensions inches(millimeters) unless otherwise noted Order Number TL082CM NS Package M08A Order Number TL082CP NS Package N08E www.national.com11
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  Notes LIFE SUPPORT POLICY NATIONAL’SPRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: [email protected] National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 www.national.com TL082WideBandwidthDualJFETInputOperationalAmplifier National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.