© 2000 Fairchild Semiconductor Corporation DS006398 www.fairchildsemi.com
August 1986
Revised April 2000
DM74LS1648-BitSerialIn/ParallelOutShiftRegister
DM74LS164
8-Bit Serial In/Parallel Out Shift Register
General Description
These 8-bit shift registers feature gated serial inputs and
an asynchronous clear. A low logic level at either input
inhibits entry of the new data, and resets the first flip-flop to
the low level at the next clock pulse, thus providing com-
plete control over incoming data. A high logic level on
either input enables the other input, which will then deter-
mine the state of the first flip-flop. Data at the serial inputs
may be changed while the clock is HIGH or LOW, but only
information meeting the setup and hold time requirements
will be entered. Clocking occurs on the LOW-to-HIGH level
transition of the clock input. All inputs are diode-clamped to
minimize transmission-line effects.
Features
s Gated (enable/disable) serial inputs
s Fully buffered clock and serial inputs
s Asynchronous clear
s Typical clock frequency 36 MHz
s Typical power dissipation 80 mW
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram Function Table
H = HIGH Level (steady state)
L = LOW Level (steady state)
X = Don't Care (any input, including transitions)
↑ = Transition from LOW-to-HIGH level
QA0, QB0, QH0 = The level of QA, QB, or QH, respectively, before the
indicated steady-state input conditions were established.
QAn, QGn = The level of QA or QG before the most recent ↑ transition of the
clock; indicates a one-bit shift.
Order Number Package Number Package Description
DM74LS164M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74LS164N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs Outputs
Clear Clock A B QA QB ... QH
L X X X L L ... L
H L X X QA0 QB0 ... QH0
H ↑ H H H QAn ... QGn
H ↑ L X L QAn ... QGn
H ↑ X L L QAn ... QGn
www.fairchildsemi.com 2
DM74LS164
Logic Diagram
Timing Diagram
3 www.fairchildsemi.com
DM74LS164
Absolute Maximum Ratings(Note 1)
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” tables will define the conditions
for actual device operation.
Recommended Operating Conditions
Note 2: TA = 25°C and VCC = 5V.
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Note 3: All typicals are at VCC = 5V, TA = 25°C.
Note 4: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 5: ICC is measured with all outputs OPEN, the SERIAL input grounded, the CLOCK input at 2.4V, and a momentary ground, then 4.5V, applied to the
CLEAR input.
Switching Characteristics
at VCC = 5V and TA = 25°C
Supply Voltage 7V
Input Voltage 7V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range −65°C to +150°C
Symbol Parameter Min Nom Max Units
VCC Supply Voltage 4.75 5 5.25 V
VIH HIGH Level Input Voltage 2 V
VIL LOW Level Input Voltage 0.8 V
IOH HIGH Level Output Current −0.4 mA
IOL LOW Level Output Current 8 mA
fCLK Clock Frequency (Note 2) 0 25 MHz
tW Pulse Width Clock 20
ns
(Note 2) Clear 20
tSU Data Setup Time (Note 2) 17 ns
tH Data Hold Time (Note 2) 5 ns
tREL Clear Release Time (Note 2) 30 ns
TA Free Air Operating Temperature 0 70 °C
Symbol Parameter Conditions Min
Typ
(Note 3)
Max Units
VI Input Clamp Voltage VCC = Min, II = −18 mA −1.5 V
VOH HIGH Level VCC = Min, IOH = Max
2.7 3.4 V
Output Voltage VIL = Max, VIH = Min
VOL LOW Level VCC = Min, IOL = Max
0.35 0.5
Output Voltage VIL = Max, VIH = Min V
IOL = 4 mA, VCC = Min 0.25 0.4
II Input Current @ Max Input Voltage VCC = Max, VI = 7V 0.1 mA
IIH HIGH Level Input Current VCC = Max, VI = 2.7V 20 µA
IIL LOW Level Input Current VCC = Max, VI = 0.4V −0.4 mA
IOS Short Circuit Output Current VCC = Max (Note 4) −20 −100 mA
ICC Supply Current VCC = Max (Note 5) 16 27 mA
From (Input) RL = 2 kΩ
Symbol Parameter To (Output) CL = 15 pF CL = 50 pF Units
Min Max Min Max
fMAX Maximum Clock Frequency 25 MHz
tPLH Propagation Delay Time
Clock to Output 27 30 ns
LOW-to-HIGH Level Output
tPHL Propagation Delay Time
Clock to Output 32 40 ns
HIGH-to-LOW Level Output
tPHL Propagation Delay Time
Clear to Output 36 45 ns
HIGH-to-LOW Level Output
www.fairchildsemi.com 4
DM74LS164
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A
5 www.fairchildsemi.com
DM74LS1648-BitSerialIn/ParallelOutShiftRegister
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com

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Dm74 ls164

  • 1. © 2000 Fairchild Semiconductor Corporation DS006398 www.fairchildsemi.com August 1986 Revised April 2000 DM74LS1648-BitSerialIn/ParallelOutShiftRegister DM74LS164 8-Bit Serial In/Parallel Out Shift Register General Description These 8-bit shift registers feature gated serial inputs and an asynchronous clear. A low logic level at either input inhibits entry of the new data, and resets the first flip-flop to the low level at the next clock pulse, thus providing com- plete control over incoming data. A high logic level on either input enables the other input, which will then deter- mine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is HIGH or LOW, but only information meeting the setup and hold time requirements will be entered. Clocking occurs on the LOW-to-HIGH level transition of the clock input. All inputs are diode-clamped to minimize transmission-line effects. Features s Gated (enable/disable) serial inputs s Fully buffered clock and serial inputs s Asynchronous clear s Typical clock frequency 36 MHz s Typical power dissipation 80 mW Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table H = HIGH Level (steady state) L = LOW Level (steady state) X = Don't Care (any input, including transitions) ↑ = Transition from LOW-to-HIGH level QA0, QB0, QH0 = The level of QA, QB, or QH, respectively, before the indicated steady-state input conditions were established. QAn, QGn = The level of QA or QG before the most recent ↑ transition of the clock; indicates a one-bit shift. Order Number Package Number Package Description DM74LS164M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow DM74LS164N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Inputs Outputs Clear Clock A B QA QB ... QH L X X X L L ... L H L X X QA0 QB0 ... QH0 H ↑ H H H QAn ... QGn H ↑ L X L QAn ... QGn H ↑ X L L QAn ... QGn
  • 3. 3 www.fairchildsemi.com DM74LS164 Absolute Maximum Ratings(Note 1) Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” tables will define the conditions for actual device operation. Recommended Operating Conditions Note 2: TA = 25°C and VCC = 5V. Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Note 3: All typicals are at VCC = 5V, TA = 25°C. Note 4: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 5: ICC is measured with all outputs OPEN, the SERIAL input grounded, the CLOCK input at 2.4V, and a momentary ground, then 4.5V, applied to the CLEAR input. Switching Characteristics at VCC = 5V and TA = 25°C Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range 0°C to +70°C Storage Temperature Range −65°C to +150°C Symbol Parameter Min Nom Max Units VCC Supply Voltage 4.75 5 5.25 V VIH HIGH Level Input Voltage 2 V VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current −0.4 mA IOL LOW Level Output Current 8 mA fCLK Clock Frequency (Note 2) 0 25 MHz tW Pulse Width Clock 20 ns (Note 2) Clear 20 tSU Data Setup Time (Note 2) 17 ns tH Data Hold Time (Note 2) 5 ns tREL Clear Release Time (Note 2) 30 ns TA Free Air Operating Temperature 0 70 °C Symbol Parameter Conditions Min Typ (Note 3) Max Units VI Input Clamp Voltage VCC = Min, II = −18 mA −1.5 V VOH HIGH Level VCC = Min, IOH = Max 2.7 3.4 V Output Voltage VIL = Max, VIH = Min VOL LOW Level VCC = Min, IOL = Max 0.35 0.5 Output Voltage VIL = Max, VIH = Min V IOL = 4 mA, VCC = Min 0.25 0.4 II Input Current @ Max Input Voltage VCC = Max, VI = 7V 0.1 mA IIH HIGH Level Input Current VCC = Max, VI = 2.7V 20 µA IIL LOW Level Input Current VCC = Max, VI = 0.4V −0.4 mA IOS Short Circuit Output Current VCC = Max (Note 4) −20 −100 mA ICC Supply Current VCC = Max (Note 5) 16 27 mA From (Input) RL = 2 kΩ Symbol Parameter To (Output) CL = 15 pF CL = 50 pF Units Min Max Min Max fMAX Maximum Clock Frequency 25 MHz tPLH Propagation Delay Time Clock to Output 27 30 ns LOW-to-HIGH Level Output tPHL Propagation Delay Time Clock to Output 32 40 ns HIGH-to-LOW Level Output tPHL Propagation Delay Time Clear to Output 36 45 ns HIGH-to-LOW Level Output
  • 4. www.fairchildsemi.com 4 DM74LS164 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A
  • 5. 5 www.fairchildsemi.com DM74LS1648-BitSerialIn/ParallelOutShiftRegister Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com