Doering

Doering

• 1.
  Future Prospects forMoore’s Law Eighth Annual High Performance Embedded Computing Workshop Lincoln Laboratory September 28, 2004 Robert Doering Texas Instruments, Inc.
• 2.
  Generalizations of Moore’s Law Exponential trends in: More functions* per chip Increased performance Reduced energy per operation Decreased cost per function ( the principal driver) * transistors, bits, etc. Source: DataQuest, Intel 10 -2 10 -4 1 Price per Transistor in MPU ($) Dollars to Microcents: 10 -6
• 3.
  High-Level CMOS TechnologyMetrics – What are the Limits ? Component Diversity (integrated logic, memory, analog, RF, …) Cost/Component (e.g., μ¢/gate or μ¢/bit in an IC) Component Density (e.g., gates/cm 2 or bits/cm 2 ) Logic Gate Delay (time for a gate to switch logic states) Energy Efficiency (energy/switch and energy/time) Mfg. Cycle Time (determines time-to-market for new designs as well as rate of yield learning) All of these are limited by multiple factors inter-linked into a complex “tradeoff space.” We can only touch on a few of the issues today !
• 4.
  State-of-the-Art CMOS in2004 ITRS Technology Node: 90 nm (half-pitch of DRAM metal lines) 4T-Gates/cm 2 : 37x10 6 (150 million transistors/cm 2 ) 6T-eSRAM bits/cm 2 : 10 8 (600 million transistors/cm 2 ) Cost/Gate (4T): 40 μ¢ (high volume; chip area = 1 cm 2 ) Cost/eSRAM bit: 10 μ¢ (high volume; chip area = 1 cm 2 ) Gate Delay 24 ps * (for 2-input, F.O. = 3 NAND) Switching Energy 0.5 fJ * (for inverter, half-cycle) Passive Power 6 nW * (per minimum-size transistor) Min. Mfg. Cycle Time 10 days (or 3 mask levels/day) * Values at extreme tradeoff for MPU application
• 5.
  Scaling -- TraditionalEnabler of Moore’s Law * 500 350 250 180 130 90 65 45 32 22 Feature Size [nm] Year of Production ITRS Gate Length 9 return to 0.7x/3-yr ? 13 * For Speed, Low-Cost, Low-Power, etc. ITRS Lithography Half-Pitch (DRAM) 95 97 99 01 04 07 10 13 16 95 97 99 01 04 07 10 13 16
• 6.
  Can We Extendthe Recent 0.7x/2-year Litho Scaling Trend ? 3000 2000 1500 1000 400 350 250 180 130 90 65 45 500 600 10 1 10 2 10 3 10 4 1980 1990 2000 2010 Year of Production Above wavelength Near wavelength Below wavelength g-line  =436nm i-line  =365nm DUV  =248nm 193  =193nm 157  =157nm 32  =EUV 13.5nm Half-Pitch / Wavelength (nm) i-193  ‘=133nm For lithography, it’s a question of cost and control/parametric-yield !
• 7.
  A “Bag ofTricks” for Optical-Extension Complexity (mask, use) Strength of enhancement Illumination mode Other (Tool) Mask Mask OPC Resist k 1 0.25 0.5 Conventional Annular Dipole Soft Quasar Custom Scattering bars Quasar Binary Intensity Mask Attenuated PSM 6% Attenuated PSM 18% Alternating PSM Source: ASML Serifs Hammerheads Line Biasing Thick resist Thin resist Focus drilling Phase filters Double Exposures Wavelength NA Of course : increasing complexity  increasing cost !
• 8.
  Amortization of MaskCost @ 130nm ~ 1 million units required to get within 10% of asymptotic cost ! (and getting worse with continued scaling) Significant motivation for some form of “mask-less lithography” !
• 9.
  Of course, overallscaling is limited by more than just lithography ! Growing Significance of Non-Ideal Device-Scaling Effects : I ON vs. I OFF tradeoff unfavorable  and L scaling for interconnects Approaching Limits of Materials Properties Heat removal and temperature tolerance C MAX vs. leakage tradeoff for gate dielectric C MIN vs. mechanical-integrity tradeoff for inter-metal dielectric Increases in Manufacturing Complexity/Control Requirements cost and yield of increasingly complex process flows metrology and control of L GATE , T OX , doping, etc. Affordability of R&D Costs development of more complex and “near cliff” technologies design of more complex circuits with “less ideal” elements
• 10.
  ITRS Tries toAddress Top-Down Goals MPU Clock (GHz) 2001 2003
• 11.
  ITRS Highlights ScalingBarriers, e.g.: Production Year: 2001 2004 2007 2010 2013 2016 Litho Half-Pitch [nm]: 130 90 65 45 32 22 Overlay Control [nm]: 45 32 23 18 13 9 Gate Length [nm]: 65 37 25 18 13 9 CD Control [nm]: 6.3 3.3* 2.2 1.6 1.2 0.8 T OX (equivalent) [nm]: 1.3-1.6 1.2 0.9 0.7 0.6 0.5 I GATE (L MIN ) [µA/µm]: - 0.17 0.23 0.33 1 1.67 I ON (NMOS) [µA/µm]: 900 1110 1510 1900 2050 2400 I OFF (NMOS) [µA/µm]: 0.01 0.05 0.07 0.1 0.3 0.5 Interconnect  EFF  - 3.1-3.6 2.7-3.0 2.3-2.6 2.0-2.4 <2.0
• 12.
  Another Interconnect-Scaling IssueSurface scattering becomes dominant p=0 (diffuse scattering) p=1 (specular scattering) 0 1 2 3 4 5 0 100 200 300 400 500 Metal Line Width (nm) Resistivity (μΩcm) p=0 p=0.5 Wire width < mean-free-path of electrons
• 13.
  2004 LG = 37-nm Transistor T OX (equiv.) = 1.2 nm
• 14.
  Can Some Hi-KDielectric Replace SiON ? Source: Intel Sub-nm SiON: mobility uniformity leakage
• 15.
  In general, continuedtransistor scaling requires new materials, processes, … Selective-epi raised source/drain for shallow junctions & reduced short-channel effects P-WELL STI STI SOURCE DRAIN GATE Si-Substrate Halo I2 Etches for new materials that achieve profile, CD control, and selectivity Metal gate electrode to reduce gate depletion High-  gate dielectric for reducing gate current with thin Tox Strained channel for improved mobility Doping and annealing techniques for shallow abrupt junctions Ni-silicide process for low resistance at short gate lengths (near term)
• 16.
  … and,eventually new structures Steps toward ideal “coax gate”  Fin BOx Tri-Gate FET 3 Gates Fin BOx  / Ω Gate FET 3+ Gates Fin BOx FinFET 2 Gates Thick Dielectric Active Gate Buried Oxide Silicon   Si Si Gate Buried Oxide Silicon
• 17.
  Potential FET Enhancements? Calculations by T. Skotnicki
• 18.
  At PQE 2004,Professor Mark Lundstrom expressed the outlook: “Sub-10nm MOSFETs will operate, but … - on-currents will be ~0.5xI ballistic , off-currents high, - 2D electrostatics will be hard to control, - parasitic resistance will degrade performance, - device to device variations will be large, and - ultra-thin bodies and hyper-abrupt junctions will be essential”
• 19.
  ITRS Assessment ofSome Current Ideas for Successors to CMOS Transistors No obvious candidates yet for a CMOS replacement !
• 20.
  SRC Research GapAnalysis (for <50nm) Worldwide Funding ~ $1,386 M Government Funding Asia-Pacific $103 M Ongoing Tasks $2,169M New Tasks $372M WW Research Gap ~ $1,155M Industry Funding (Semiconductors + Suppliers) U.S. $313 M Japan $142 M Europe $ 74 M ~ $580 M Asia-Pac $ 51 M U.S. $329 M Europe $249 M Japan $125 M ~ $806 M Worldwide Needs ~ $2,541 M
• 21.
   Extending Moore’s Law via Integrating New Functions onto CMOS ITRS Emerging Technologies ? “ Another Dimension”
• 22.
  Why “Moore’s Law”Is Still a Fun Topic ! What makes us think that we can forecast more than ~5 years of future IC technology any better today ?!! A 1975 IC Technology Roadmap