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8051 Interrupt Programming By Dr. Min He.

8051 Interrupts Interrupt sources and priority levels Interrupt polling priority Interrupt vector table Registers used by interrupts Hardware steps in executing interrupts Software steps to enable an interrupt Handling external interrupts Interrupt Programming

Introducing Interrupts Interrupts and resets are among the most useful mechanisms that a computer system provides. Benefits provided by interrupts and resets: I/O operations are performed more efficiently Errors a r e handled more smoothly, and CPU utilization is improved. An interrupt is an event that requires the CPU to stop normal program execution and perform a special piece of code called Interrupt Service Routine (ISR) related to the event. External Interrupt: an external signal that is used to get the attention of the CPU Internal Interrupt: all microcontrollers has on-chip peripheral devices such as timers, A/D converters, serial peripheral interface, and so on. Signals asserted by these devices to get the attentions of the CPU are called internal interrupts. Software Interrupt: internal interrupt generated by software errors such as illegal opcodes, overflow, divided-by-zero, and underflow.

Interrupt Service Routine Similar to a procedure call, except that it can occur between any two instructions of the program is transparent to the running program (usually) is typically not explicitly requested by the program calls a routine at an address determined by the type of interrupt, not by the program atomically changes some processor mode bits in some special function register, such as TCON in 8051.

Common 8051 Interrupts There are 5 interrupt sources in common 8051. A unique number is assigned to each interrupt: Can set up two interrupt levels. Interrupt Name Number External Interrupt 0 INT0 0 Timer Interrupt 0 TF0 1 External Interrupt 1 INT1 2 Timer Interrupt 1 TF1 3 Serial Interrupt 1 R1+T1 4 Timer 2 TF2 5

Interrupt Polling Priority Upon Reset External Interrupt 0 Timer Interrupt 0 External Interrupt 1 Timer Interrupt 1 Serial Communication

Interrupt Vector Table Interrupt ISR ROM Address (Hex) Pin Flag Clearing Reset 0000 9 Auto External Hardware interrupt 0 (INT0) 0003 P3.2 Auto Timer 0 Interrupt (TF0) 000B Auto External Hardware interrupt 1 (INT1) 0013 P3.3 Auto Timer 1 Interrupt (TF1) 001B Auto Serial COM Interrupt (RI and TI) 0023 Programmer clears it.

Registers Used by Interrupts IE (Interrupt Enable) : to enable interrupts IP: set interrupt priority if needed TCON: if external interrupt is used, set control bit: edge-triggered vs. level-triggered. EA -- ET2 ES ET1 EX1 ET0 EX0 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 -- -- PT2 PS PT1 PX1 PT0 PX0

Hardware Steps in Executing an Interrupt Finish executing current instruction and save the address of the next one (PC) on the stack. Save status of all the interrupts internally (not on the stack). Jump to interrupt vector table Get the address of the ISR from interrupt vector table, and jump to execute the ISR. The microcontroller get PC from top of stack and returns to the place where it was interrupted upon executing the RETI instruction of the ISR.

Software Steps to Enable an Interrupt Set EA to enable interrupt EA=1; Set the corresponding interrupt bit in IE to enable a specific interrupt Example: ET0 = 1; enable timer 0 overflow interrupt EX0 = 1; enable external interrupt 0

External Interrupts --Level-triggered vs. Edge-triggered Level-triggered: Default mode upon reset of the 8051 A low-level signal triggers the interrupt. The low signal must be held low before the execution of ISR and must be removed before RETI. Edge-triggered: A high-to-low signal triggers the interrupt Need to set TCON.0(IT0)/TCON.2(IT1) TCON.1(IE0) and TCON.3(IE1) are set when an falling edge is detected and cleared by RETI.

Use TCON Register to Setup External Interrupts D7 D0 IE1/IE0 : external interrupt 1 & 0 edge flag. Set by CPU when the external interrupt edge is detected. Cleared by CPU when the interrupt is processed. IT1/IT0 : external interrupt 1 & 0 type control bit. Set/cleared by software to specify falling edge/low-level triggered interrupts. TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

Sampling of External Interrupts Level-triggered external interrupt: To ensure the activation of the hardware interrupt at the INTn pin, the duration of the low-level signal should be around 4 machine cycles, but not more. This is due to the fact that the level-triggered interrupt is not latched. Edge-triggered external interrupt: the external source must be held high for at least one machine cycle, and then held low for at least one machine cycle to ensure that the transition is seen by the microcontroller.

Interrupt-in-service Flag: IEx Used to keep track of edge-triggered external interrupt only The falling edge is latched by interrupt-in-service flag: IE0/IE1 is set by CPU when external interrupt is detected. No other external interrupt on the same pin will be responded when IE0/IE1 is raised. These flags are cleared when the ISRs are finished upon execution of instruction RETI.

Interrupt Programming In main: set interrupt mode Ex: Enable external interrupt 0, set it to be edge triggered: IT0=1; // set INT0 to be edge triggered EX0=1; // enable INT0 EA=1; // enable interrupt Write ISR function: bit my_flag; … . void chg_mode(void) interrupt 0 { my_flag=1; } Notice : No function prototype is needed for interrupt service routine. The interrupt keyword tells the compiler function chg_mode is an ISR. The number tell the compiler the interrupt source for the ISR.

Example: Furnace Controller Using interrupts, design an 8051 furnace controller that keeps a building at 20  C+/-1C  . Solution: The furnace ON/OFF solenoid is connected to P1.7 such that: P1.7 = 1 for furnace ON, P1.7=0 for furnace OFF. Temperature sensor is connected to external interrupt 0 and 1 to provide HOT and COLD signal.

Reading Assignment “ Embedded System Design with the C8051 ”, by Han-Way Huang. ISBN: 978-0495-47174-5, Publisher: Cengage Learning, Copyright: 2009. Chapter 6, sections 1, 2, 4.

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