Embedded System Practical Workshop using the ARM Processor

EMBEDDED SYSTEMS
PRACTICAL
WORKSHOP USING THE
ARM PROCESSOR
Prepared by: Mo’meN M. Ali
E-mail: momen.1993@live.com

References
• The Definitive Guide of ARM Cortex-M3 & M4
• Real-Time Interfacing to ARM Cortex-M Microcontrollers
• www.embedded-tips.blogspot.com
• www.ti.com/tm4c12x
• www.infocenter.arm.com
• https://courses.edx.org/courses/UTAustinX/UT.6.02x
EMBEDDED SYSTEMS WORKSHOP
Mo’meN M. Ali

All the codes are uploaded to this Git repo
https://github.com/Mo2meN-
Ali/TM4C12x/tree/master/Embedded%20Systems%20using%20ARM-
Cortex%20Workshop
Mo’meN M. Ali

Day 1
• Introduction to Embedded Systems
• Introduction to the ARM Cortex-M Processor & the TM4C12x
Microcontroller Family
• Parallel I/O Port
• Lab1: RGB Toggle
Mo’meN M. Ali

Day 2
• PLL & SysTick Timer Precise Time delays
• Lab2: Tuning Fork
• Universal asynchronous receiver transmitter [UART] interface
• Lab3: PC – Microcontroller communication over UART
• Lab4: PC Controls Microcontroller over the UART
• Serial Peripheral Interface
• Lab5: Nokia5110 LCD Interface
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Day 3
• Interrupt Synchronization
• Lab6: Matrix Keypad Interface
• Time Interfacing
• Lab7: Pulse Width Modulation
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Day 4
• DAC
• Lab8: Internal Temperature sensor
• ADC
• Lab9: Piano
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DAY1
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INTRODUCTIONTO
EMBEDDEDSYSTEMS
Mo’meN M. Ali

What is an Embedded System !
• Embedded systems is a branch of computer systems
• An Embedded System is a specific oriented programmed microcomputer
with a mechanical, chemical or electrical devices attached to it in order to
work as a system
• Embedded Systems have a dedicated HW & SW with a limited resources
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Embedded Systems Examples
• Telecom
• Smart Cards
• Missiles and satellites
• Computer Networking
• Digital Consumer Electronics
• Automotive
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Embedded Systems Concerns
• Power
• Code Size
• Execution Time
• Weight
• Cost
• Safety
• Security
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Embedded Systems
Architecture
• Power
• Code Size
• Execution Time
• Weight
• Cost
• Safety
• Security
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Embedded Systems Architecture
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How Embedded Systems Interacts
with the external environment !
• External Environment can interact with an embedded system through
sensors
• Embedded system can interact with an environment through actuator
• HCI embedded systems
• Embedded systems are reactive
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Exercise
• Form a groups
• Pick an embedded system and define its characteristics
MO’MEN M. ALI

INTRODUCTIONTOTHEARM
CORTEX-MPROCESSOR
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What is ARM !
• ARM refers to Advanced RISC Machines
• The ARM processor Dominates 80% of the embedded market
• ARM Founded in 1990
• Load-Store Architecture
• Full Descending Stack
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Mo’meN M. Ali
ARM Ecosystem

What is Cortex Processor !
• The new generation of the ARM Processor
• Consists of ARM CPU + System Peripherals
• Thumb-2 Technology
• Faster, more predictable interrupts and better debugging support
• On Chip Bus Interface based on ARM AMBA
• Nested Vector Interrupt Controller
• Unaligned memory access
Mo’meN M. Ali

Mo’meN M. Ali
Cortex Processors Roadmap

Series of Cortex Processor
• Cortex-A: General Purpose High end applications, System Clock > 1GHz
• Cortex-R: Real-Timer mid end applications, 600MHz > System Clock < 400MHz
• Cortex-M: Special Purpose low end applications, System Clock < 200MHz
Mo’meN M. Ali

Cortex-M Processors
• The First of the Cortex generation, started with Cortex-M3 in 2005
• Cortex-M3 & Cortex-M4 are 32-bit Architecture
• Thumb-2 Instruction set
• Three Stage pipeline design
• Harvard Architecture with unified memory space
• Cortex-M4 Supports: SIMD, MAC, Float point instructions (single precision),
Saturating arithmetic instructions
• Usage: Microcontrollers Cores
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Cortex-M CPU
• 32-bit RISC
• 16 registers
• 3 stages pipeline [fetch, decode,
execute]
• Branch prediction
• Load-store architecture
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Program Status Register
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• THE ALIASED ADDRESS FOR A
BIT IN THE ALIASED WORD
REGION WILL BE: OFFSET +
ADDR*32 + BIT*4
Cortex-M4
Memory Map
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Cortex-M System buses
• ICode bus Fetch opcode from ROM
• DCode bus Read constant data from ROM
• System bus Read/Write data from RAM or I/O, fetch
opcode from RAM
• PPB Read/Write data from internal peripherals
like the NVIC
• AHB Read/Write data from high-speed I/O and
parallel ports (M4 Only)
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CPU operating modes
• Privileged access level [use MSP as the stack pointer]
• Unprivileged access level [use PSP as the stack pointer]
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Power Modes
WFI
• Puts the CPU into sleep mode until an interrupt happen
WFE
• Put the CPU into sleep mode until an external event happen
LEEPDEEP
• CPU Enters the deep sleep mode
• Halts Peripherals, Processor Clock, flash memory and PLL
SLEEPONEXT
• Puts CPU into sleep mode after finishing an ISR
SEVONPEND
• An interrupt can generate an event even if disabled
• The interrupt status needs to be 0 before entering WFE
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• Flexible exception and interrupt
management
• Nested exception / interrupt support
• Vectored exception / interrupt entry
• Interrupt masking
• Supports 240 interrupt requests
• 8 to 256 interrupt priority levels
• Configurable by the manufacturers to the
needed number of interrupts
Nested Vectored Interrupt Controller
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System Tick Timer (SysTick)
• A 24-bit Down Counter
• Auto Acknowledge
• Auto reload
• Consists of 4 registers :
- Name Address
• SysTick Control and Status 0xE000E010
• SysTick Reload value 0xE000E014
• SysTick Current value 0xE000E018
• SysTick Calibration value [optional] 0xE000E01C
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Working sequence of the NVIC processor
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1. A peripheral asserts an interrupt request to
the processor
2. The processor suspends the currently
executing task
3. The processor executes an interrupt service
routine (ISR) to service the peripheral, and
optionally clear the interrupt request by
software if needed.
4. The processor resumes the previously
suspended task.

Cortex-M3/M4 Integration
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ARM Cortex-M Microcontroller
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• Program memory (e.g., Flash memory)
• Internal bus infrastructure
• Communication protocols e.G. UART, SPI, I2C
• Clock generator (including phase locked loop), reset
generator, and distribution network for these signals
• I/O pads
• ADC
• Timers
• Flash
• SRAM

Mo’meN M. Ali
Cortex-M Microcontroller Examples

How to write a quality embedded
code
• Only Change what you need not more.
• Use Bitwise AND to CLEAR bits
• Use Bitwise OR to SET bits
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Blind Cycle Synchronization
Blind cycle synchronization means to
wait for a fixed amount of time for an
I/O operation to be complete before
that fixed time has elapsed
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Busy Wait Synchronization
Busy wait synchronization means
check the I/O to be done by using a
software loop
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Interrupt Synchronization
Interrupt synchronization means that
the hardware will make a special sign
in a specific flag for each I/O when
the operation complete
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First in, First out Buffers [FIFOs]
Fifos are just a queues to store data
in hardware from I/O in the order of
the first data to be inserted is the
first data will be picked
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Pull Up Resistor
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Pull Down Resistor
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BREAK
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THETM4CMICROCONTROLLERS
FAMILY
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TM4C12x Architecture Overview
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TM4C12x Clock Sources
• Precision Internal Oscillator (PIOSC): 16MHz [+/- 1%:in room temperature],
[+/- 3%: Across temperature]
• Low Frequency Internal Oscillator (LFIOSC): 30KHz
• Hibernation Mode Clock Source (HMCS): 32.768KHz
• Main Oscillator (MOSC): An external Accurate clock source.
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EK-TM4C123GXL
Mo’meN M. Ali

Mo’meN M. Ali

EK-TM4C123G On-Board
• Tiva TM4C123GH6PMI Microcontroller
• USB micro-A and micro-B connector for USB device, host, and on-the-go (OTG) connectivity
• RGB user LED
• Two user switches
• Reset switch
• On-board ICDI
• Switch-selectable power sources:
- ICDI
- USB device
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NMI, !RST, OSC Pins
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In-Circuit Debug Interface (ICDI)
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Virtual COM port
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User Switches & RGB User LED
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Mo’meN M. Ali
EK-
TM4C123G
PCB
Design
Reference

PARALLEL I/O
PORTS
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GPIO General Programming steps
1. Enable the Peripheral’s Clock
2. Wait until the clock is stabilized (3-5 cycles)
3. Write 0x4C4F434B to the Lock register // PortF & PortC ONLY
4. Configure the Commit register // PortF & PortC ONLY
5. Configure the control register
6. Disable analog Functionality
7. Disable Alternate Function
8. Enable Digital Functionality
9. Configure the pin direction
10. Write/Read from the respective Pin/s
Mo’meN M. Ali

GPIOPortf_Init()
SYSCTL_RCGC2_R|= 0x00000020; // Enable the port’s clock
while ( 0 == (SYSCTL_PRGPIO_R & SYSCTL_PRGPIO_R5) ) { } // Wait until Port is clocked and working
GPIO_PORTF_LOCK_R = 0x4C4F434B; // 2) unlock GPIO Port F
GPIO_PORTF_CR_R = 0x1F; // allow changes to PF4-0
GPIO_PORTF_AMSEL_R&= 0x00; // Disable analog
GPIO_PORTF_AFSEL_R&= 0x00; // disable alternate function, Enable GPIO
GPIO_PORTF_DEN_R|= 0x1F; // Enable Digital on PF0-PF4
GPIO_PORTF_DIR_R|= 0x0E; // PF0, PF4 input (switches), PF1-PF3 output (RGB LED)
GPIO_PORTF_PUR_R|= 0x11; // Enable Pull up resistor for the 2 Buttons PF0, PF4
Mo’meN M. Ali

Project 1
Control the on-Board RGB-LED using the two Switches
https://github.com/Mo2meN-Ali/TM4C12x/tree/master/Embedded%20Systems%20using%20ARM-
Cortex%20Workshop/Day1/RGBToggle

DAY2
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PHASE
LOCKED LOOP
& SYSTICK
TIMER
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Phase Locked Loop Concept
• Phase locked loops are used to generate an output signal that in phase with the
input signal
• PLL’s mainly consists of phase detector and variable frequency oscillator
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Phase Locked Loop’s Block Diagram
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PLL Programming steps
1. Use RCC2 register because it has larger fields than the corresponding RCC field
2. Set the BYBASS
3. Specify the crystal oscillator value XTAL
4. Clear the PWRDN2 bit to activate the PLL
5. Configure and Enable the clock divider SYSDIV2 field to n, then system clock will be divided by n+1
6. Wait for the PLL to stabilize
7. Enable the PLL
Mo’meN M. Ali

PLL_Init()
SYSCTL_RCC2_R |= 0x80000000; // use RCC2 because it has more options
SYSCTL_RCC2_R |= 0x00000800; // set bypass for configuring the PLL
SYSCTL_RCC_R |= (SYSCTL_RCC_R & ~0x000007C0) + 0x00000540; // clear XTAL bits, set XTAL to 16 MHz
// clear PWRDN to enable PLL, select the main oscillator, set DIV400 for 400 MHz
SYSCTL_RCC2_R &= ~0x00000070;
SYSCTL_RCC2_R &= ~0x00002000;
SYSCTL_RCC2_R |= 0x40000000;
SYSCTL_RCC2_R = (SYSCTL_RCC2_R & ~0x1FC00000) | (4 << 22); // clear SYSDIV, then set it to 5 = (n + 1) for 80 MHz
while (0 == (SYSCTL_RIS_R & 0x00000040)) {}; // wait for PLL to stabilize
SYSCTL_RCC2_R &= ~0x00000800; // clear BYPASS to enable PLL
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SysTick Timer delay working cycle
• NVIC_ST_CTRL_R&= 0; // DISABLE SYSTICK WHILE CONFIGURING
• NVIC_ST_CURRENT_R= 0; // CLEAR THE CURRENT VALUE
• NVIC_ST_RELOAD_R= PERIOD - 1; // SETUP THE PERIOD COUNTS
• WHILE( 0 == (NVIC_ST_CTRL_R & 0X00010000) ) { } // WATCH THE FLAG
• NVIC_ST_CTRL_R|= 0X00000005; // ENABLE SYSTEM CLOCK, NO INTERRUPTS
// START SYSTICK TIMER
Mo’meN M. Ali

Tuning Fork
Cortex%20Workshop/Day2/Tuning_Fork
Project 2

UNIVERSAL
ASYNCHRONOUS
RECEIVER
TRANSMITTER
(UART)
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UART Usages
• It allows Microcontrollers to communicate with:
1. PC
2. Another microcontroller
3. Printers
4. Input sensors
5. LCDs
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UART clock and transfer rate
• Baud rate: the total number of bits transmitted per second
• Bandwidth: is the amount of useful information transmitted per second
• Start Condition: is a logic low pulse that must be transmitted at the beginning of each frame
• Stop condition: is a logic high pulse that must be transmitted in the end of each frame
• Baud rate= UART Clock Frequency / Clock Divider * Baud rate
• Bandwidth = (baud rate / 10) bytes/sec
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UART frame components
• A frame is the smallest complete unit of serial transmission
• A frame consists of 8 bit of data(LSB first), start condition and stop condition
• Start condition is a logic low that must be transmitted in the beginning of each frame
• Stop condition is a logic high that must be transmitted in the end of each frame
Mo’meN M. Ali

UART on the TM4C
• The TM4C has 8 UART modules
• UART Baud rate is 5Mbps in low speed, 10Mbps in high speed
• Separate 16x8 Tx FIFos, Rx FIFOs to reduce CPU interrupt service loading
• Programmable data size frame 5 to 8 bits
• FIFO based interrupt
• uDMA on UART
• BRD = BRDI + BRDF = UART Clock Frequency / Clock Divider * Baud rate
• Clock Divider is 16 in low speed mode, 8 in high speed mode
Mo’meN M. Ali

UART Programming Steps
1. Enable the Clock to the respective Port
2. Enable the Clock to the respective UART
3. Configure the two pins that will be used as Tx and Rx.
4. Disable the UART before configuring
5. Chose low speed mode or high speed mode
6. Set the integer baud rate register
7. Set the fractional baud rate register
8. Configure the UART data packet, Enable/Disable the FIFO
9. If FIFO Enabled, set the transmission/reception trigger condition
10. Enable the respective UART
Mo’meN M. Ali

UARTx_Init()
SYSCTL_RCGCGPIO_R|= SYSCTL_RCGCGPIO_R0;
SYSCTL_RCGCUART_R|= SYSCTL_RCGCUART_R0;
GPIO_PORTA_AMSEL_R&= ~0x03;
GPIO_PORTA_PCTL_R= (GPIO_PORTA_PCTL_R & ~0x000000FF) | 0x00000011;
GPIO_PORTA_AFSEL_R|= 0x03;
GPIO_PORTA_DEN_R|= 0x03;
UART0_CTL_R&= ~UART_CTL_UARTEN;
UART0_CTL_R&= ~UART_CTL_HSE; // low speed disabled, divide clock by 16
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UARTx_Init Continued
UART0_IBRD_R= 43; // Baud Rate = 115200
UART0_FBRD_R= 26;
UART0_LCRH_R|= UART_LCRH_WLEN_8 | UART_LCRH_FEN; // 8 bit word length, FIFOs Enabled, one stop bit
// no parity bits
UART0_IFLS_R|= UART_IFLS_TX1_8 | UART_IFLS_RX4_8; // trigger Transmit when 1/8 of Tx FIFO is ready
// trigger receive when 1/4 or less of Rx FIFO is empty
UART0_CC_R&= ~0xF; // Alternate Clock source, as define by the ALTCLKCFG register
UART0_CTL_R|= UART_CTL_UARTEN; // Enable UART0
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UART Transmitting Functions
• UARTx_TxChar();
• UARTx_TxString();
• UARTx_TxUNum();
• UARTx_NewLine();
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UARTx_TxChar()
• First we check the FIFO transmission flag to make sure that the UART FIFO register is not
full and has a space if it is not, we must wait for it to have at least 1-byte free using busy-
wait synchronization technique
• Puts the char into the data register of the respective UART which must be in ASCII
format
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UARTx_TxString()
• Every string in C is null terminated, so, we transmit each character till we reach the null
character which have to the last character
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UARTx_TxUNum()
• To transmit a number through UART we must use a technique called successive
refinement, that means we break the number into digits bit by bit which is a recursive
technique.
• Then we transmit each digit as a frame.
Mo’meN M. Ali

UARTx_NewLine()
• CR is an ASCII character called Carriage Return which moves the cursor to the beginning
of the line without advances to the next line
• LF is an ASCII character called Line Feed which moves the cursor to the new line
without moving it to the beginning of the line
• By using both of those characters we have ‘n’ w which advances to the beginning of
the next line of text
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UART Reception Functions
• UARTx_RxChar();
• UARTx_GetOneChar();
• UARTx_RxString();
• UARTx_RxUNum();
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UARTx_RxChar()
• First we check the FIFO reception flag to make sure that the UART FIFO register has
received 1 character at least, if not we must wait for it to receive a character using busy-
wait synchronization technique
• Pulls the char from the data register of the respective UART which will be in ASCII format
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UARTx_GetOnChar()
• First we check the FIFO reception flag to see if it is not empty, then we pick the bottom
character which is the oldest one, then we return
• If the FIFO is empty we return 0, signaling it is empty
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UARTx_RxString()
• We read each character into the string till the user press ENTER, signaling the end of the
string.
• we echo each character to the user
• We take the array size, so we don’t overflow also that’s how we can keep tracking on
each character in the string which allows us to delete character If it is wrongly pressed
• In the end we null terminating the characters to form a C string
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UARTx_RxUNum()
• Receives the number as a stream of ASCII characters until ENTER is pressed
• Checks each ASCII character that it contains a valid digits between 0-9, then break it into
2 digits then convert it to a real digit
• Echo it to the user
• Gather each digit to generate a full mathematical number then return it
Mo’meN M. Ali

PC – Microcontroller communication over UART
Cortex%20Workshop/Day2/PC_uC_Communication
Project 3

PC Controls Microcontroller over UART
Cortex%20Workshop/Day2/PC_Controls_uC_over_UART
Project 4

SERIAL
PERIPHERAL
INTERFACE
(SPI)
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Serial Peripheral Interface
• Full Duplex Protocol
• SPI Allows MCUs to communicate synchronously with Peripheral devices or other MCUs
• SPI can Operate as a master or as a slave
• Only the master initiates all the data communication
• The channel can have one master and one slave, or it can have one master and multiple
slaves
• With multiple slaves, the configuration can be:
• Star (centralized master connected to each slave)
• Ring (each node has one receiver and one transmitter, where the nodes are connected in a circle)
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Network Topology
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SPI VS UART
UART
• A asynchronous protocol which means two devices operates at the same
frequency but have two separate clocks
• The clock signal is not included in the interface cable between devices
• Two UART devices can communicate as long as the two clocks have frequencies
within +/-5% of each other
SPI
• is synchronous protocol which means the two devices are clocked from the same
clock (which is the master clock)
• The clock signal is included in the interface cable between devices
Mo’meN M. Ali

SPI Protocol I/O Lines
The SPI protocol includes four I/O Lines:
• Chip/Slave select CS, SS: is an optional negative logic control signal from the
master to slave signifying transmission
• Master out slave in MOSI: is the data line driven by the master and received by
the slave
• Master in slave out MISO: is the data line driven by the slave and received by the
master
• Serial Clock SCK: is a 50% duty cycle clock generated by the master
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Synchronous serial peripheral (SSI)
on the TM4C
The TM4C has 4 SSI modules
SSI Clock is SystemClock / 2 in master mode, SystemClock / 16 in slave mode
Separate 16x8 Tx FIFos, Rx FIFOs to reduce CPU interrupt service loading
Programmable data size frame 4 to 16 bits
FIFO based interrupt, End-of-transmission interrupt
uDMA on SSI
Fssi = Fbus / (CPSDVSR * (1 + SCR))
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Common control features for the
SSI module
Badu rate control register, used to select the transmission rate
Data size 4 to 16 bits, set 4-bit DSS field equal to (size – 1)
Mode bits in the control register to select
• Master versus slave
• Freescale mode with clock parity and clock phase
• TI Synchronous Serial mode
• Microwire mode
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Common status bits for the SSI
module
BSY, SSI is currently transmitting and/or receiving a frame or the transmit FIFO is not empty
RFF, SSI receive FIFO is full
RNE, SSI receive FIFO is not empty
TNF, SSI transmit FIFO is not full
TFE, SSI transmit FIFO is empty
Mo’meN M. Ali

Common control features for the
SSI module
Badu rate control register, used to select the transmission rate
Data size 4 to 16 bits, set 4-bit DSS field equal to size – 1
Mode bits in the control register to select
• Master versus slave
• Freescale mode with clock parity and clock phase
• TI Synchronous Serial mode
• Microwire mode
Mo’meN M. Ali

SSI Transmission Details
• The key to proper transmission is to select one edge of the clock to transmit and the
other edge to latch the data in the receiver
• In order for the communication to occur without error, the data available from the
device that is driving the data line must overlap (start before and end after) the data
required by the other device that is receiving the data.
• It is this overlap that will determine the maximum frequency at which SSI can occur
• Setup time is the time before the clock edge the input data must be valid
• Hold time is the time after a clock edge the data must continue to be valid
• The SPI transmits data at the same time as it receives input
• The data is transmitted MSB first
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Freescale SPI modes
• The SPI changes its output on the opposite edge of the clock as it uses to shift data in
• There are three modes control bits that affect the transmission protocol (MS, SPO, SPH)
• MS = 0, master mode and the TM4C will generate the clock on the SCKL, data output on
SSITx Pin and data input on SSIRx pin.
• SPO is the clock control polarity bit, it specifies the logic level of the clock when data is
not being transferred
• SPH affects the timing of the first bit transferred and received
• if SPH = 0, the device will shift data in on 1st, 3rd, 5th, 7th, … clock edge
• If SPH= 1, the device will shift data in on 2nd, 4th, 6th, 8th, …. Clock edge
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Nokia 5110 LCD
• Graphic display LCD
• 4032 Pixels
• 48 row, 84 column
• Logic supply voltage range VDD to VSS: 2.7 to 3.3 V
• 4 MHz Max baud rate
• Freescale SPI mode
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Nokia 5110 Pin Assignment
// Red SparkFun Nokia 5110 (LCD-10168)
// Signal (Nokia 5110) LaunchPad pin
// Reset (RST, pin 1) connected to PA7
// SSI0Fss (CE, pin 2) connected to PA3
// Data/Command (DC, pin 3) connected to PA6
// SSI0Tx (Din, pin 4) connected to PA5
// SSI0Clk (Clk, pin 5) connected to PA2
// 3.3V (Vcc, pin 6) power
// back light (BL, pin 7) ground
// Ground (Gnd, pin 8) not connected
Mo’meN M. Ali

Nokia 5110 Initialization ritual
1. First, we need to initialize the SSI Port (4MHz Max baudrate, SPI=SPH= 0)
2. Every LCD needs to differentiate between command signal and data signal and we
control that by manipulating the data/command DC bit
3. After reset: we must set the LCD into the Extended instruction set mode (H= 1 )Power
down mode bit is set (PD= 1) addressing mode are horizontal by default (bit V= 0)
Address counters are 0 on X-axis and 0 in Y-axis
4. we must Apply a restart pulse after reset (ACTIVE LOW)
5. Chose the normal instruction set (H= 0), clear the Power down bit (PD= 0), set the
Addressing mode (V bit) and the instruction mode (H bit), set the temperature
coefficient, bias voltage
6. Clear the display (RAM Contents are undefined upon reset which may cause glitches
on the display display )
Mo’meN M. Ali

Init_SSI()
SYSCTL_RCGC2_R|= SYSCTL_RCGC2_GPIOA;
SYSCTL_RCGC1_R|= SYSCTL_RCGC1_SSI0; // Enable clock for SSI0
GPIO_PORTA_AMSEL_R&= 0x00;
GPIO_PORTA_AFSEL_R|= 0x2C; // PA2-PA5 SSI
GPIO_PORTA_PCTL_R= (GPIO_PORTA_PCTL_R & ~0x00FFFF00) + 0x00222200;
GPIO_PORTA_DEN_R|= 0xEC;
GPIO_PORTA_DIR_R= (GPIO_PORTA_DIR_R & ~0x30) + 0xE0; // PA6, PA7 output, PA4
//receive, PA5 Transmit
SSI0_CR1_R&= ~0x02; // Disable SSI during configuration
SSI0_CR1_R&= 0; // Master mode
SSI0_CC_R&= 0; // SSICLK source is the SYSCLCK
SSI0_CPSR_R= 2; // CPSDVSR = 2
SSI0_CR0_R= 0x0900; // SCR = 9 for 4 MHz SSI Baud Rate
SSI0_CR0_R|= 0x0007; // 8-bit data size
SSI0_CR0_R&= ~0x00F0; // Freescale SPI, SPO = SPH = 0
SSI0_CR1_R|= 0x02; // Enable the SSI
Mo’meN M. Ali

Nokia5110_Init()
unsigned long delay;
Init_SSI();
RES= 0; // reset LCD to a known state
for(delay= 10; 0 != delay; --delay) {}; // about 100ns delay (Minimum)
RES= 0x80; // negative logic (Active low)
Nokia5110_Write(command, 0x21); // chip active PD = 0, V = 0 (horizontal addressing mode), H
// = 1 (extended instruction set)
Nokia5110_Write(command, 0xB1); // 3.3 Volt red SparkFun
Nokia5110_Write(command, 0x04); // set temp Coefficient
Nokia5110_Write(command, 0x14); // set 1:48 Bias
Nokia5110_Write(command, 0x20); // we must send 0x20 before change the display control
mode, H= 0 (normal instruction set)
Nokia5110_Write(command, 0x0C); // Normal Mode
Nokia5110_Clear();
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Nokia5110_Write()
• This function is the transmission function which transmits both data and commands to
the LCD through the SSI
• It take the information to be transmitted (one byte at a time) and the type of this
information (data/command)
• This function is the spinal column of all writes on the LCD
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Nokia5110_SetCursor()
• This function sets the address counter of the LCD which decides the place to write on
the display
• It takes the new coordinates of both the X & Y axis (Row and column)
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Nokia5110_PrintChar()
• This function Prints a single character on the Display by filling the right pixels with 1s
column by column (or 0s if we are in the reverse display mode)
• It leaves a blank column after and before each character, so, characters does not overlap
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Nokia5110_PrintNum()
• This function is designed to print numbers on the display it uses a mode macro to
decided if the number is positive or negative which the user must specify
• Since arithmetic calculations on both positive and negative numbers are the same so,
we use a single unsigned variable to print both with maintaining the –ve sign in negative
mode
• In this way we can get the advantage of longer values the unsigned variables are offering
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Nokia5110 LCD Interface
Cortex%20Workshop/Day2/Nokia5110_SSI
Project 5

DAY3
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INTERRUPT
SYNCHRONIZA
TION
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What is Interrupts & why it is useful
• Interrupts is an Automatic transfer of software execution in response to a hardware
event asynchronously
• It is a hardware trigger, software Action
• It is the way for computers to do multiple tasks simultaneously
• Interrupts can be Enabled/Disabled
• When interrupt happen the execution path of the software changes which called
Context Switch
• The new execution path is called Interrupt service routine(ISR) or background thread
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Interrupts from Programming
Perspective
1. Initialization
2. ISR
3. Inter-Thread Communication
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Thread
• A thread is a software execution path which means separate registers & stack from the
foreground thread
• Threads share access to I/O, global variables and resources
• A Thread is created by the hardware interrupt request and killed when the ISR returns
from the interrupt
• Threads working towards a common goal
• Multithreading is a collection of threads working together in order to perform an
overall task.
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Process
• A Process is also a software execution path
• Processes have separate global variables, system resource and does not share I/O
• Process does not always work towards a common goal
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Thread / Processes

Interrupts Priority
• Each ISR has its own Priority which is a number in a specific register that decides if two Interrupts
happened at the same which will be executed first
• The smaller the number the higher the priority (eg., priority 0 is higher than priority 1)
• A higher priority interrupt can always interrupts lower priority interrupts and not the vice versa
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Difference between Interrupt Enable
& Interrupt Masking
• There is a difference between Disable interrupt or prevent context switch
• Interrupts can be enabled but we can prevent interrupts from reaching the processor
which will disable the context switching (we will have to use Busy-Wait synchronization
in this case to watch the flag)
• There is a bit controls this behavior for each interrupt which means we can allow some
and prevent some
• PRIMASK register is used to mask disable all interrupt except for the NMI
• BASEPRI register is used to set the lowest level of priorities to be allowed and prevent
others (eg,. If BASEPRI = 3, then any ISR with the priority 3 or higher can interrupt the
foreground thread others can not)
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The Processor accepts interrupt if
the following conditions are met
• The processor is working not halted or in reset state
• The exceptions are enabled (with special cases for NMI and HardFault exception which
are always Enabled)
• The exception has a higher priority than the current working thread priority level
• The exception is not blocked by an exception masking register (e.g,. PRIMASK)
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Context Switch for Exception
Entrance (no floating point)
• Current Instruction is finished
• Eight register is pushed on the stack (R0, R1, R2, R3, R12, LR, PC ,PSR with R0 on the top)
• LR is set to 0xFFFFFFF9 (bits[31:8]: always 1’s, bits[7:0]: specifying the type of the return)
• IPSR is set to the IRQ number
• PC is loaded with the exception starting address
• Interrupt Service routines are treated as normal C functions on the Cortex-M Processor
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Exception exit (EXC_RETURN)

ARM Architecture Procedure Call
Standard (AAPCS)
• R0-R3, R12, LR, and PSR are called caller-saved registers
• The caller function need to make sure that it does not save values in this registers before
the call
• R4-R11 are called callee-saved registers
• The callee function needs to make sure that the content of this registers are unaltered
during the call
• Return values are saved in R0 and R1 respectively
• Double-Word Stack Alignment The Stack Pointer value should be Double-word aligned
(The bit 9 of the stacked xPSR is used to indicate if the value of the stack pointer has been
adjusted) at function entry or exit boundary (This step is not a must but rather
programmable)
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Double Work Stack Alignment –
xPSR Bit 9 Indicator

NVIC on the Cortex-M Processor
• Interrupts on the Cortex-M are controlled by the Nested Vectored Interrupt Controller
Processor
• Each exception has an associated 32-bit vector that points to the memory location where
the ISR that handles the exception is located
• Vector Table are stored in ROM, 0x0000.0000 has the initial stack pointer, and location
0x0000.0004 contains the initial program counter, which is also called the reset vector (this
function points to a function called reset handler which is the first thing executes after
reset which is calling the main() )
• There are up to 240 possible interrupt sources and their 32-bit vectors are listed in order
starting with location 0x0000.0008
• Startup.s is the file which contains the reset vector function and the vector table
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TM4C NVIC Register

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Interthread communication

Semaphore
• Binary semaphores are shared flags which used as a signal for some operation to be
ready when set
• Counting semaphores are a shared counter representing the number of objects has
been reached
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Mailbox
Mailboxes are binary
semaphores + data variable
which used to carry the
information

Edge-Trigger Interrupt general programming steps
1. Configure the pin as regular input pin
2. Clear the interrupt sense IS register for Edge triggering mode
3. Write to the interrupt both Edges IBE register (Set means interrupt on both edges)
4. Write to the Interrupt event IEV register (if IBE is cleared this register is used to
decide interrupt on which Edge)
5. if you willing to use busy-wait synchronization Clear Interrupt Mask Enable IME register
(default state is set)
6. Enable Interrupts on the Peripheral
7. Set the interrupt corresponding priority bit field in NVIC
8. Enable the corresponding Interrupt bit in the NVIC
9. Enable general interrupt on the Cortex-M Processor (set the I bit)
-most interrupts needs to be Acknowledged when it occurs which is writing 1 to the
corresponding bit in the interrupt clear register ICR every time the interrupt occurs (except for
SysTick)
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GPIOPortFEdgeTriggerSw_Init()
SYSCTL_RCGC2_R|= SYSCTL_RCGC2_GPIOF;
while ( 0 == (SYSCTL_PRGPIO_R & SYSCTL_PRGPIO_R5) ) { }
GPIO_PORTF_LOCK_R= 0x4C4F434B; // unlock GPIOF
GPIO_PORTF_CR_R|= 0x1F; // Enable for PF0 & PF4
GPIO_PORTF_PCTL_R&= ~0x000FFFFF; // will use digital
GPIO_PORTF_AMSEL_R&= ~0x17; // no analog
GPIO_PORTF_AFSEL_R&= ~0x17; // no Alternate Function
GPIO_PORTF_DEN_R|= 0x17; // 2 switches, RGB LED
GPIO_PORTF_PUR_R|= 0x11; // pull-up the 2 switches (negative logic)
GPIO_PORTF_DIR_R|= ~0x11; // input switches, output RGB LEDGPIO_PORTF_IS_R&= ~0x11; // Edge-trigger Interrupt
GPIO_PORTF_IBE_R&= ~0x11; // not both-edges
GPIO_PORTF_IEV_R&= ~0x11; // falling edges of PF0 & PF4
GPIO_PORTF_ICR_R= 0x11; // clear the interrupt flags before starting
GPIO_PORTF_IM_R= 0x11; // Enable external interrupts on PF0, PF4
NVIC_PRI7_R= (NVIC_PRI7_R & 0xFF0FFFFF) | 0x00800000; // setup PortF interrupt on NVIC Priority 4
NVIC_EN0_R|= 0x40000000; // EnablePortF interrupt on NVIC, PortF IRQ number is 30 so we set bit 30 in the NVIC Enable register
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Periodic Interrupts
• Periodic Timers is one of the most important techniques in system/embedded Programming
• Periodic Timers creates Periodic InterruptsIn periodic timer mode we configure the timer to run
continuously until it reaches the end of counting then it sets the interrupt flag and rolls over
automatically
• When the timer counts from 1 to 0 it sets the interrupt trigger flag
• On the next count, the timer is reloaded and starts over
• Timer Period = (bus period) * (delay period + 1) or (Freqbus / FreqTask)
• Another application of periodic interrupts is called intermittent polling or periodic polling
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Periodic Polling
• Periodic polling is similar to busy-wait synchronization except it is working on a regular basis not
continuously
• Periodic polling allows the system to serve multiple tasks virtually at the same time
• If the polling period is Δt, then on average the interface latency will be 0.5Δt, and the worst case
latency will be Δt
• This method frees the main from the I/O tasks
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When to use Periodic Polling !?
• The I/O hardware cannot generate interrupts directly
• We wish to perform the I/O functions in background
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Periodic Interrupts using SysTick
Activation steps
1. Disable SysTick while configuring
2. Any write to the current register clears it
3. Load the Period into the NVIC_ST_RELOAD_R
4. Set the SysTick Handler priority in NVIC_PRI3_R
5. Set System Clock Source as SysTick Clock source
6. Interrupts Enabled
7. Enable/Start SysTick Timer
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Periodic Interrupts using SysTick C
Code
NVIC_ST_CTRL_R &= 0; // Disable systick while configuring
NVIC_ST_CURRENT_R = 0; // any write to current clears it
NVIC_ST_RELOAD_R = Period; // Timer Period
NVIC_PRI3_R = 0; // priority 0 (Highest Priority)
NVIC_ST_CTRL_R |= 0x7; // Enable SysTick, SystemClock is the clock source, Interrupts Enabled
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Mo’meN M. Ali
Matrix KeyPad

Matrix KeyPad Interface
• The main Problems with KeyPad interface is:
• Button bouncing
• Two Keys rollover
• We will be using Periodic Polling technique because it affords a simple solution to both
problems :
• The time between key strokes will be in the order of 20ms
• The time the maximum bounce time will be 10ms
• So we will poll at the rate of 18ms
• Average latency will be 9ms, worst case latency will be 18ms
• We maintain rollover by saving the last key press into a static variable
• Never printing the present key but rather the last key (This is also enhancing the
bouncing prevention)
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Matrix KeyPad Button Search Algorithm
• The Main concept is to differentiate between rows and columns by setting one of them
to output and the other to input
• Set the rows to a different output than the columns, e.g., Rows= 0x0, Columns= 0xF
• Every short period (which will be faster than a human fingers) the MCU connects each
row with all columns and checks if there is a change (A key press), until we catch the
column with a change (Column != 0xF)
• After, knowing the row we search the bit changed which will be the exact column
• Now we have key[row][col] the exact pressed key
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MatrixKeyPad_Init()
SYSCTL_RCGC2_R|= SYSCTL_RCGC2_GPIOB;
// columns (RB0-RB3), rows (RB4-RB7)
GPIO_PORTB_CR_R= 0x0F; // commit to open I2C0
GPIO_PORTB_PUR_R= 0x0F; // pull-up on the input pins (rows)
GPIO_PORTB_AMSEL_R&= 0x00; // no analog
GPIO_PORTB_AFSEL_R&= 0x00; // no alternate function
GPIO_PORTB_PCTL_R&= 0x00000000;
GPIO_PORTB_DEN_R|= 0xFF;
GPIO_PORTB_DIR_R|= 0xF0; // RB0-RB3 cols(output), RB4-RB7 rows (input)
GPIO_PORTB_DATA_R= 0x0F; // rows default output is high
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Matrix KeyPad4x4
Cortex%20Workshop/Day3/MatrixKeyPad4x4
Project 6

TIME
INTERFACING
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TM4C123 General Purpose Timer
modules
• Six 16- /32-bit programmable GPTM Blocks
• Six 32- /64-bit programmable GPTM Blocks
• 16-bit general purpose timerxA or timerxB with an 8-bit prescaler
• 32-bit RTC using an external 32.768-KHz Clock Source
• Count up or down
• Daisy chaining of timer modules to allow single timer to initiate multiple timing events
• Timer synchronization allows selected timers to start counting on the same clock cycle
• Analog-to-digital event trigger
• uDMA
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GPTM vs SysTick
• General Purpose Timers works in many different modes and has a lot of configuration
dislike SysTick Timer which only work as a count-down timer
• General Purpose Timers Interrupts differs from SysTick in 2 ways:
• It needs to be acknowledge by software
• Interrupts needs to be activated in the NVIC Processor by the software
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GPTM Working modes
• One shot
• Periodic (Output compare)
• Pulse Width Modulation PWM
• Edge Count (input capture)
• Edge Time (input capture)
• Real Time Clock RTC
• We select the timer working mode by configuring the TIMERx_CFG_R & TIMERx_TxMR_R
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GPTM Periodic mode Activation steps
without interrupts
1. Enable the GPTM clock from the RCGCTIMER register
2. Ensure the Timer is disabled before making any changes (clear TAEN field)
3. Select 16- /32-bit mode timer (write 0x4 to TIMER0_CFG_R for 16-bit mode or 0x00
for 32-bit mode)
4. Write 0x2 to TAMR
5. Load the period to the TIMER0_TAILR_R with the [ (bus period) * (prescaler + 1) *
(delay period + 1) ]
6. Write 1 to CATOCINT of TIMER0_ICR_R to clear the time–out flag
7. Set the TAEN bit to start the timer and start counting
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GPTM Periodic mode Activation steps
with interrupts
1. Enable the GPTM clock from the RCGCTIMER register
2. Ensure the Timer is disabled before making any changes (clear TAEN field)
3. Select 16- /32-bit mode timer (write 0x4 to TIMER0_CFG_R for 16-bit mode or 0x00
for 32-bit mode)
4. Write 0x2 to TAMR
5. Load the period to the TIMER0_TAILR_R with the [ (bus period) * (prescaler + 1) *
(delay period + 1) ]
6. Write 1 to CATOCINT of TIMER0_ICR_R to clear the time–out flag
7. Set TATOIEN of TIMER0_IMR_R to mask the Interrupt
8. Set the priority in the corresponding NVIC Priority register
9. Set the corresponding NVIC Enable Interrupt register
10. Set the TAEN bit to start the timer and start counting
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Precision, Resolution, range and
Accuracy
• Precision is the number of separate and distinguishable values
• Resolution is the smallest change that can be detected
• Range is the minimum and maximum values that can reliably be measured
• Accuracy is the difference between actual and practical values ((Actual – ideal) / ideal)
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Pulse Width modulation
• Pulse width modulation is generating a wave with constant frequency and variable duty
cycle
• Duty cycle is the high period of the wave
• Duty Cycle = High / (High + Low) = High / Period
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Pulse Width modulation using Timers
• The output wave period will be the timer period
• We change the duty cycle using the TIMER0_TxMATCHR_R
• We set Timer to periodic mode and PWM to keep generating Pulses
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TimerxPWM Activation steps
1. Enable Clock to the Port
2. Enable Clock to the Timer module
3. Disable analog on the pin
4. Enable alternate function on the pin
5. Write the special value into the control register (7 for timer configuration)
6. Enable digital on the pin
7. Disable timer module while configuring
8. Configure 16- /32-bit timer
9. configure the timer for periodic mode, PWM
10. Load the timer’s period which is the wave period
11. Configuring the duty cycle by loading the low period into the match register.
12. Enable the timer module
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Timer0APWM_Init()
SYSCTL_RCGC2_R|= SYSCTL_RCGC2_GPIOB; // PortB clock
SYSCTL_RCGCTIMER_R|= SYSCTL_RCGCTIMER_R0; // Timer0 clock
GPIO_PORTB_AMSEL_R&= ~0x40; // Disable Analog on PB6
GPIO_PORTB_AFSEL_R|= 0x40; // Enable Alternate function
GPIO_PORTB_PCTL_R= (GPIO_PORTB_PCTL_R & ~0x0F000000) | 0x07000000;
GPIO_PORTB_DEN_R|= 0x40; // Enable Digital
TIMER0_CTL_R&= ~TIMER_CTL_TAEN; // Disalbe Timer0A while configuring
TIMER0_CFG_R|= TIMER_CFG_16_BIT; // 16-Bit Mode
TIMER0_TAMR_R|= 0x0000000A; // Periodic, PWM Enabled
TIMER0_TAILR_R= Period - 1; // Square wave Period
TIMER0_TAMATCHR_R= Period - High - 1; // Duty Cycle, the match Register works as the low period of the pulse
TIMER0_CTL_R|= TIMER_CTL_TAEN; // Enable/Start Timer0A
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Pulse Width Modulation
Cortex%20Workshop/Day3/PWM%26EdgeTrigger%20Interrupts
Project 7

DAY4
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ANALOG-TO-
DIGITAL
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Analog To Digital
• An analog to digital converter (ADC) converts an analog signal into digital form
• An embedded system uses the ADC to collect information about the external world
(data acquisition system)
• The input signal is an analog voltage, and the output is a binary number
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Analog To Digital factors
• The ADC precision is the number of distinguishable ADC Inputs ((2^ADCbits ) - 1)
• The ADC range is the maximum and minimum ADC inputs (volts, amps)
• The ADC resolution or step size is the smallest distinguishable change in input that
causes the digital output to change by 1 (resolution = (ADC reference voltage /
precision))
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Analog To Digital Conversion
Techniques
• Successive approximation
• Sigma-delta
• Flash
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Successive Approximation ADC
• It is the most pervasive method for ADC conversion
• A n-bit successive approximation ADC is clocked n
times at each clock another bit is determined starting
with the MSB
• The speed of a successive approximation ADC relates
linearly with its precision in bits
• The DAC within is the same precision as the ADC
• The ADC frequency could be in order of mega sample
per second
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Successive Approximation ADC
conversion technique
• For each clock, the successive approximation
hardware issues a new guess on vd by setting the bit
under test to a 1
• If the vd now is higher than vin then the next bit is
cleared if vd is less than vin then the next bit is set
and so on until we determine all the remaining bits
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Sigma delta ADC conversion
• It is a cost effective approach, with time average-sense (speed)
• Its digital signal processing runs at faster frequency than the overall ADC system
called oversampling
• It can use a much lower precision DAC (most of the time it only needs 1-bit DAC)
• The ADC frequency could be in order of kilo sample per second
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Sigma delta ADC conversion technique
• The delta part is a subtractor (V1 = vo - vi)
• The sigma part is an analog integration
• If vo == vi, then V2 will be zero, the comparator tests V2 if positive then vo is
made smaller if negative then vo is made larger
• This dac-subtractor-integrator-comparator-digital loop is executed at a rate
much faster than the eventual digital output rate
• This method is mathematically called signal convolution
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Flash ADC
• It is the fastest ADC
conversion technique and
the most expensive as well
• It converts the analog input
voltage and produce the
binary output without
looping or convoluting
• The ADC frequency could be
in order of giga sample per
second
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Flash ADC conversion technique
• Flash ADC takes the vi and
the vref then outputs the
binary number nearly at
once
• If the ADC precision is n then
there will be 2^n
comparators with one
comparator signal works as
the control signal for the
encoder
• The output then is passed to
an as input encoder, the
output of the encoder is the
ADC output
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Flash ADC conversion technique
• The sample and hold is an analog latch holds the input constant during the
conversion
• Acquisition time is the time for the output to equal the input after the control
switched from hold to sample
• Droop rate is the output voltage slope when control equals hold (dvo/dt)
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Nyquist Theorem
• Nyquist Theorem states that if the signal is sampled with a frequency of fs, then the
digital samples only contain frequency components from 0 to ½ fs. Conversely, if the
analog signal does contain frequency components larger than ½ fs, then there will be an
aliasing error during the sampling process
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Aliasing
• Aliasing is when the digital signal appears to have a different
frequency than the original analog signal
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ADC on the TM4C123
• Two ADC modules with each one has four sample sequencers
• Successive approximation ADC
• 12 input channel
• 12-bit Precision
• Up to 1 Msps
• Single ended and differential-input configuration
• On-chip Temperature sensor
• uDMA
• Flexible trigger source:
• Controller (software)
• Timers
• Analog Comparators
• PWM
• GPIO
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ADC Timer trigger activation steps1. Initialize the timer module, Periodic mode, load the sampling time into the TIMERx_TAILR_R
2. We must set bit 5 of TIMERx_CTL_R which is the Timer x output trigger enable
3. Initialize the Port pins as input, analog, alternate function
4. Enable the ADC clock source
5. Set the ADC sampling rate (125Ksps, 256Ksps, 500Ksps, 1Msps)
6. Set the priority of each sample sequencer
7. Disable the sequencer to be used before configuring
8. Configure the trigger event for the required sample sequencer in the ADCx_EMUX_R
9. For each sample in the sample sequence, configure the corresponding input source (which sample sequencer
those samples belong) in the ADC0_SSMUXn_R
10. Configure the control bits for the required sample sequencer in the ADC0_SSCTLn_R, the sample interrupt
enable bit, the differential mode bit, the temperature sensor enable bit and the END bit (this bit decides which
sample is the last in the sampling sequence, failure to set any of this bit causes unpredictable behavior)
11. If interrupts to be used we set the corresponding bit in the ADCx_IM_R to enable interrupts on the ADC
12. We enable the required sample sequencer by writing 1 to the corresponding ASENx in the ADC0_ACTSS_R
13. Set the ADC interrupt priority in the NVIC
14. Enable interrupts in the NVIC
15. Enable global interrupts on the system by setting the PRIMASK register
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TemperatureSensor_Init()
// Port pins initialization C code
// Timer Initialization C code
ADC0_ACTSS_R&= ~0x00000008; // Disable SS3
ADC0_SSPRI_R= (ADC0_SSPRI_R & 0) | 0x0123; // SS3 priority 0 (higher)
ADC0_PP_R= (ADC0_PP_R & 0) | 0x00200000 | 0x00000010 | 0x00000001; // Resolution is 2, temperature sensor is on,
// 125k sample/sec
ADC0_EMUX_R|= 0x5000; // Timer is the trigger source
ADC0_SSCTL3_R= (ADC0_SSCTL3_R & 0) | ADC_SSCLT3_TS | ADC_SSCTL3_IM | ADC_SSCTL3_END; // EnableTemperature
// sensor, Interrupts and END0. No differential sampling mode
ADC0_SSMUX3_R= (ADC0_SSCTL3_R & 0x0) | 0x8; // AIN8 is the sample destination
ADC0_IM_R= (ADC0_IM_R & ~0x0000000F) | 0x00000008; // Promote SS2 interrupt to the controller
ADC0_ACTSS_R|= 0x00000008; // Enable SS3
ADC0_ISC_R= 0x00000001; // clear interrupt flag
NVIC_PRI4_R= (NVIC_PRI4_R & 0xFFFF00FF) | 0x00002000; // bits 13-15 for ADC0 sample sequencer 3
NVIC_EN0_R|= 1 << 17; // Enable interrupt 17 in NVIC
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Internal Temperature sensor
Cortex%20Workshop/Day4/Internal%20Temperature%20Sensor
Project 8

DIGITAL-TO-
ANALOG
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Digital To Analog
• An analog to digital converter (DAC) converts an Digital signal to analog
• Since most signals in the world exists as continuous signals so, embedded systems uses
the DAC to communicate with the external world
• The input signal is usually binary value (digital signal), and the output is an analog signal
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Digital To Analog factors
• The DAC precision is the number of values from which the amplitude of the digital
signal is selected ((2^DACbits ) - 1)
• The DAC range is the maximum minus the minimum value
• The DAC resolution is the smallest distinguishable change in output
• The DAC monotonicity is that if the input increased the output increase, if decreased
the output decrease ( sign(f(n+1) – f(n)) = sign(f(m+1) – f(m)), where n is the output &
m is the input )
• The DAC linearity is that the output increases or decreases by the same amount as the
input ( f(n+1) – f(n) = f(m+1) – f(m), where n is the output & m is the input )
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Digital To Analog Monotonicity
Sign(f(n+1) – f(n)) = sign(f(m+1) – f(m)),
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Digital To Analog linearity
F(n+1) – f(n) = f(m+1) – f(m),
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Binary Weighted DAC
• It is a resistor n-bit network to convert analog signal into digital signal
• We choose the resistors to be 2/1 start from the lower bit so Q0 is
twice as the resistance as Q1
• Example: 2-bit binary weighted DAC
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2-bit Binary Weighted DAC analysis
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Binary Weighted DAC Drawbacks
1. It can not be more than 8-bit DAC
2. The summing DACs includes the noise, errors, uncertainty in the digital power supply
3. It is difficult to avoid nonmonotonicity in this type of DACs
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R-2R Ladder DAC
• R-2R ladder DAC is another
n-bit resistor network to
transform the analog signals
into digital signal
• It has far less monotonicity
and linearity errors
• It can be constructed with 1
resistor value
• Example: 3-bit R-2R ladder
DAC
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R-2R Ladder DAC Analysis
• We will check the three basics states (1, 2, 4)
• If this cases are demonstrated, then the law of superposition guarantees the other five
will work
• When one of the digital input is true then Vref is connected to the R-2R ladder, and
when it is false, then the connection is grounded
• The current across the active switch is Io = (Vref / 3R), this current is divided by 2 at
each branch point. I.e., I1= (Io / 2), I2= (I1 / 2)
Mo’meN M. Ali

R-2R Ladder DAC Analysis
Mo’meN M. Ali

DAC Chips
• TLV5618: 12-bit, Dual output, SPI compatible
• MAX5353: 12-bit, Single output, SPI compatible
• DAC0808: 8-bit, Single output, Parallel input
Mo’meN M. Ali

DAC0808
• 8-bit R-2R ladder DAC chip
• +/- 0.19% error maximum
• Fast settling time: 150ns
• High speed multiplying input
slew rate: 8 ma/μs
Mo’meN M. Ali

DAC Waveform Generation
• The key of generation waveforms is Periodic Interrupts
• The Period or frequency of the interrupt will be determined by this equation (Fint = Fs /
N, where Fi is the interrupt Period, Fs is the frequency of the tune and N is the number
of points into the sine wave array)
• We put the waveform information in a large statically allocated global array
• Every interrupt we fetch a new value out of the data structure and output it to the DAC
Mo’meN M. Ali

Waveform output
• GPIO_PORTF_DATA_R^= 0x0A; // Blue LED, debugging
• DAC_Out(SineWave[Index]); // out the current value (point) of the sinewave
on the parallel port
• Index= (Index + 1) & 0x1F;
Mo’meN M. Ali

DAC_Init()
SYSCTL_RCGC2_R|= SYSCTL_RCGC2_GPIOB;
GPIO_PORTB_PCTL_R&= 0xFFFF0000;
GPIO_PORTB_AMSEL_R&= 0xF0;
GPIO_PORTB_AFSEL_R&= 0xF0;
GPIO_PORTB_DR8R_R|= 0x0F;
GPIO_PORTB_DIR_R|= 0x0F;
GPIO_PORTB_DEN_R|= 0x0F;
Mo’meN M. Ali

Tone frequency table
Fint = fs / N
Embedded systems workshop
Mo’men M. Ali

Piano
Cortex%20Workshop/Day4/Piano
Project 9

THANK YOUSEE YOU SOON
Mo’meN M. Ali

Embedded System Practical Workshop using the ARM Processor

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