Interrupts
• There are many situations the processor can perform other
tasks while waiting for input/ output device to become ready.
• This to happen. We arrange the input/ output device to alert
the processor when it becomes ready.
• This is done by each can send a special hardware signal called
an interrupt to the processor.
• The bus control line called interrupt-request line is dedicated
for this purpose.
• A routine executed in response to an interrupt request is
called the interrupt- service routine.
Interrupt
Interrupt
Interrupt request
• Assume an interrupt req arrives during execution of
instruction i.
• The processor first completes execution of instruction i by
load the address of the first instruction of the interrupt-
service routine.
• Assume this address is hardwired in the processor.
• After execution of interrupt service routine , the processor
has to come back to instruction i+1.
Contd.,
• Hence, when an interrupt occurs, the content of PC, which
currently point to the i+1, must be put into the temporary
storage.
• At return of interrupt service routine reloads the PC from
that temp storage location, causing execution to resume at
instruction i+1.
• In many processor , the return address is saved on the
processor stack. Alternatively, saved in temp register.
ACK
• As part of interrupt, the processor must inform the device
that its request has been recognized so that it may remove
its interrupt- req signal.
• It may accomplished by special signal on the bus.
• An interrupt- Acknowledge signal.
• An interrupt service routine is similar to that of a
subroutine, performs a function required by the program
from which it is called.
• The task of saving and restoring information can be done by
processor.
• Saving registers increases the delay b/w the time an
interrupt req is received and start of execution of the
interrupt-service routine. This delay is called interrupt
latency.
Interrupt Hardware
• An input/ output device requests an interrupt by activating a
bus line called interrupt-request.
• Several input/ output devices can request an interrupt.
• A single interrupt request line may used for this purpose.
• All devices are connected to the line via switches to ground.
Interrupt
• To request an interrupt, a device closes its associated
switch.
• If all interrupt-request signals INTR1 to INTRn are inactive,
that is, if all switches are open, the voltage on the interrupt
request line will equal to Vdd. This is an inactivate state of
the line.
• When a device requests an interrupt by closing its switch,
the voltage on the line drops to 0, causing the interrupt-
request signal INTR received by the processor to go to 1.
• If closing of one (or) more switches that cause the line
value to drop to 0, the value of logical OR of the request
from individual devices, that is
• INTR=INTR1+INTR2+INTR3..............
• Use the complement form of INTR to name of the interrupt
signal on the common line because this signal is active in
the low voltage state
1.Enabling and disabling interrupts
• A processor has the facility to enable and disable interrupts
as desired.
• When a device request the interrupt during the processor
service for another interrupt, the result cause the processor
enter into the infinite loop.
• This can be handled by the following 2 ways:
 The processor ignore the interrupt request line(INTR) until
the Interrupt Service Routine(ISR) is completed.
 This can be done by using interrupt-Disable as first
instruction and interrupt-Enable as the last instruction.
• The second option is processor automatically disable
interrupts before starting the execution of the ISR.
• The status register PS stored in the stack with PC value.
• The processor set this register bit 1 when the interrupt
accept and when a return instruction is executed, the
contents of the PS are cleared (0)and stored in the stack
again.
2.Handling Multiple Devices
• When the number of devices initiating interrupts.
• For example, device X may request an interrupt while an
interrupt caused by device Y is being serviced.
• Hence all the device using the common interrupt line.
• Additional information require to identify the device that
activated the request.
• When the two devices activated the line at the same time,
we must break up the tie and chose one the device request
among two. Some scheme should be used by the processor.
2.1Polling scheme
• The device that raises the interrupt will set one of the bit
(IRQ) in status register to 1.
• The processor will poll the devices to find which raised an
interrupt first.
Disadvantage:
• Time spend in interrogating the IRQ bits of the devices that
may not be requesting any service.
2.2Vectored interrupts
• To reduce the time involved in the polling scheme, a device
requesting an interrupt may identify itself directly to the
processor.
• A device can send a special code to the processor over the
bus. The code is used to identify the device.
• If the interrupt produces a CALL to a predetermined
memory location, which is the starting address of ISR, then
that address is called vectored address and such interrupts
are called vectored interrupts.
3.Interrupt priority
• When a interrupt arrives from one (or) more devices
simultaneously, the processor has to decide which request
should be serviced first.
• The processor takes this decision with the help of interrupt
priorities.
• The processor accepts interrupt request having highest
priority.
• Each request assign a different priority level.
• The request received from the interrupt request line are sent
to a priority arbitration circuit in the processor.
• The request is accepted only if it has a higher priority level
than that currently assigned to the processor.
Interrupt
4.Controlling device request
• The processor allow only the input / output devices
requested(interrupt), that are being used by a given
program.
• Other devices should not be allowed to generate interrupt
requests even though they are ready to transfer the data.
• Hence, we need a mechanism in the interface circuits of
individual devices to control whether the device is allowed
to generate an interrupt request.
• Two mechanism for control request:
1. One is at the device end- interrupt enable bit in the control
register(IRQ).
2. Processor end- enable bit in the program status register(PS)
or priority structure determine whether a given interrupt
request will be accepted.
• System properties->View resource by type

More Related Content

PPT
Logic System Design KTU Chapter-4.ppt
PPTX
Mealy and moore machine
PPTX
flip flops
PPTX
Flip flop
PPT
Formatted input and output
PPTX
Unit -I Toc.pptx
PPTX
Instruction pipeline: Computer Architecture
PPTX
Longest Common Subsequence
Logic System Design KTU Chapter-4.ppt
Mealy and moore machine
flip flops
Flip flop
Formatted input and output
Unit -I Toc.pptx
Instruction pipeline: Computer Architecture
Longest Common Subsequence

What's hot (20)

PDF
Computer organiztion5
PPT
Addition and subtraction with signed magnitude data (mano
PPTX
Flip Flop & RS Latch
PPTX
Combinational Circuits & Sequential Circuits
PPTX
DLD Lecture No 18 Analysis and Design of Combinational Circuit.pptx
PPTX
Karatsuba algorithm for fast mltiplication
PPTX
Latches and flip flops
PPT
Randomized algorithms ver 1.0
PPTX
Regular expressions
PPTX
Round Robin Algorithm.pptx
PPT
Time complexity.ppt
PPTX
Intro to assembly language
PPTX
Job sequencing with Deadlines
PDF
Logic microoperations
PPTX
Latches and flip flops
PPTX
latches
PPTX
Combinational circuit
PPTX
Sequential Logic Circuit
PPT
Combinational circuits
PPTX
Pumping lemma
Computer organiztion5
Addition and subtraction with signed magnitude data (mano
Flip Flop & RS Latch
Combinational Circuits & Sequential Circuits
DLD Lecture No 18 Analysis and Design of Combinational Circuit.pptx
Karatsuba algorithm for fast mltiplication
Latches and flip flops
Randomized algorithms ver 1.0
Regular expressions
Round Robin Algorithm.pptx
Time complexity.ppt
Intro to assembly language
Job sequencing with Deadlines
Logic microoperations
Latches and flip flops
latches
Combinational circuit
Sequential Logic Circuit
Combinational circuits
Pumping lemma
Ad

Viewers also liked (20)

PDF
Introduction To Computer Bus - www.thestuffpoint.com
PDF
110 lr and slr parsing
PDF
Compiler Components and their Generators - Traditional Parsing Algorithms
PPT
Getting started into mySQL
PPTX
Ll1 exam structure
PPT
Mysql grand
PPT
interface
PPTX
Ll1 exam prep
PPT
Virtualization Concepts
PPT
Micro programmed control
DOCX
B tech cs-iii-guidelined for technical seminar
PPT
Io devies
PPTX
Lecture 09 syntax analysis 05
PPT
LL1 Ozymandias
PDF
LL Parsing
PPT
Networking devices(siddique)
PDF
Compiler Components and their Generators - LR Parsing
PPTX
LALR Parser Presentation ppt
DOCX
seminar report on multiple access control protocol submitted by munesh
Introduction To Computer Bus - www.thestuffpoint.com
110 lr and slr parsing
Compiler Components and their Generators - Traditional Parsing Algorithms
Getting started into mySQL
Ll1 exam structure
Mysql grand
interface
Ll1 exam prep
Virtualization Concepts
Micro programmed control
B tech cs-iii-guidelined for technical seminar
Io devies
Lecture 09 syntax analysis 05
LL1 Ozymandias
LL Parsing
Networking devices(siddique)
Compiler Components and their Generators - LR Parsing
LALR Parser Presentation ppt
seminar report on multiple access control protocol submitted by munesh
Ad

Similar to Interrupt (20)

PDF
bec306c Computer Architecture and Organization
PDF
Computer oganization input-output
PPTX
Module 5 Part 1-IO ORGANIZATION IMP.pptx
PPTX
Module4-Inputoutput Organization.pptxbygvug
PPTX
Computer Organization and Architecture_Unit 1_part b.pptx
PPT
IO organization.ppt
PDF
Module 4 IO organization- computer arc.pdf
PPT
Unit2 p1 io organization-97-2003
PPT
Computer Organization_Input_ UNIT -4.ppt
PPTX
chapter7-io organization.pptx
PPT
input and output organization in computer architecture
PPT
Unit 5 I/O organization
PPT
Microprocessor IO module and its different functions
PDF
A transfer from I/O device to memory requires the execution of several instru...
PPTX
priority interrupt computer organization
PPTX
420214730-15cs34-module-2-pptx.pptx
PPT
unit-5 ppt.ppt
DOC
Ca 2 note mano
PPTX
I/O Organization
PPT
Input Output Operations
bec306c Computer Architecture and Organization
Computer oganization input-output
Module 5 Part 1-IO ORGANIZATION IMP.pptx
Module4-Inputoutput Organization.pptxbygvug
Computer Organization and Architecture_Unit 1_part b.pptx
IO organization.ppt
Module 4 IO organization- computer arc.pdf
Unit2 p1 io organization-97-2003
Computer Organization_Input_ UNIT -4.ppt
chapter7-io organization.pptx
input and output organization in computer architecture
Unit 5 I/O organization
Microprocessor IO module and its different functions
A transfer from I/O device to memory requires the execution of several instru...
priority interrupt computer organization
420214730-15cs34-module-2-pptx.pptx
unit-5 ppt.ppt
Ca 2 note mano
I/O Organization
Input Output Operations

More from Siddique Ibrahim (20)

PPTX
List in Python
PPT
Python Control structures
PPTX
Python programming introduction
PPT
Data mining basic fundamentals
PPT
Basic networking
PPT
Osi model 7 Layers
PPT
pipelining
PPTX
Hardwired control
PPT
Interrupt
PPT
Stack & queue
PPT
Metadata in data warehouse
PPTX
Data extraction, transformation, and loading
PPT
Aggregate fact tables
PPT
PHP variables
PPT
Php hypertext pre-processor
PPT
Cryptography basices
PPT
Secondary storage devices
PPT
Internal memory
PPT
Interface
PPT
Error detection and correction
List in Python
Python Control structures
Python programming introduction
Data mining basic fundamentals
Basic networking
Osi model 7 Layers
pipelining
Hardwired control
Interrupt
Stack & queue
Metadata in data warehouse
Data extraction, transformation, and loading
Aggregate fact tables
PHP variables
Php hypertext pre-processor
Cryptography basices
Secondary storage devices
Internal memory
Interface
Error detection and correction

Recently uploaded (20)

PDF
Hybrid horned lizard optimization algorithm-aquila optimizer for DC motor
PDF
UiPath Agentic Automation session 1: RPA to Agents
PPT
Module 1.ppt Iot fundamentals and Architecture
PPTX
AI IN MARKETING- PRESENTED BY ANWAR KABIR 1st June 2025.pptx
PDF
Two-dimensional Klein-Gordon and Sine-Gordon numerical solutions based on dee...
PPTX
Microsoft Excel 365/2024 Beginner's training
PDF
TrustArc Webinar - Click, Consent, Trust: Winning the Privacy Game
PPTX
Final SEM Unit 1 for mit wpu at pune .pptx
PPTX
Configure Apache Mutual Authentication
PDF
A contest of sentiment analysis: k-nearest neighbor versus neural network
PDF
sustainability-14-14877-v2.pddhzftheheeeee
PDF
The influence of sentiment analysis in enhancing early warning system model f...
DOCX
search engine optimization ppt fir known well about this
PDF
Produktkatalog für HOBO Datenlogger, Wetterstationen, Sensoren, Software und ...
PPTX
Chapter 5: Probability Theory and Statistics
PDF
ENT215_Completing-a-large-scale-migration-and-modernization-with-AWS.pdf
PDF
CloudStack 4.21: First Look Webinar slides
PDF
Five Habits of High-Impact Board Members
PDF
Convolutional neural network based encoder-decoder for efficient real-time ob...
PDF
Getting started with AI Agents and Multi-Agent Systems
Hybrid horned lizard optimization algorithm-aquila optimizer for DC motor
UiPath Agentic Automation session 1: RPA to Agents
Module 1.ppt Iot fundamentals and Architecture
AI IN MARKETING- PRESENTED BY ANWAR KABIR 1st June 2025.pptx
Two-dimensional Klein-Gordon and Sine-Gordon numerical solutions based on dee...
Microsoft Excel 365/2024 Beginner's training
TrustArc Webinar - Click, Consent, Trust: Winning the Privacy Game
Final SEM Unit 1 for mit wpu at pune .pptx
Configure Apache Mutual Authentication
A contest of sentiment analysis: k-nearest neighbor versus neural network
sustainability-14-14877-v2.pddhzftheheeeee
The influence of sentiment analysis in enhancing early warning system model f...
search engine optimization ppt fir known well about this
Produktkatalog für HOBO Datenlogger, Wetterstationen, Sensoren, Software und ...
Chapter 5: Probability Theory and Statistics
ENT215_Completing-a-large-scale-migration-and-modernization-with-AWS.pdf
CloudStack 4.21: First Look Webinar slides
Five Habits of High-Impact Board Members
Convolutional neural network based encoder-decoder for efficient real-time ob...
Getting started with AI Agents and Multi-Agent Systems

Interrupt

  • 2. • There are many situations the processor can perform other tasks while waiting for input/ output device to become ready. • This to happen. We arrange the input/ output device to alert the processor when it becomes ready. • This is done by each can send a special hardware signal called an interrupt to the processor. • The bus control line called interrupt-request line is dedicated for this purpose.
  • 3. • A routine executed in response to an interrupt request is called the interrupt- service routine.
  • 6. Interrupt request • Assume an interrupt req arrives during execution of instruction i. • The processor first completes execution of instruction i by load the address of the first instruction of the interrupt- service routine. • Assume this address is hardwired in the processor. • After execution of interrupt service routine , the processor has to come back to instruction i+1.
  • 7. Contd., • Hence, when an interrupt occurs, the content of PC, which currently point to the i+1, must be put into the temporary storage. • At return of interrupt service routine reloads the PC from that temp storage location, causing execution to resume at instruction i+1. • In many processor , the return address is saved on the processor stack. Alternatively, saved in temp register.
  • 8. ACK • As part of interrupt, the processor must inform the device that its request has been recognized so that it may remove its interrupt- req signal. • It may accomplished by special signal on the bus. • An interrupt- Acknowledge signal.
  • 9. • An interrupt service routine is similar to that of a subroutine, performs a function required by the program from which it is called. • The task of saving and restoring information can be done by processor. • Saving registers increases the delay b/w the time an interrupt req is received and start of execution of the interrupt-service routine. This delay is called interrupt latency.
  • 10. Interrupt Hardware • An input/ output device requests an interrupt by activating a bus line called interrupt-request. • Several input/ output devices can request an interrupt. • A single interrupt request line may used for this purpose. • All devices are connected to the line via switches to ground.
  • 12. • To request an interrupt, a device closes its associated switch. • If all interrupt-request signals INTR1 to INTRn are inactive, that is, if all switches are open, the voltage on the interrupt request line will equal to Vdd. This is an inactivate state of the line. • When a device requests an interrupt by closing its switch, the voltage on the line drops to 0, causing the interrupt- request signal INTR received by the processor to go to 1. • If closing of one (or) more switches that cause the line value to drop to 0, the value of logical OR of the request from individual devices, that is • INTR=INTR1+INTR2+INTR3.............. • Use the complement form of INTR to name of the interrupt signal on the common line because this signal is active in the low voltage state
  • 13. 1.Enabling and disabling interrupts • A processor has the facility to enable and disable interrupts as desired. • When a device request the interrupt during the processor service for another interrupt, the result cause the processor enter into the infinite loop. • This can be handled by the following 2 ways:  The processor ignore the interrupt request line(INTR) until the Interrupt Service Routine(ISR) is completed.  This can be done by using interrupt-Disable as first instruction and interrupt-Enable as the last instruction.
  • 14. • The second option is processor automatically disable interrupts before starting the execution of the ISR. • The status register PS stored in the stack with PC value. • The processor set this register bit 1 when the interrupt accept and when a return instruction is executed, the contents of the PS are cleared (0)and stored in the stack again.
  • 15. 2.Handling Multiple Devices • When the number of devices initiating interrupts. • For example, device X may request an interrupt while an interrupt caused by device Y is being serviced. • Hence all the device using the common interrupt line. • Additional information require to identify the device that activated the request. • When the two devices activated the line at the same time, we must break up the tie and chose one the device request among two. Some scheme should be used by the processor.
  • 16. 2.1Polling scheme • The device that raises the interrupt will set one of the bit (IRQ) in status register to 1. • The processor will poll the devices to find which raised an interrupt first. Disadvantage: • Time spend in interrogating the IRQ bits of the devices that may not be requesting any service.
  • 17. 2.2Vectored interrupts • To reduce the time involved in the polling scheme, a device requesting an interrupt may identify itself directly to the processor. • A device can send a special code to the processor over the bus. The code is used to identify the device. • If the interrupt produces a CALL to a predetermined memory location, which is the starting address of ISR, then that address is called vectored address and such interrupts are called vectored interrupts.
  • 18. 3.Interrupt priority • When a interrupt arrives from one (or) more devices simultaneously, the processor has to decide which request should be serviced first. • The processor takes this decision with the help of interrupt priorities. • The processor accepts interrupt request having highest priority. • Each request assign a different priority level. • The request received from the interrupt request line are sent to a priority arbitration circuit in the processor. • The request is accepted only if it has a higher priority level than that currently assigned to the processor.
  • 20. 4.Controlling device request • The processor allow only the input / output devices requested(interrupt), that are being used by a given program. • Other devices should not be allowed to generate interrupt requests even though they are ready to transfer the data. • Hence, we need a mechanism in the interface circuits of individual devices to control whether the device is allowed to generate an interrupt request. • Two mechanism for control request: 1. One is at the device end- interrupt enable bit in the control register(IRQ). 2. Processor end- enable bit in the program status register(PS) or priority structure determine whether a given interrupt request will be accepted.
  • 21. • System properties->View resource by type