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This document discusses arithmetic functions in digital circuits. It begins by introducing iterative combinational circuits and binary adders such as half adders, full adders, and ripple carry adders. It then covers binary subtraction using two's complement representation and signed binary numbers. The document explains various signed number representations including signed magnitude and signed complement. It provides examples of addition and subtraction for signed integers in these representations.
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- 1. Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Chapter 4 – Arithmetic Functions Logic and Computer Design Fundamentals
- 2. Chapter 4 2 Overview Iterative combinational circuits Binary adders • Half and full adders • Ripple carry and carry lookahead adders Binary subtraction Binary adder-subtractors • Signed binary numbers • Signed binary addition and subtraction • Overflow Binary multiplication Other arithmetic functions • Design by contraction
- 3. Chapter 4 3 Iterative Combinational Circuits Arithmetic functions • Operate on binary vectors • Use the same subfunction in each bit position Can design functional block for subfunction and repeat to obtain functional block for overall function Cell - subfunction block Iterative array - a array of interconnected cells An iterative array can be in a single dimension (1D) or multiple dimensions
- 4. Chapter 4 4 Block Diagram of a 1D Iterative Array Example: n = 32 • Number of inputs = ? • Truth table rows = ? • Equations with up to ? input variables • Equations with huge number of terms • Design impractical! Iterative array takes advantage of the regularity to make design feasible
- 5. Chapter 4 5 Functional Blocks: Addition Binary addition used frequently Addition Development: • Half-Adder (HA), a 2-input bit-wise addition functional block, • Full-Adder (FA), a 3-input bit-wise addition functional block, • Ripple Carry Adder, an iterative array to perform binary addition, and • Carry-Look-Ahead Adder (CLA), a hierarchical structure to improve performance.
- 6. Chapter 4 6 Functional Block: Half-Adder A 2-input, 1-bit width binary adder that performs the following computations: A half adder adds two bits to produce a two-bit sum The sum is expressed as a sum bit , S and a carry bit, C The half adder can be specified as a truth table for S and C X 0 0 1 1 + Y + 0 + 1 + 0 + 1 C S 0 0 0 1 0 1 1 0 X Y C S 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0
- 7. Chapter 4 7 Logic Simplification: Half-Adder The K-Map for S, C is: This is a pretty trivial map! By inspection: and These equations lead to several implementations. Y X 0 1 321 1 S Y X 0 1 32 1 C )YX()YX(S YXYXYXS ++= =+= )(C YXC )YX( = =
- 8. Chapter 4 8 Five Implementations: Half-Adder We can derive following sets of equations for a half- adder: (a), (b), and (e) are SOP, POS, and XOR implementations for S. In (c), the C function is used as a term in the AND- NOR implementation of S, and in (d), the function is used in a POS term for S. YXC )(S)c( YXC )YX()YX(S)b( YXC YXYXS)a( YXC = = = ++= = += + YXC YXS)e( )YX(C C)YX(S)d( = = += += C
- 9. Chapter 4 9 Implementations: Half-Adder The most common half adder implementation is: (e) A NAND only implementation is: YXC YXS = = )(C C)YX(S )YX( = += X Y C S X Y C S
- 10. Chapter 4 10 Functional Block: Full-Adder A full adder is similar to a half adder, but includes a carry-in bit from lower stages. Like the half-adder, it computes a sum bit, S and a carry bit, C. • For a carry-in (Z) of 0, it is the same as the half-adder: • For a carry- in (Z) of 1: Z 0 0 0 0 X 0 0 1 1 + Y + 0 + 1 + 0 + 1 C S 0 0 0 1 0 1 1 0 Z 1 1 1 1 X 0 0 1 1 + Y + 0 + 1 + 0 + 1 C S 0 1 1 0 1 0 1 1
- 11. Chapter 4 11 Logic Optimization: Full-Adder Full-Adder Truth Table: Full-Adder K-Map: X Y Z C S 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 X Y Z 0 1 3 2 4 5 7 6 1 1 1 1 S X Y Z 0 1 3 2 4 5 7 6 1 11 1 C
- 12. Chapter 4 12 Equations: Full-Adder From the K-Map, we get: The S function is the three-bit XOR function (Odd Function): The Carry bit C is 1 if both X and Y are 1 (the sum is 2), or if the sum is 1 and a carry-in (Z) occurs. Thus C can be re-written as: The term X·Y is carry generate. The term XY is carry propagate. ZYZXYXC ZYXZYXZYXZYXS ++= +++= ZYXS = Z)YX(YXC +=
- 13. Chapter 4 13 Implementation: Full Adder Full Adder Schematic Here X, Y, and Z, and C (from the previous pages) are A, B, Ci and Co, respectively. Also, G = generate and P = propagate. Note: This is really a combination of a 3-bit odd function (for S)) and Carry logic (for Co): (G = Generate) OR (P =Propagate AND Ci = Carry In) Co = G + P · Ci Ai Bi Ci Ci+1 Gi Pi Si
- 14. Chapter 4 14 Binary Adders To add multiple operands, we ―bundle‖ logical signals together into vectors and use functional blocks that operate on the vectors Example: 4-bit ripple carry adder: Adds input vectors A(3:0) and B(3:0) to get a sum vector S(3:0) Note: carry out of cell i becomes carry in of cell i + 1 Description Subscript 3 2 1 0 Name Carry In 0 1 1 0 Ci Augend 1 0 1 1 Ai Addend 0 0 1 1 Bi Sum 1 1 1 0 Si Carry out 0 0 1 1 Ci+1
- 15. Chapter 4 15 4-bit Ripple-Carry Binary Adder A four-bit Ripple Carry Adder made from four 1-bit Full Adders: B3 A 3 FA B2 A 2 FA B1 S3C4 C0 C3 C2 C1 S2 S1 S0 A 1 FA B0 A 0 FA
- 16. Chapter 4 16 Unsigned Subtraction Algorithm: • Subtract the subtrahend N from the minuend M • If no end borrow occurs, then M N, and the result is a non-negative number and correct. • If an end borrow occurs, the N > M and the difference M - N + 2n is subtracted from 2n, and a minus sign is appended to the result. Examples: 0 1 1001 0100 - 0111 - 0111 0010 1101 10000 - 1101 (-) 0011
- 17. Chapter 4 17 Unsigned Subtraction (continued) The subtraction, 2n - N, is taking the 2’s complement of N To do both unsigned addition and unsigned subtraction requires: Quite complex! Goal: Shared simpler logic for both addition and subtraction Introduce complements as an approach A B Binary adder Binary subtractor Selective 2's complementer Quadruple 2-to-1 multiplexer Result Borrow Complement S 0 1 Subtract/Add
- 18. Chapter 4 18 Complements Two complements: • Diminished Radix Complement of N (r - 1)’s complement for radix r 1’s complement for radix 2 Defined as (rn - 1) - N • Radix Complement r’s complement for radix r 2’s complement in binary Defined as rn - N Subtraction is done by adding the complement of the subtrahend If the result is negative, takes its 2’s complement
- 19. Chapter 4 19 Binary 1's Complement For r = 2, N = 011100112, n = 8 (8 digits): (rn – 1) = 256 -1 = 25510 or 111111112 The 1's complement of 011100112 is then: 11111111 – 01110011 10001100 Since the 2n – 1 factor consists of all 1's and since 1 – 0 = 1 and 1 – 1 = 0, the one's complement is obtained by complementing each individual bit (bitwise NOT).
- 20. Chapter 4 20 Binary 2's Complement For r = 2, N = 011100112, n = 8 (8 digits), we have: (rn ) = 25610 or 1000000002 The 2's complement of 01110011 is then: 100000000 – 01110011 10001101 Note the result is the 1's complement plus 1, a fact that can be used in designing hardware
- 21. Chapter 4 21 Alternate 2’s Complement Method Given: an n-bit binary number, beginning at the least significant bit and proceeding upward: • Copy all least significant 0’s • Copy the first 1 • Complement all bits thereafter. 2’s Complement Example: 10010100 • Copy underlined bits: 100 • and complement bits to the left: 01101100
- 22. Chapter 4 22 Subtraction with 2’s Complement For n-digit, unsigned numbers M and N, find M - N in base 2: • Add the 2's complement of the subtrahend N to the minuend M: M + (2n - N) = M - N + 2n • If M N, the sum produces end carry rn which is discarded; from above, M - N remains. • If M < N, the sum does not produce an end carry and, from above, is equal to 2n - ( N - M ), the 2's complement of ( N - M ). • To obtain the result - (N – M) , take the 2's complement of the sum and place a - to its left.
- 23. Chapter 4 23 Unsigned 2’s Complement Subtraction Example 1 Find 010101002 – 010000112 01010100 01010100 – 01000011 + 10111101 00010001 The carry of 1 indicates that no correction of the result is required. 1 2’s comp
- 24. Chapter 4 24 Unsigned 2’s Complement Subtraction Example 2 Find 010000112 – 010101002 01000011 01000011 – 01010100 + 10101100 11101111 00010001 The carry of 0 indicates that a correction of the result is required. Result = – (00010001) 0 2’s comp 2’s comp
- 25. Chapter 4 25 Signed Integers Positive numbers and zero can be represented by unsigned n-digit, radix r numbers. We need a representation for negative numbers. To represent a sign (+ or –) we need exactly one more bit of information (1 binary digit gives 21 = 2 elements which is exactly what is needed). Since computers use binary numbers, by convention, the most significant bit is interpreted as a sign bit: s an–2 a2a1a0 where: s = 0 for Positive numbers s = 1 for Negative numbers and ai = 0 or 1 represent the magnitude in some form.
- 26. Chapter 4 26 Signed Integer Representations Signed-Magnitude – here the n – 1 digits are interpreted as a positive magnitude. Signed-Complement – here the digits are interpreted as the rest of the complement of the number. There are two possibilities here: • Signed 1's Complement Uses 1's Complement Arithmetic • Signed 2's Complement Uses 2's Complement Arithmetic
- 27. Chapter 4 27 Signed Integer Representation Example r =2, n=3 Number Sign -Mag. 1's Comp. 2's Comp. +3 011 011 011 +2 010 010 010 +1 001 001 001 +0 000 000 000 – 0 100 111 — – 1 101 110 111 – 2 110 101 110 – 3 111 100 101 – 4 — — 100
- 28. Chapter 4 28 Signed-Magnitude Arithmetic If the parity of the three signs is 0: 1. Add the magnitudes. 2. Check for overflow (a carry out of the MSB) 3. The sign of the result is the same as the sign of the first operand. If the parity of the three signs is 1: 1. Subtract the second magnitude from the first. 2. If a borrow occurs: • take the two’s complement of result • and make the result sign the complement of the sign of the first operand. 3. Overflow will never occur.
- 29. Chapter 4 29 Example 1: 0010 +0101 Example 2: 0010 +1101 Example 3: 1010 - 0101 Sign-Magnitude Arithmetic Examples
- 30. Chapter 4 30 Signed-Complement Arithmetic Addition: 1. Add the numbers including the sign bits, discarding a carry out of the sign bits (2's Complement), or using an end-around carry (1's Complement). 2. If the sign bits were the same for both numbers and the sign of the result is different, an overflow has occurred. 3. The sign of the result is computed in step 1. Subtraction: Form the complement of the number you are subtracting and follow the rules for addition.
- 31. Chapter 4 31 Example 1: 1101 +0011 Example 2: 1101 -0011 Signed 2’s Complement Examples
- 32. Chapter 4 32 2’s Complement Adder/Subtractor Subtraction can be done by addition of the 2's Complement. 1. Complement each bit (1's Complement.) 2. Add 1 to the result. The circuit shown computes A + B and A – B: For S = 1, subtract, the 2’s complement of B is formed by using XORs to form the 1’s comp and adding the 1 applied to C0. For S = 0, add, B is passed through unchanged FA FA FA FA S B3 C3 S2 S1 S0S3C4 C2 C1 C0 A 3 B2 A 2 B1 A 1 B0 A 0
- 33. Chapter 4 33 Overflow Detection Overflow occurs if n + 1 bits are required to contain the result from an n-bit addition or subtraction Overflow can occur for: • Addition of two operands with the same sign • Subtraction of operands with different signs Signed number overflow cases with correct result sign 0 0 1 1 + 0 - 1 - 0 + 1 0 0 1 1 Detection can be performed by examining the result signs which should match the signs of the top operand
- 34. Chapter 4 34 Overflow Detection Signed number cases with carries Cn and Cn-1 shown for correct result signs: 0 0 0 0 1 1 1 1 0 0 1 1 + 0 -1 -0 +1 0 0 1 1 Signed number cases with carries shown for erroneous result signs (indicating overflow): 0 1 0 1 1 0 1 0 0 0 1 1 + 0 - 1 -0 + 1 1 1 0 0 Simplest way to implement overflow V = Cn + Cn - 1 This works correctly only if 1’s complement and the addition of the carry in of 1 is used to implement the complementation! Otherwise fails for - 10 ... 0