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Mos transistor
This document discusses MOS transistor theory, including MOS structure, ideal and non-ideal I-V characteristics, capacitance models, and delay models. It describes how MOS transistors operate in different modes depending on terminal voltages and how carrier mobility and channel charge determine current in linear and saturation regions. Non-ideal effects like velocity saturation, body effect, and leakage currents are also covered. The document concludes with discussions of pass transistors, tri-state inverters, and using resistor-capacitor models to estimate delay.
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Mos transistor
- 1. 1 1 Slides adapted from: N.Weste, D. Harris, CMOS VLSI Design, Ā© Addison-Wesley, 3/e, 2004 MOS Transistor Theory 2 Outline The Big Picture MOS Structure Ideal I-V Charcteristics MOS Capacitance Models Non ideal I-V Effects Pass transistor circuits Tristate Inverter Switch level RC Delay Models
- 2. 2 3 The Big Picture Sofar, we have treated transistors as ideal switches An ON transistor passes a finite amount of current Depends on terminal voltages Derive current-voltage (I-V) relationships Transistor gate, source, drain all have capacitance I = C (āV/āt) āt = (C/I) āV Capacitance and current determine speed 4 MOS Transistor Symbol
- 3. 3 5 MOS Structure Gate andbody form MOS capacitor Operating modes Accumulation Depletion Inversion 6 nMOS Transistor Terminal Voltages Mode of operation depends on Vg, Vd, Vs Vgs = Vg ā Vs Vgd = Vg ā Vd Vds = Vd ā Vs = Vgs - Vgd Source and drain are symmetric diffusion terminals By convention, source is terminal at lower voltage Hence Vds ā„ 0 nMOS body is grounded. First assume source is 0 too. Three regions of operation Cutoff Linear Saturation Vg Vs Vd VgdVgs Vds +- + - + -
- 4. 4 7 nMOS in cutoffoperation mode No channel Ids = 0 8 nMOS in linear operation mode Channel forms Current flows from D to S e- from S to D Ids increases with Vds Similar to linear resistor
- 5. 5 9 nMOS in Saturationoperation mode Channel pinches off Ids independent of Vds We say current saturates Similar to current source 10 pMOS Transistor
- 6. 6 11 I-V Characteristics (nMOS) InLinear region, Ids depends on How much charge is in the channel? How fast is the charge moving? 12 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion: Gate ā oxide ā channel Qchannel = CV C = Cg = ĪµoxWL/tox = coxWL V = Vgc ā Vt = (Vgs ā Vds/2) ā Vt cox = Īµox / tox
- 7. 7 13 Carrier velocity Charge iscarried by e- Carrier velocity v proportional to lateral E-field between source and drain v = ĀµE Āµ called mobility E = Vds/L Time for carrier to cross channel: t = L / v 14 nMOS Linear I-V Now we know How much charge Qchannel is in the channel How much time t each carrier takes to cross channel ox 2 2 ds ds gs t ds ds gs t ds Q I t W V C V V V L V V V V Āµ Ī² = ļ£« ļ£¶= ā āļ£¬ ļ£· ļ£ ļ£ø ļ£« ļ£¶= ā āļ£¬ ļ£· ļ£ ļ£ø ox= W C L Ī² Āµ =
- 8. 8 15 nMOS Saturation I-V IfVgd < Vt, channel pinches off near drain When Vds > Vdsat = Vgs ā Vt Now drain voltage no longer increases current ( ) 2 2 2 dsat ds gs t dsat gs t V I V V V V V Ī² Ī² ļ£« ļ£¶= ā āļ£¬ ļ£· ļ£ ļ£ø = ā 16 nMOS I-V Summary ( ) 2 cutoff linear saturatio 0 2 2 n gs t ds ds gs t ds ds dsat gs t ds dsat V V V I V V V V V V V V V Ī² Ī² ļ£± ļ£“ < ļ£“ ļ£“ ļ£« ļ£¶= ā ā <ļ£¬ ļ£·ļ£² ļ£ ļ£øļ£“ ļ£“ ā >ļ£“ļ£³ first order transistor models
- 9. 9 17 I-V characteristics ofnMOS Transistor 18 Example 0.6 Āµm process from AMI Semiconductor tox = 100 Ć m = 350 cm2/V*s Vt = 0.7 V Plot Ids vs. Vds Vgs = 0, 1, 2, 3, 4, 5 Use W/L = 4/2 Ī» ( ) 14 2 8 3.9 8.85 10 350 120 / 100 10 ox W W W C A V L L L Ī² Āµ Āµ ā ā ļ£« ļ£¶ā¢ ā ļ£« ļ£¶ = = =ļ£¬ ļ£·ļ£¬ ļ£· ā ļ£ ļ£øļ£ ļ£ø 0 1 2 3 4 5 0 0.5 1 1.5 2 2.5 Vds Ids (mA) Vgs = 5 Vgs = 4 Vgs = 3 Vgs = 2 Vgs = 1
- 10. 10 19 pMOS I-V Characteritics Alldopings and voltages are inverted for pMOS Mobility Āµp is determined by holes Typically 2-3x lower than that of electrons Āµn 120 cm2/V*s in AMI 0.6 mm process Thus pMOS must be wider to provide same current In this class, assume Āµn / Āµp = 2 20 pMOS I-V Summary ( ) 2 cutoff linear saturatio 0 2 2 n gs t ds ds gs t ds ds dsat gs t ds dsat V V V I V V V V V V V V V Ī² Ī² ļ£± ļ£“ < ļ£“ ļ£“ ļ£« ļ£¶= ā ā <ļ£¬ ļ£·ļ£² ļ£ ļ£øļ£“ ļ£“ ā >ļ£“ļ£³ first order transistor models
- 11. 11 21 I-V characteristics ofpMOS Transistor 22 Capacitances of a MOS Transistor Any two conductors separated by an insulator have capacitance Gate to channel capacitor is very important Creates channel charge necessary for operation (intrinsic capacitance) Source and drain have capacitance to body (parasitic capacitance) Across reverse-biased diodes Called diffusion capacitance because it is associated with source/drain diffusion
- 12. 12 23 Gate Capacitance When thetransistor is off, the channel is not inverted Cg = Cgb = ĪµoxWL/tox = CoxWL Letās call CoxWL = C0 When the transistor is on, the channel extends from the source to the drain (if the transistor is unsaturated, or to the pinchoff point otherwise) Cg = Cgb + Cgs + Cgd 24 Gate Capacitance In reality the gate overlaps source and drain. Thus, the gate capacitance should include not only the intrinsic capacitance but also parasitic overlap capacitances: Cgs(overlap) = Cox W LD Cgs(overlap) = Cox W LD
- 13. 13 25 Detailed Gate Capacitance 2/3C0+ CoxWLDC0/2 + CoxWLDCoxWLDCgs (total) CoxWLDC0/2 + CoxWLDCoxWLDCgd (total) 00C0Cgb (total) SaturationLinearCutoffCapacitance Source: M-S Kang, Y. Leblebici, CMOS Digital ICs, 3/e, 2003, McGraw-Hill 26 Diffusion Capacitance Csb, Cdb Undesired capacitance (parasitic) Due to the reverse biased p-n junctions between source diffusion and body and drain diffusion and body Capacitance depends on area and perimeter Use small diffusion nodes Comparable to Cg for contacted diffusion Ā½ Cg for uncontacted Varies with process
- 14. 14 27 Lumped representation ofthe MOSFET capacitances 28 Non-ideal I-V effects The saturation current increases less than quadratically with increasing Vgs Velocity saturation Mobility degradation Channel length modulation Body Effect Leakage currents Sub-threshold conduction Junction leakage Tunneling Temperature Dependence Geometry Dependence
- 15. 15 29 Velocity saturation and mobilitydegradation At strong lateral fields resulting from high Vds, drift velocity rolls off due to carrier scattering and eventually saturates Strong vertical fields resulting from large Vgs cause the carriers to scatter against the surface and also reduce the carrier mobility. This effect is called mobility degradation 30 Channel length modulation The reverse biased p-n junction between the drain and the body forms a depletion region with length Lā that increases with Vdb. The depletion region effectively shorten the channel length to: Leff = L ā Lā Assuming the source voltage is close to the body votage Vdb ~ Vsb. Hence, increasing Vds decrease the effective channel length. Shorter channel length results in higher current
- 16. 16 31 Body Effect The potentialdifference between source and body Vsb affects (increases) the threshold voltage Threshold voltage depends on: Vsb Process Doping Temperature 32 Subthreshold Conduction The ideal transistor I-V model assumes current only flows from source to drain when Vgs > Vt. In real transistors, current doesnāt abruptly cut off below threshold, but rather drop off exponentially This leakage current when the transistor is nominally OFF depends on: process (Īµox, tox) doping levels (NA, or ND) device geometry (W, L) temperature (T) ( Subthreshold voltage (Vt) )
- 17. 17 33 Junction Leakage The p-njunctions between diffusion and the substrate or well for diodes. The well-to-substrate is another diode Substrate and well are tied to GND and VDD to ensure these diodes remain reverse biased But, reverse biased diodes still conduct a small amount of current that depends on: Doping levels Area and perimeter of the diffusion region The diode voltage 34 Tunneling There is a finite probability that carriers will tunnel though the gate oxide. This result in gate leakage current flowing into the gate The probability drops off exponentially with tox For oxides thinner than 15-20 Ć , tunneling becomes a factor
- 18. 18 35 Temperature dependence Transistor characteristicsare influenced by temperature Āµ decreases with T Vt decreases linearly with T Ileakage increases with T ON current decreases with T OFF current increases with T Thus, circuit performances are worst at high temperature 36 Geometry Dependence Layout designers draw transistors with Wdrawn, Ldrawn Actual dimensions may differ from some factor XW and XL The source and drain tend to diffuse laterally under the gate by LD, producing a shorter effective channel Similarly, diffusion of the bulk by WD decreases the effective channel width In process below 0.25 Āµm the effective length of the transistor also depends significantly on the orientation of the transistor
- 19. 19 37 Impact of non-idealI-V effects Threshold is a significant fraction of the supply voltage Leakage is increased causing gates to consume power when idle limits the amount of time that data is retained Leakage increases with temperature Velocity saturation and mobility degradation result in less current than expected at high voltage No point in trying to use high VDD to achieve fast transistors Transistors in series partition the voltage across each transistor thus experience less velocity saturation Tend to be a little faster than a single transistor Two nMOS in series deliver more than half the current of a single nMOS transistor of the same width Matching: same dimension and orientation 38 Pass Transistors nMOS pass transistors pull no higher than VDD-Vtn Called a degraded ā1ā Approach degraded value slowly (low Ids) pMOS pass transistors pull no lower than |Vtp| Called a degraded ā0ā Approach degraded value slowly (low Ids)
- 20. 20 39 Pass transistor Circuits 40 Transmissiongate ON resistance
- 21. 21 41 Tri-state Inverter If theoutput is tri-stated but A toggles, charge from the internal nodes (= caps) may disturb the floating output node 42 Effective resistance of a transistor First-order transistor models have limited value Not accurate enough for modern transistors Too complicated for hand analysis Simplification: treat transistor as resistor Replace Ids(Vds, Vgs) with effective resistance R Ids = Vds/R R averaged across switching range of digital gate Too inaccurate to predict current at any given time But good enough to predict RC delay (propagation delay of a logic gate)
- 22. 22 43 RC Values Capacitance C =Cg = Cs = Cd = 2 fF/Āµm of gate width Values similar across many processes Resistance R ā 6 Kā¦*Āµm in 0.6um process Improves with shorter channel lengths Unit transistors May refer to minimum contacted device (4/2 Ī») or maybe 1 Āµm wide device Doesnāt matter as long as you are consistent 44 RC Delay Models Use equivalent circuits for MOS transistors ideal switch + capacitance and ON resistance unit nMOS has resistance R, capacitance C unit pMOS has resistance 2R, capacitance C Capacitance proportional to width Resistance inversely proportional to width
- 23. 23 45 Switch level RCmodels 46 Inverter Delay Estimate Estimate the delay of a fanout-of-1 inverter delay = 6RC
- 24. 24 47 Resistance of aunit transmission gate The effective resistance of a transmission gate is the parallel of the resistance of the two transistor Approximately R in both directions Transmission gates are commonly built using equal-sized transistors Boosting the size of the pMOS only slightly improve the effective resistance while significantly increasing the capacitance 48 Summary Models are only approximations to reality, not reality itself Models cannot be perfectly accurate Little value in using excessively complicated models, particularly for hand calculations To first order current is proportional to W/L But, in modern transistors Leff is shorter than Ldrawn Doubling the Ldrawn reduces current more than a factor of two Two series transistors in a modern process deliver more than half the current of a single transistor Use Transmission gates in place of pass transistors Transistor speed depends on the ratio of current to capacitance Sources of capacitance (voltage dependents) Gate capacitance Diffusion capacitance