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![eMMC Interface
NXP
i.MX6
eMMC
Flash
SD3 Data [ 3 – 0 ]
SD3 Reset
SD3 Clock
SD3 CMD](https://image.slidesharecdn.com/imx6udooboardhardware-170819015603/85/NXP-i-MX6-Multi-Media-Processor-Peripherals-10-320.jpg)
![Micro SD Card Interface
NXP
i.MX6
Micro SD
Card
SD Data [ 3 – 0 ]
SD Reset
SD Clock
SD CMD
SD CD](https://image.slidesharecdn.com/imx6udooboardhardware-170819015603/85/NXP-i-MX6-Multi-Media-Processor-Peripherals-19-320.jpg)
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NXP i.MX6 Multi Media Processor & Peripherals
The document provides an overview of the UDOO Neo board, which is based on the NXP i.MX6 SoloX core processor featuring an ARM Cortex-A9 architecture. It details hardware specifications including memory, interfaces such as USB, HDMI, I2C, UART, and communication protocols, as well as functionalities like video encoding and decoding. Additionally, it covers the board's general purpose I/O capabilities and debugging features via secure JTAG.
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NXP i.MX6 Multi Media Processor & Peripherals
- 1. NXP IMX6 Processor Udoo– Neo Board Overview
- 2. Introduction • Development platformbased on NXP IMX6 SoloX Core processor – ARM Cortex-A9 Single core upto 1GHz • Micro SD Card • 1 Gbyte DDR3 SDRAM • HDMI Video / Audio Output • 10 / 100 Mbps Ethernet • USB OTG • USB Host • 802.11 WiFi Interface • Bluetooth 4.0
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- 5. NXP IMX6 SoloXProcessor • ARM Cortex-A9 upto 1GHz • 32 Kbyte L1 instruction cache • 32 Kbyte L1 Data Cache • Cortex-A9 NEON Media Processing Engine • 2D & 3D Graphics Processor • Video Decoder / Encoder – 1080p60 Decode – 1080p60 Encode, Dual 720p60 Encode • DDR & NAND Memory Interface
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- 7. DDR3 SDRAM • DoubleData Rate 3 Synchronous Dynamic RAM • 4 x 256 MB DDR3 SDRAM • Address Lines multiplexed with ROW & Column • 16-Bit Data Bus • Differential Clock • DDR3 Control Signals – Chip Select – Row / Column Address Strobes • Data Mask
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- 9. eMMC Flash • FlashMemory & MMC Controller into a single Chip • Used as embedded non-volatile memory • Permanent attached to board • Does not support SPI protocol • All mobile phone & tablets uses this as internal memory as well as for images.
- 10. eMMC Interface NXP i.MX6 eMMC Flash SD3 Data[ 3 – 0 ] SD3 Reset SD3 Clock SD3 CMD
- 11. General Purpose I/O •Generic Pin on an IC / Board • Configured as Input or Output • Can be enabled / disabled • Logic Level – High – Low • Input values are readable • Output values are writable / readable • Input configured pins also can be used as Interrupt • No predefined purpose
- 12. Serial Peripheral Interface •Synchronous Serial Communication Interface • Used for Short distance. Basically with in the board • Full duplex mode with master slave architecture • Also called as four-wire bus • Pins – MISO : Master Input Slave Output – MOSI : Master Output Slave Input – SCK : Serial Clock – SS : Slave Select
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- 14. Inter Integrated CircuitInteface • Multi master, multi slave serial interface bus • Uses only two bi-directional open drain lines – SDA : Serial Data Line – SCL : Serial Clock Line • Since lines are open drain, these pins needs to be pulled high. – Normally pull up resistor will be 4.7 K / 10K
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- 16. UART • Univeral AsynchronuosReceiver / Transmitter • Supports NRZ encoding format • 7 or 8 bit data • 1 or 2 Stop bits • Hardware Flow Control – RTS – Request to Send – CTS – Clear to Send • Programmable Parity ( even, odd and none ) • RS485, RS232 compatible
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- 18. Secure Digital Interface •Provides interface with SD/SDIO/MMC Cards • Handles bus transaction with SD / SDIO / MMC Cards • Evolution of old MMC Technology • Provides Security, Capacity, Performance • Interface categorization as follows, – Memory Card – IO Card – Combo Card ( Both memory & IO )
- 19. Micro SD CardInterface NXP i.MX6 Micro SD Card SD Data [ 3 – 0 ] SD Reset SD Clock SD CMD SD CD
- 20. HDMI • High DefinitionMulti Media Interface • Transfers uncompressed Video, Audio and Data using a Single Cable • High bandwidth Data Content Protection • HDMI System has one to one connectivity with – HDMI Source which is the transmitter – HDMI Sinks which is the receiver • Data Display Channel – Configuration & Data Exchange in HDMI
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- 22. Parallel RGB LCDInterface • Parallel Video Interface • Supports upto 24 Bit Data • Supports BT.656 Data format ( 8 Bit ) • Supports BT.1120 Data format ( 16 Bit ) • Supports HDTV standards SMPTE274 • Supports HDTV Standards SMPTE296 • RGB Color Depth fully configurable upto 8 Bit / color value
- 23. Parallel RGB LCDInterface
- 24. LVDS Display Bridge •Linear Voltage Differential Signaling • Used to connect with Display with LVDS receiver • Featured with Synchronization & Control • Data arrangement will be based on external Display • LVDS Display Port – 1 Clock Channel – 4 Data Channel • Each pair contains LVDS Special differential pads
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- 26. RGMII • Reduced Gigabit Media Independent Interface • Used to interface between Ethernet MAC & PHY • Half the number of data pins used in GMII • Data clocking will be done at both rising and falling edges of the clock • Carrier Sense / Collision Detection • Management Interface – Management Interface Clock ( MDC ) – Management Interface I/O ( MDIO )
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- 28. USB Host • USB2.0 Host controller • 2 x USB 2.0 Host Ports • Host Mode Event Handler • USB Enhanced Host Controller Interface • USB Host uses Master / Slave Architecture • USB Host – Master • USB Device – Slave
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- 30. USB OTG • USBOn – The – GO • Allows devices to switch back & forth between USB Host & Device • Will acts as Host when device connected • Will acts as USB Device when it is connected with Host
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- 32. Secure JTAG • Providesdebug & test control with maximum security • Joint Test Access Group • IEEE Standard 1149.1 v2001 ( JTAG ) • Debug related control & status • Putting the selected cores into reset / monitor • JTAG Boundary Scan – Provides access to all logic signals of complex IC – Provides access to device pins
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